wu Integrated Circuit Systems, Inc. ICS5300 GENDAC Preliminary 8-bit Integrated Clock-LUT-DAC General Description The ICS5300 GENDAC isa combination of dual program- mable clock generators, a 256 x 18-bit RAM, and a triple 8-bit video DAC. The GENDAC supports 8-bit pseudo color applications, as well as 15-bit, 16-bit and 24-bit True Color bypass for high speed, direct access to the DACs. The RAM makes it possible to display 256 colors selected froma possible 262, 144 colors. The dual clock generators use Phase Locked Loop (PLL) technology to provide programmable frequencies for use in the graphics sub- system. The video clock contains 8 frequencies, 6 of which are programmable by the user. The memory clock has one programmable frequency location. The three 8-bit DACs on the ICS5300 are capable of driving singly or doubly-terminated 75Q loads to nomi- nal 0- 0.7 volts at pixel rates up to 135 MHz. Differential and integral linearity errors are less than 1 LSB over full temperature and Vpp ranges. Monotonicity is guaran- teed by design. On-chip pixel mask register allows dis- played colors to be changed in a single write cycle rather than by modifying the color palette. ICS is the world leader in all aspects of frequency (clock) generation for graphics, using patented techniques to produce low jitter video timing. Block Diagram Features Triple video DAC, dual clock generator, and a color palette 24,16, 15, or 8-bit pseudo color pixel mode supports True Color, Hi-Color, and VGA modes High speed 256 x 18 color palette (135 MHz) with bypass mode and 8-bit DACs Two fixed, six programmable video (pixel) clock frequencies (CLK0) * One programmable memory (controller) clock frequency (CLK1) * DAC power down in blanking mode Low power operation Anti-sparkle circuitry On-chip loop filters reduce external components Standard CPU interface * Single external crystal (typically 14.318 MHz) * Monitor Sense * Internal voltage reference 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions * Very low clock jitter IcSIS002ICS5300 GENDAC Preliminary . , , , Bas gg5 Pin Configuration KE ZGRRR4MES] SFOHOOUVVUUOKXK / OM HON KH HOA a Oo RD* | 7 ses 39| BLANK* DO} 8 38} PCLK D1| 9 37| P7 D2 | 10 GENDAC I 36| P6 ba | 12 Ics5300 8 D5 | 13 33| P3 D6 | 14 32} P2 D7] 15 31} Pl RSO | 16 30| PO RS1JIRARANARAARAAAR 29] DVDD N ee fe my B2SBG SRR 225 mame Uos Pin Description (68 pin PLCC) Symbol Pin # Type Description CS1 1 Input Clock select 1. The status of CSO-2 determine which frequency is selected on the CLKO (video) output. CS2 2 Input Clock select 2. The status of CSO-2 determine which frequency is selected on the CLKO (video) output. CGND 3 - Ground for clock circuits. Connect to ground. SENSE* 4 Output Monitor Sense, active low. This pin is low when any of the red, green, or blue outputs have exceeded 335mV. The chip has on-board compara- tors and an internal 335mV voltage reference. This is used to detect monitor type. CVDD 5 - Clock Power Supply. Connect to DVDD WR* 6 Input RAM/PLL Write Enable, active low. This signal controls the timing of the write operation on the microprocessor interface inputs, DO-D7. RD* 7 Input RAM/PLL Read Enable, active low. This is the READ bus control signal. When active, any information present on the internal data bus is available on the Data I/O lines, D0O-D7. DO - D7 8-15 1/O System data bus I/O. These bidirectional Data I/O lines are used by the host microprocessor to write (using active low WR*) information into, and read (using active low RD*) information from the six internal registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL Parameter, and Command). During the write cycle, the rising edge of WR* latches the data into the selected register (set by the status of the three RS pins). The rising edge of RD* determines the end of the read cycle. When RD* is a logical high, the Data I/O lines no longer contain information from the selected register and will go into a tri-state mode. 11493ICS5300 GENDAC Preliminary Pin Description (continued) Symbol Pin # Type Description RSO 16 Input Register Address Select 0. These inputs control the selection of one of the RS1 17 Input six internal registers. They are sampled on the falling edge of the active RS2 18 Input enable signal (RD* or WR*). CGND 19 - Ground for clock circuits. Connect to ground CVDD 20 - Clock Power Supply. Connect to AVDD RED 21 Output Color Signals. These three signals are the DACs' analog outputs. Each GREEN 22 | Output DAC is composed of several current sources. The outputs of each of the BLUE 23 Output sources are added together according to the applied binary value. These outputs are typically used to drive a CRT monitor. AVDD 24 - Analog power supply. Connect to AVDD RSET 25 Input Resistor Set. This pin is used to set the current level in the analog outputs. It is usually connected through a 140Q, 1% resistor to ground. AGND 26 - Analog Ground. Connect to ground DGND 27 - Digital Ground. Connect to ground VREF 28 Input Internal Reference Voltage. Normally connects to a 0.1pF cap to ground. To use an external Vref, connect a 1.235V reference to this pin. DVDD 29 - Digital power supply. PO-P7 30 - 37 Input Pixel Address Lines. This byte-wide information is latched by the rising edge of PCLK when using the Color Palette, and is masked by the Pixel Mask register. These values are used to specify the RAM word address in the default mode (accessing RAM). In the Hi-Color XGA, and True Color modes, they represent color data for the DACs. These inputs should be grounded if they are not used. PCLK 38 Input Pixel Clock. The rising edge of PCLK controls the latching of the Pixel Address Anding inputs. This clock also controls the progress of these values through the three-stage pipeline of the Color Palette RAM, DAC, and outputs. BLANK* 39 Input Composite BLANK* Signal, active low. When BLANK is asserted, the outputs of the DACs are zero and the screen becomes black. The DACs are automatically powered down to save current during blanking. The color palette may still be updated through D0-D7 during blanking. XIN 40 Input Crystal input. A 14.318 MHz crystal should be connected to this pin. XOUT 41 Output Crystal output. A 14.318 MHz crystal should be connected to this pin. CLKO 42 Output Video clock output. Provides a CMOS level pixel or dot clock frequency to the graphics controller. The output frequency is determined by the values of the PLL registers. CLK1 43 Output Memory clock output. Used to time the video memory. cso 44. Input Clock select 0. The status of CS0-2 determine which frequency is selected on the CLKO (video) output. 11493 3ICS5300 GENDAC Preliminary internal Registers RS2]| RS1 | RSO Register Name Description (all registers can be written to and read from) 0 0 0 Pixel Address WRITE 0 1 1 Pixel Address READ There is a single Pixel Address register within the GENDAC. This register can be accessed through either register address 0,0,0 or register address 0,1,1. A read from address 0,0,0 is identical to a read from address 0,1,1. Writing a value to address 0,0,0 performs the following operations: a) Specifies an address within the color palette RAM. b) Initializes the Color Value register. Writing a value to address 0,1,1 performs the following operations: a) Specifies an address within the color palette RAM. b) Loads the Color Value register with the contents of the location in the addressed RAM palette and then increments the Pixel Address register. Writing to this 8-bit register is performed prior to writing one or more color values to the color palette RAM. Writing to this 8-bit register is performed prior to reading one or more color values from the color palette RAM. 0 0 1 Color Value The 18-bit Color Value register acts as a buffer between the microprocessor interface and the color palette. Using a three bytes transfer sequence allows a value to be read from or written to this register. When a byte is read, the color value is contained in the least significant 6 bits , DO-D5 (the most significant 2 bits are set to zero). When writing a byte, the same 6 bits are used. When reading or writing, data is transferred in the same order - the red byte first, then green, then blue. Each transfer between the Color Value register and the color palette replaces the normal pixel mapping operations of the GENDAC for a single pixel. After writing three definitions to this register, its contents are written to the location in the color palette RAM specified by the Pixel Address register, and the Pixel Address register increments. After reading three definitions from this register, the contents of the location in the color palette RAM specified by the Pixel Address registers are copied into the Color Value register, and the Pixel Address register increments. 0 1 0 Pixel Mask The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel Address value applied to the Pixel Address inputs (P0-P7). A one ina position in the mask register leaves the corresponding bit in the Pixel Address unaltered, while a zero sets that bit to zero. The Pixel Mask register does not affect the Pixel Address generated by the microprocessor interface when the palette RAM is being accessed. 11/493leer Ty BREREEEErF aed ICS5300 GENDAC Preliminary Internal Registers (continued) RS2 | RS1 | RSO Register Description Name (all registers can be written to and read from) 1 0 QO | PLL Address | Writing to this 8-bit register is performed prior to writing one or more WRITE PLL programming values to the PLL Parameter register. 1 1 1 PLL Address | Writing to this 8-bit register is performed prior to reading one or more READ PLL programming values from the PLL Parameter register. 1 1 0 Command This8-bit register selects the color mode, for instance 8-bit Pseudo Color, Hi- Color , True Color, or XGA, and DAC power down. The registers a are reset to pseudo color mode on power up. 1 0 1 PLL There are sixteen parameter registers as indexed by PLL Address Write/ Parameter Readregisters. Parameter registers 00-0D and OF are two bytes long and 0E is one byte long. This register set contains one control register. The bits of this register include clock select and enable functions, the rest contain PLL frequency parameters. After writing the start index address in the PLL address register, these registers can be accessed in successive two (or one) bytes. The address register auto increments after one or two bytes to access the entire register set. 11483ICS5300 GENDAC Preliminary Absolute Maximum Ratings Power Supply Voltage .......--.-sssseesssessssesseeesncenesenens 7V DC Digital Output Current ........cesesesseneeeseeseeseees 25 mA Voltage on any other pin ......GND0.5V to Vpp + 0.5V Analog Output Current .....ssssecccsescesseccsssesenereccneees 45 mA Temperature UNder DIAS 00... eeneceeeeseeeeeee -40 C to 85C _- Reference Current ........ccccsssceseseresscecsssenstsncceesenees -15mA Storage Temperatule .........c.cececsecsseeeees 65 Cto 150C - Power Dissipation ...........ssscssssessessssesserecssasenseeesenens 10W Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics Symbol Parameter Conditions Min Max Units DC Characteristics (note: J) Vpp Positive supply voltage 4.75 5.25 V Vu Input logic 1 voltage 2.0 Vpp + 0.5 Vv Vi Input logic 0 voltage ~0.5 0.8 Vv leer Reference current -7.0 -10 mA V eer Reference voltage 1.10 1.35 V ly Digital input current Vpp = max, +10 pA GND Vin S$ Vpp lag Off-state digital output current Vpp = max, +50 pA GND Vi S$ Vop Ipp Average power supply current I, = max, 250 mA Digital outputs unloaded Lyacorr DACs in power down mode No palette access 50 mA Vou Output logic 1 I, =-3.2mA, note K 2.4 V Vor Output logic 0 I, =-3.2mA, note K 0.4 V ICLK, Input Clock Rise Time TTL levels 15 ns ICLK; Input Clock Fall Time TIL levels 15 ns Fy Frequency Change of CLKO and With respect to CLK1 over supply and temperature | _ typical frequency 0.05 % 8 oICS5300 Preliminary Electrical Characteristics (continued) Symbol Parameter Conditions Min Max Units DAC Characteristics (note: J) Vo (max) | Maximum output voltage I, $10mA 1.5 Vv I, (max) | Maximum output current Vo S1V 21 mA Full scale error note A, B +5 % DAC to DAC correlation note B #2 %o Integral Linearity, 6-bit note B +0.5 LSB Integral Linearity, 8-bit note B +1 LSB Full scale settling time*, 6-bit note C 28 ns Full scale settling time, 8-bit note C 20 ns Rise time (10% to 90%)* note C 6 ns Glitch energy* note C 200 pVsec * Characterized values only Symbol Parameter Conditions Min Max Units PLL AC Characteristics fy Clock 0 operating range 29 135 MHz fy Clock 1 operating range 25 135 MHz t, Output clocks rise time 25 pf load, TTL levels 1.5 ns tr Output clocks fall time 25 pf load, TTL levels 1.5 ns dt Duty Cycle, 40/60 60/40 % jis Jitter, one sigma 130 ps ps jabs Jitter, absolute -300 ps 300 ps ps fref Input reference frequency Typically 14.318 MHz 5 25 MHz 11/93ICS5300 GENDAC Preliminary AC Electrical Characteristics (note: J) 80 MHz 110 MHz 135 MHz Symbol} Parameter Condition | Min | Max | Min | Max| Min | Max | Units toHcH PCLK period 12.5 9.09 74 ns Atcycy PCLK jitter note D 42.5 42.5 % tercH PCLK width low 5 3.6 3 ns toyc. PCLK width high 5 3.6 3 ns tpvcH Pixel word setup time note E 3 3 2 ns toupx Pixel word hold time note E 3 2 1 ns tevcu BLANK* setup time note E 3 3 2 ns toupx BLANK* hold time note E 3 2 1 ns toHay PCLK to valid DAC output note F 20 20 20 ns Atcuay Differential output delay note G 2 2 2 ns twowH WR pulse width low 50 50 50 ns tetRH RD* pulse width low 50 50 50 ns teywi Register select setup time Write cycle 10 10 10 ns toveL Register select setup time Read cycle 10 10 10 ns twisx Register select hold time Write cycle] 10 10 10 ns tersx Register select hold time Read cycle 10 10 10 ns tovwu WRy* data setup time 10 10 10 ns twrpx WR* data hold time 10 10 10 ns trtox Output turn-on delay 5 5 5 ns trLov RD* enable access time 40 40 40 ns trHox Output hold time 5 5 5 ns trHoz Output turn-off delay note H 20 20 20 ns twHw1i Successive write interval notel A (topicay) 4 (toricay) 4 (toc cycle twueii WR* followed by read interval] noteI 4 (tec) 4 (torcH) 4 (tocH cycle teyRti Successive read interval notel # (taycy baferttert) 4 (tonicay cycle teywii RD* followed by write interval} noteI f (tayqy) 4 (torscay) 4 (toceH cycle twHw12 WE after color write notel fA (taycy 4 (toricay) 4 (tocH cycle twuer2 RD* after color write notel 4 (teycy 4 (topicea) 4 (toycH cycle teuRi? RD* after color read noteIl BB (toc 8 (topicey) 8 (topic cycle teHwi2 WR after color read notel 8 (toycH 8 (toca) 8 (torce cycle twuris RD* after read address write notel 8 (taycH 8 (topce) 8 (topce) cycle tsop SENSE* output delay 1 1 1 ps 11493ICS5300 GENDAC Preliminary NOTES: A. Full scale error is derived from design equation {{(FSJguz) R, ~ 2.7 Oger) R,J/12-1gep)R, |} 100% Vetack tever=0V F.S.Igy7 = Actual full scale measured output B. R=37.5Q, Ipge = 8.88mMA Z,= 37.5Q + 30 pF, Inge = 8.88MA D. This parameter is the allowed Pixel Clock frequency variation. It does not permit the Pixel Clock period to vary outside the minimum values for Pixel Clock (te3}3) period. n E. It is required that the color palettes pixel address be a valid logic level with the appropriate setup and hold times at each rising edge of Pay (this requirement includes the blanking period). F. Theoutput delay is measured from the 50% point of the rising edge of CLOCK to the valid analog output. A valid analog output is defined when the analog signal is halfway between its successive values. G. This applies to different analog outputs on the same device. H. Measured at+ 200 mV from steady state output voltage. J. This parameter allows synchronization between operations on the microprocessor interface and the pixel stream being processed by the color palette. J. The following specifications apply for Vpp= +5V40.5V, GND=0. Operating Temperature = 0C to 70C. K. Except for SENSE pin. AC Test Conditions Input pulse levels........ssscsssscsesssseesseessesseeneeneess Vppto 3V Input rise and fall times (10% to 90%).......ssesssesseeseee ONS Digital input timing reference level... 1.5V Digital output timing reference level........0.8V and 2.4V Capacitance C, Digital input... esecesecsesscseneeeeseeseenenssesssseensseses 7pF Cy Digital Outpul.......cscscesesserecreseeececeessseserensenssceseneeeees 7pF Coa Analog Output... ceceecssssseesseceens seecseeseesneceseeseesees 10pF 2002 1.4V se) 50 pF (including scope and jig) tt DIGITAL OUTPUT LOAD General Operation The ICS5300 GENDAC is intended for use as the analog output stage of raster scan video systems. It contains a high-speed Random Access Memory of 256 x 18-bit words, three 6/8-bithigh-speed DACs, a microprocessor / graphic controller interface, a pixel word mask, on-chip compara- tors, and two user programmable frequency generators. Anexternally generated BLANK* signal can be applied to pin 39 of the ICS5300. This signal acts on all three of the analog outputs. The BLANK* signal is delayed internally so that it appears with the correct relationship to the pixel bit stream at the analog outputs. A pixel word mask is included to allow the incoming pixel address to be masked. This permits rapid changes to the effective contents of the color palette RAM to facilitate such operations as animation and flashing objects. Operations on the contents of the mask register can also be totally asynchronous to the pixel stream. The ICS5300 also includes dual PLL frequency generators providing a video clock (CLKO) and a memory clock (CLK1), both generated froma single 14.318 MHz crystal. There are eight selectable CLKO frequencies of which six are programmable, and a single programmable CLK1 frequency. Default values (Table 1 and Table 2) are loaded into the appropriate registers on power up. Video Path The GENDAC supports four different video modes and is determined by bits 5-7 of the command register. The default mode is the 6-bit Pseudo Color mode. The other modes are the bypass 15-bit, 16-bit and 24 bit True Color. Pseudo color In this mode, Pixel Address and BLANK* inputs are sampled on the rising edge of the clock (PCLK) and any change appears at the analog outputs after three succeed- ing rising edges of the clock. The DAC outputs depends on the data in the color palette RAM. 11493ICS5300 GENDAC Preliminary Bypass Modes The GENDAC supports three different bypass modes; 15- bit (5,5,5) mode, 16-bit (5,6,5) mode and the 24-bit True Color 8-bit DAC mode. In these modes, the pixel address pins PO-P7 represent the Color Data that is applied di- rectly to the DAC. The internal RAM is bypassed. In the 15/16-bit mode two consecutive bytes contain the 15/16 bits of color data. Two consecutive rising edges of the PCLK latch the data on the PO-P7 pins into registers and the byte framing is internally synchronized with the rising edge of BLANK*. The internal pipe line delay from the "first byte" to the DAC is four PCLK rising edges. In the 24-bit True Color mode, three bytes contains the 24-bit color data. Three consecutive rising edges of the PCLK latch the data. The framing is the same as the 15/16-bit mode. The internal pipe line delay from the "first byte" to the DAC is five PCLK rising edges. DAC Outputs The outputs of the DACs are designed to be capable of producing 0.7 volt peak white amplitude with an Ippy of 8.88 mA when driving a doubly terminated 75Q load. This corresponds to an effective DAC output load (Regrectrve) Of 37.52. The formula for calculating I, with various peak white voltage / output loading combinations is given below: VeEAK WHITE Iper = 2.1 x Reprecrive Note that for all values of Ipp, and output loading: Veack Lever = 9 The reference current Ippp is determined by the reference voltage Vpp, and the value of the resistor connected to Regy pin. Vege can be the internal band gap reference voltage or can be overridden by an external voltage. In both cases Inne =Vepe/ Reg - Figure 4- DAC Set up The BLANK* input to the GENDAC acts on all three of the DAC outputs. When the BLANK* input is low, the DACs are powered down. The connection between the DAC outputs of the ICS5300 and the RGB inputs of the monitor should be regarded as a transmission line. Impedance changes along the trans- mission line will result in the reflection of part of the video signal back along the transmission line. These reflections may result in a degradation of the picture displayed by the monitor. RF techniques should be observed to ensure good fidel- ity. The PCB trace connecting the GENDAC to the off- board connector should be sized to form a transmission line of the correct impedance. Correctly matched RF connectors should be used forconnection from the PCB to the coaxial cable leading to the monitor and from the cable to the monitor. There are two recommended methods of DAC termina- tion: double termination and buffered signal. Each is described below with its relative merits: Double Termination (Figure 1) For this termination scheme, a load resistor is placed at both the DAC output and the monitor input. The resistor values should be equal to the characteristic impedance of the line. Double termination of the DAC output allows both ends of the transmission line between the DAC outputs and the monitor inputs to be correctly matched. The result should be an ideal reflection free system. This arrangement is relatively tolerant to variations in transmission line impedance (e.g. a mismatched connector) since no reflections occur from either end of the line. 11493 10ICS5300 GENDAC Preliminary A doubly terminated DAC output will rise faster than any singly terminated output because the rise time of the DAC outputs is dependent on the RC time constant of the load. MONITOR 1CS5300 R LOAD Rroap GND + GND Figure 1 - Double Termination Buffered Signal (Figure 2) If the GENDAC drives large capacitive loads (for instance long cable runs), it may be necessary to buffer the DAC outputs. The buffer will have a relatively high input impedance. The connection between the DAC outputs and the buffer inputs should also be considered as a transmission line. The buffer output will have a relatively low impedance. It should be matched to the transmission line between it and the monitor with a series terminating resistor. The transmission line should be terminated at the monitor. Rg MONITOR . 1CS5300 R Loap Rr GND GND Figure 2 - Buffered Signal SENSE Output The GENDAC contains three comparators, one each for the DAC output (R, G and B) lines. The reference voltage to the comparators is proportional to the Vz, (internal or external) and is typically 0.33 for Ver: =1.23 Volts. When the voltage on any of these pins go higher than the reference voltage to the comparators, the SENSE pin is driven low. This signal is used to detect the type of (or lack of) monitor connected to the system. PLL Clock The ICS5300 has dual PLL frequency generators for gen- erating the video clock (CLKO) and memory clock (CLK1) needed for graphics subsystems. Both these clocks are generated from a single 14.318 MHz crystal or can be driven by an external clock source. The chip includes the capacitors for the crystal and all the components needed for the PLL loop filters, minimizing board component count. There are eight possible video clock, CLKO, frequencies (f0-f7) which can be selected by the external pins CS0- CS2. Pins are software selectable by setting a bitin the PLL control register. Two of these frequencies (f0-f1) are fixed and the other six (f2-f7) can be programmed for any frequency by writing appropriate parameter values to the PLL parameter registers. The default frequencies on power up are commonly used video frequencies (table 1). At power up, the frequencies can be selected by pins CSO0- CS2. There is only a single programmable memory clock frequency (CLK1 ). On power up this frequency defaults to the frequency given in table 2. The memory clock transition between frequencies is smooth and glitch free if the transition is kept between the limits 45-65 MHz. VLCK fn} (MHz) | Comments f0| 25.175 | VGAO (VGA Color monitor) (fixed) f1] 28.322 | VGA1 (VGA Monochrome monitor) (fixed) f2} 31.500] VESA 640 x 480 @72 Hz (programmable) 3| 36.00 | VESA 800 x 600 @56 Hz (programmable) f4| 40.00 | VESA 800 x 600 @60 Hz (programmable) 5] 44.889 | 1024 x 768 @43 Hz Interlaced (programmable) f6] 65.00 | 1024x 768 @ 60 Hz, 640 x 480 Hi-Color @ 72 Hz (programmable) 7} 75.00 | VESA 1024 x 768 @ 70 Hz, True Color 640 x 480 (programmable) Table 1 - Video clock (CLK0) default frequency register (with a 14.318 MHz input) 11493 11ICS5300 GENDAC Preliminary fn | MHz Comments fA | 45.00 MHz | Memory and GUI subsystem clock Table 2 - Memory Clock (CLK1) default frequency register Microprocessor Interface Below are listed the six microprocessor interface registers within the ICS5300, and the register addresses through which they can be accessed. RS2 | RS1 | RSO | Register Name Pixel Address (write mode) Pixel Address (read mode) Color Value Pixel Mask PLL Address (write mode) PLL Parameter Command PLL Address (read mode) Command Register accessed by (hidden) flag after special sequence of events i) PREP OOrOrFO DY OR DOR HO oO ~ Table 3 - Microprocessor Interface Registers Asynchronous Access to Microprocessor Interface Accesses to all registers may occur without reference to the high speed timing of the pixel bit stream being processed by the GENDAC. Data transfers between the color palette RAM and the Color Value register, as wellas modifications to the Pixel Mask register,are synchronized to the Pixel Clock by internal logic. This is done in the period between microprocessor interface accesses. Thus, various minimum periods are specified between microprocessor interface accesses toallow the appropriate transfers or modifications to take place. Access to PLL address, PLL parameter and to the command register are asynchronous to the pixel clock. The contents of the palette RAM can be accessed via the Color Value register and the Pixel Address registers. Writing to the color palette RAM Toset anew color definition, a value specifying a location in the color palette RAM is first written to the Write mode Pixel Address register. The values for the red, green and blue intensities are then written in succession to the Color Value register. After the blue data is written to the Color Value register, the new color definition is transferred to the RAM, and the Pixel Address register is automatically incremented. Writing new color definitions to a set of consecutive locations in the RAM is made easy by this auto- incrementing feature. First, the start address of the set of locations is written to the write mode Pixel Address register, followed by the color definition of that location. Since the address is incremented after each color definition is written, the color definition for the next location can be written immediately. Thus, the color definitions for consecutive locations can be written sequentially to the Color Value register without re-writing to the Pixel Address register each time. Reading from the RAM To read a color definition, a value specifying the location in the palette RAM to be read is written to the read mode Pixel Address register. After this value has been written, the contents of the location specified are copied to the Color Value register, and the Pixel Address register automatically increments. The red, green and blue intensity values can be read by a sequence of three reads from the Color Value register. After the blue value has been read, the location in the RAM currently specified by the Pixel Address register is copied to the Color Value register and the Pixel Address again automatically increments. A set of color values in consecutive locations can be read simply by writing the start address of the set to the read mode Pixel Address register and then sequentially reading the color values for each location in the set. Whenever the Pixel Address register is updated, any unfinished color definition read or write is aborted and a new one may begin. The Pixel Mask Register The pixel address used to access the RAM through the pixel interface is the result of the bitwise ANDing of the 11493 12ICS5300 GENDAC Preliminary incoming pixel address and of the contents of the Pixel Mask register. This pixel masking process can be used to alter the displayed colors without altering the video memory or the RAM contents. By partitioning the color definitions by one or more bits in the pixel address, such effects as rapid animation, overlays, and flashing objects can be produced. The Pixel Mask register isindependent of the Pixel Address and Color Value registers. The Command Register The Command register is used to select the various GEN- DAC color modes and to set the power down mode. On power up this register defaults to an 6-bit Pseudo Color mode. This register can be accessed by control pins RS2- RSO, or by a special sequence of events for graphics subsystems that do not have the control signal RS2. For graphic systems that do not have RS2, this pin is tied low and an internal flag (HF; Hidden Flag) is set when the pixel mask register is read four times consecutively. Once the flag is set, the following Read or Write to the pixel mask register is directed to the command register. The flag is reset for Read or Write to any register other than the pixel mask register. The sequence has to be repeated for any subsequent access to the command register. The PLL Parameter Register The CLKO and CLK1 of the ICS5300 can be programmed for different frequencies by writing different values to the PLL parameter register bank. There are eight registers in the parameter register; seven are two bytes long and one (0E) is one byte long. Writing to the PLL parameter register To write the PLL parameter data, the corresponding address location is first written to the PLL address regis- ter. For software compatibility with other chips, two address registers are defined; the Write mode PLL ad- dress register and the Read mode PLL address register. They are actually a single Read/Write register in the ICS5300. The next PLL parameter write will be directed to the first byte of the address location specified by the PLL address register. The next Write to the parameter register will automatically be to the second byte of this register. At the end of the second Write the address is automatically incremented. For the one byte "OE" register the address location is incremented after the first byte Write. If this frequency is selected while programming, the output frequency will change at the end of the second Write. Reading the PLL parameter register To read one of the registers of the PLL parameter register the address value corresponding to the location is first written to the PLL address register. The next PLL param- eter read will be directed to the first byte of the address location pointed by this index register. A next Read of the parameter register will automatically be the second byte of this register. At the end of the second Read, the address location is automatically incremented. The address regis- ter (OE) is incremented after the first byte Read. Power Down Mode When bit 0 in the Command register is high (set to 1) , the GENDAC enters the DAC power down mode. The DACs are turned off, and the data is retained in the RAM. It is possible to access the RAM, in which case the current will temporarily increase. While the RAM is being accessed, the currentconsumption will be proportional to thespeed of the clock. There is no effect on either clock generator while in this mode. Power Supply As a high speed CMOS device, the ICS5300 may draw large transient currents from the power supply, it is necessary to adopt high frequency board layout and power distribution techniques to ensure proper opera- tion of the GENDAC. Please refer to the suggested layout on page 29. To supply the transient currents required by the ICS5300, the impedance in the decoupling path should be kept to a minimum between the power supply pins Vpp and GND. Itis recommended that the decoupling capacitance between Vp, and GND should be a 0.1 F high frequency capacitor, in parallel with a large tantalum capacitor with 11493 13ICS5300 GENDAC Preliminary a value between 22uF and 47uF. A ferrite bead may be added in series with the positive supply to form a low pass filter and further improve the power supply local to the GENDAC. It will also reduce EMI. Thecombination of series impedance in the ground supply to the GENDAC, and transients in the current drawn by the device will appear as differences in the GND voltages to the GENDAC and to the digital devices driving it. To minimize this differential ground noise, the impedance in the ground supply between the GENDAC and the digital devices driving it should be minimized. Digital Output Information The PCB trace lines between the outputs of the TIL devices driving the GENDAC and the input to the GENDAC behave like low impedance transmission lines driven from a low impedance transmission source and terminated with a high impedance. In accordance with transmission line principles, signal transitions will be reflected from the high impedance input to the device. Similarly, signal transitions will be inverted and reflected from the low impedance TTL output. Line termination is recommended to reduce or eliminate the ringing, particu- larly the undershoot caused by reflections. The termina- tion may either be series or parallel. Series termination is the recommended technique to use. It has the advantages of drawing no DC current and of using fewer components. Series termination is accom- plished by placing a resistor in series with the signal at the output of the TTL driver. This matches the TTL output impedance to that of the transmission line and ensures that any signal incident on the TTL outputisnot reflected. To minimize reflections, some experimentation will have to be done to find the proper value to use for the series termination. Generally, a value around 100Q will be required. Since each design will result ina differentsignal impedance, a resistor of a predetermined value may not properly match thesignal path impedance. Therefore, the proper value of resistance should be found empirically. 11/93 14ICS5300 GENDAC Preliminary Functional Descri ption Bit 0 Power Down Mode of RAMDAC When this bit is set to 0 (default is 0), the device operates normally. If this bit is set to 1, the power and clock to the Color Palette RAM and DACs are turned off. The data in the Color Palette RAM are still preserved. The CPU can access without loss of data by internal auto- matic clock start/stop control. The DAC out- puts become the same as BLANK* (sync) level This section describes the register address and bit defini- tion for RAMDAC and the Frequency Synthesizer sec- tions. Color Palette : output during power down mode. This bit omen pegister does not effect the PLL clock synthesizer func- ~ tion. (RSO-RS1 = 01 with hidden flag) By setting bits in the command register the ICS5300 can be Color Modes programmed for different color modes and can be pow- ered down for low power operation. The four selectable color modes are described here. 7 6 5 4 3 2 1 0 Mode 0: 8-bit Pseudo Color (one clock per pixel). This Color Mode Reserved Snooze mode is the 8-bit per pixel Pseudo Color mode. In this 2 1 #0 Should all =0 mode. inputs PO-P7 are the pixel address for the color palette RAM and are latched on the rising edge of every Table 3 - Command Registers PCLK. This is the default mode on power up and it is selected by setting bits CR7-CR5 to 000. There are three k cycles pipe line delays from input to DAC t. Bit7-5 Color Mode Select clock cycles pipe line delays from input to outpu These three bits select the Color Mode of RAMDAC operation as shown in the following table 4 (default is 0 at power up): 8-bit Pseudo Color mode DATA BYTE Bit4-1 (Reserved) 7 6 5 4 3 2 #1 = 90 PIXEL ACCESS 7 6 5S 4 3 2 1 0 CM2 CM1 CMO Clock Cycles/ (CR7) (CR6) (CRS) Color Mode Pixel Bits 0 0 0 6-Bit Pseudo Color with Palette (Default) 1 ) 0 ] 15-Bit Direct Color with Bypass (Hi-Color) 2 0 I 0 24-Bit True Color with Bypass (True Color) 3 0 1 1 16-Bit Direct Color with Bypass (XGA) 2 1 0 0 15-Bit Direct Color with Bypass (Hi-Color) 2 1 0 1 15-Bit Direct Color with Bypass (Hi-Color) 2 1 1 0 16-Bit Direct Color with Bypass (XGA) 2 1 1 1 24-Bit True Color with Bypass (True Color) 3 Table 4 - Color Mode Select 11/493 15ICS5300 GENDAC Preliminary rr Mode 1: (15-bit per color bypassHi-Color mode). This mode is the 15-bit per pixel bypass mode. In this mode, inputs P0O-P7 are the color DATA and are input directly to the DAC, bypassing the color palette. The two bytes of data is latched in two successive PCLK rising edges. ICS5300 supports only the two clock mode and does not support the mode where the data are latched on the rising and the falling edges. For compatibility, the 15/ 16 oneclock modes are selected as two clock modes in this chip. The low-byte, high byte synchronization is internally done by the rising edge of BLANK. Each color is 5-bit wide and is packed into two bytes as shown below. The mode is selected by setting bits CR7-CR5 to 001, 100 or 101. 15-Bit Color Mode 3LSB = set to zero SECOND BYTE FIRST BYTE PPPPPPPPIPPPPPPPP 76543210/76543210 X}7 65 413765 43/7654 3 RED GREEN BLUE Mode 2: (16-bit per pixel bypass XGA mode). This mode is the 16-bit per pixel bypass mode and the PO- P7 inputs to go to the DAC directly, bypassing the color palette. The 2 bytes data is latched on two successive rising edges and the low-byte, high-byte synchronization is internally done by the rising edge of BLANK". In this mode, blue and red colors are 6 bits wide and green is 5 bits wide. The 2 bytes of data is packed as shown below. The mode is selected by setting bits CR7-CR5 to 011 or 110. 16-Bit color mode 2LSB = set to zero (green) 3LSB = set to zero (blue, red) CO. Zz an loaolB D P 3 3 NSDPN OD P 5 5 Op law RE Mode 3: (24-bit per pixel True Color Mode). This mode is the 24-bit per pixel bypass mode. The three bytes of data are latched on three successive PCLK edges and the first byte is synchronized by the rising edge of BLANK. In this mode, each of the colors are 8-bit wide and the DAC is an 8-bit wide DAC. The first byte is blue followed by green and red. This mode can be selected by setting bits CR7-CR5 to 010 or 111. The DAC outputs changes every three cycles and the pipeline delay from the first byte to output is five cycles. 24-bit color mode THIRD BYTE SECOND BYTE FIRST BYTE PPPPPPPPIPPPPPPPPIPPPPPPPP 76543210176543210/76543210 76543210176543210176543210 RED GREEN _ BLUE Frequency Generators The ICS5300 clock synthesizer can be reprogrammed through the microprocessor interface for any set of frequencies. This is done by writing appropriate values to the PLL Parameter Register Bank (table 5). PLL Address Registers The address of the parameter register is written to the PLL address registers before accessing the parameter register. This register is accessed by register select pins RS2-RSO = 100 or 111. 7 6 5 4 3 2 1 0 PLL REGISTER ADDRESS 7 6 5 4 3 2 1 ~0 PLL Parameter Register There are sixteen registers in the PLL parameter register (table 5). Registers 00 to 07 are for the CLKO selectable frequency list, Register OA for CLK1 programmable fre- quency and register OE is the PLL CLKO control register. 11493 16ICS5300 GENDAC Preliminary Index | R/W | Register 00 R/- CLKO f0 PLL Parameters (2 bytes) 01 R/- CLKO fl PLL Parameters (2 bytes) 02 | R/W | CLKOf2 PLL Parameters (2 bytes) 03 R/W | CLKO3 PLL Parameters (2 bytes) 04 | R/W | CLKOf4PLL Parameters (2 bytes) 05 | R/W | CLKOf5 PLL Parameters (2 bytes) 06 R/W | CLKO f6 PLL Parameters (2 bytes) 07 R/W | CLKOf7PLL Parameters (2 bytes) 08 R/- (Reserved) = 0 (2 bytes) 09 R/- (Reserved) = 0 (2 bytes) OA | R/W | CLK1fA PLL (2 bytes) 0B R/- (Reserved) = 0 (2 bytes) oc | R/- (Reserved) = 0 (2 bytes) OD | R/- (Reserved) = 0 (2 bytes) OE | R/W | PLL Control Register (1-byte) OF R/- (Reserved) =0 (2-byte) Table 5 - PLL Parameter Registers PLL Control Register Bits in this register determine internal or external CLKO select. 7 6 5 4 3 2 1 0 (RV) | (RV)] ENBL | (RV)| (RV) INTERNAL SELECT =0 =0 | INCS | =0 =0 x x xX Bit 7-6 Reserved. Bit 5 Enable Internal Clock Select (INCS) for CLKO. When this bit is set to 1, the CLKO output frequency is selected by bit 2 - 0 in this register. External pins CSO - CS2 are ignored. Bit4-3 (Reserved). Bit 2-0 Internal Clock Select for CLKO (INCS). These three bits selects the CLKO output fre- quency if bit 5 of this register is on. They are interpreted as an octal number, n, that selects fn. Default selects 0. PLL Data Registers The CLKO and CLK1 input frequency is deternimed by the parameter values in this register. These are two bytes registers; the first byte is the M-byte and the second is the N-byte. M-Byte PLL Parameter Input The M-byte has a 7-bit value (1-127) which is the feedback divider of the PLL. 7 6 5 4 3 2 1 O Reserved M-Divider Value =0 X X X XxX XK XK X N-Byte PLL Parameter Input The N-byte has two values. NI sets a 5-bit value (1-31) for the input pre scalar and N2 is a 2-bit code for selecting 1, 2, 4, or 8 post divide clock output. 7 6 5 4 3 2 1 #90 Reserved} N2-Code N1-Divider Value =0 X X |X xK XK XK X N2 Post Divide Code N2 code 00 01 10 11 Divider aorN Ht The block diagram of the PLL clock synthesizer is given in following figure 3. Based on the Mand N values, the output frequency of the clocks is given by the following equation: (M+2) x Frog (N1+2) x2N2 M and N values should be programmed such that the frequency of the VCO is within the optimum range for duty cycle, jitter and glitch free transition. Optimum duty cycle is achieved by programming N2 for values greater than one. See the following page for programming ex- ample. V1 17ICS5300 GENDAC Preliminary Programming Example Suppose an output frequency. of 25.175 MHz is desired. The reference crystal is 14.318 MHz. The VCO should be targeted to run in the 100 to 180 MHz range, so choosing a post divide of 4 gives a VCO frequency of : 4X 25.175=101.021 MHz From the table on page 17, we find N2 = 2 Substituting F = 14.318 and 2" = 4 into the equation on page 17: 25.175 \. 4 (M+2) 14.318 (NI + 2) by trial and error: 25.175). 4 327 14.318 so M+2=127 N1+2=18 so the registers are: M=125d=1111 N=0&N2code&N Additional Information on Programming the Fre- quency Generator section of the GENDAC When programming the GENDAC PLL parameter regis- ters, there are many possible combinations of parameters which will give the correct output frequency. Some combinations are better than others, however. Here is a method to determine how the registers need to be set: The key guidelines come from the operation of the phase locked loop, which has the following restrictions: 1. 2 MHz < freee < 32 MHz This refers to the input reference frequency. Most users simply connect a 14.318 MHz crystal to the crystal inputs, so this is not a problem. 2. 600 kHz < fpr (N142) This is the frequency input to the phase detector. <8 MHz 3. 60 MHz < (M+2) fpre < 270 MHz (N1+2) This is the VCO frequency. In general, the VCO should run as fast as possible, because it has lower jitter at higher frequencies. Also, running the VCO at mul- tiples of the desired frequency allows the use of output divides, which tends to improve the duty cycle. 4. forxoand fax, < 135 MHz This is the output frequency. These rules lead to the following procedure for determin- ing the PLL parameters, assuming rules 1 and 4 are satisfied. A. Determine the value of N2 (either 1, 2, 4 or 8) by selecting the highest value of N2, which satisfies the condition N2* for < 270 MHz B. Calculate (M2+) _ 2N?fout (N1+2)~ _ fref C. Now (M+2) and (N1+2) must be found by trial and error. Witha 14.318 MHz reference frequency, there will generally be a small output frequency error due to the resolution limit of (M+2) and (N1+2). For a given fre- quency tolerance, several different (M+2) and (N1+2) combinations can usually be found. Usually, a few minutes trying out numbers with a calculator will pro- duce a workable combination. Multiplying possible values of (N1+2) by the desiredratio will indicate ap- proximately the value of M. This method is shown in the example below. A program could be written to try all possible combinations of (M+2) and (N1+2) (3937 pos- sible combinations), discard those outside error band, and select from those remaining by giving preference to ratios which use lower values of (M+2). Lower values of (M+2) and (N1+2) provide better noise rejection in the phase locked loop. Example: Suppose we are using a 14.318 MHz reference crystal and wish to output a frequency of 66 MHz with an error of no greater than 0.5%. What are the values of the PLL data registers? 11493 18eer Stig td ICS5300 GENDAC Preliminary A. 66*8 = 528 > 250 VCO speed too high 66*4 = 264 > 250 VCO speed too high 66*2 = 132 < 250 VCO speed OK, N2 = 2, N2 code = 01 from table on page 17 of the data sheet. B. 132/14.31818 = 9.219 This is the desired frequency multiplication ratio. C. Setting (N1+2) = 3, 4,...12, 13 and performing some simple calculations yields the following table: (Note that N1 cannot be 0) (N1+2) (N1+2)*9.219 rounded (=M+2) Actual Ratio Percent Error 3 27.657 28 9.33 -1.23 4 36.876 37 9,25 -0.34 5 46.095 46 9.20 0.21 6 55.314 55 9.17 0.57 7 64.533 65 9.29 -0.72 8 73.752 74 9.25 -0.34 9 82.971 83 9.22 -0.03 10 92.19 92 9.20 0.21 11 101.409 101 9.18 0.40 12 110.628 111 9.25 -0.34 13 119.847 120 9.23 -0.13 The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2) =83;M =81. The M-byte PLL parameter word is simply 81 in binary, plus bit 7 (which must be set to 0), or 01010001. The N-byte PLL parameter word is N2 code (01) concatenated with 5 bits of N2 in binary (00111), or 00100111. Once again, bit 7 must be zero. Wehavechosen the combination with the least frequency error, but several other combinations are within the 0.5% tolerance. Because the lowest value of (M+2) offers the best damping, the 37/4 combination will have the best power supply rejection. This results in lower jitter due to external noise. Fref 1 |__| Fout r} _> PHASE CHG LOOP N2 ou (N1+2) DETECT |] PUMP [| FILTER[ | YOO CNTR CT 1 (M1+2) [ Figure 3 - PLL Clock Synthesizer Block Diagram External Select (Internal Select PLL Control Register) CS2 CSI cso BIT 2 BIT 1 BIT 0 CLK 0 Frequency 0 0 0 0 0 0 f0 0 0 1 0 0 1 fl 0 1 0 0 1 0 2 0 1 1 0 1 1 3 1 0 0 1 0 0 f4 1 0 1 1 0 1 5 1 1 0 1 1 0 6 1 1 1 1 1 1 7 Video Clock Selection Table 11493 19ICS5300 GENDAC Preliminary PLCK PO-P7 BLANK* Cc B G A__ fF \ RED pune pean B _/ a a GREEN eA eae ata S ON OTF BLUE BLANK BLANK77 F System Timing - Pseudo Color, Mode 0 PLCK PO-P7 BLANK* tcHav RED B | \ A_ toway BLANK BLANK _/ B_ GREEN __a__/ Lo Sf BLANK BLANK A tcnav BLUE \_s_ oT BLANK BLANK ~_ Detailed Timing Specifications - Pseudo Color, Mode 0 1193 20ICS5300 GENDAC Preliminary BLANK / PO-P7 / LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE \ A A B B a__ 7 DAC-RD , / A-_, DAC-GR | / B | _ 7B DAC-BL | / A System Timing Bypass - 15 (5/5/5) and 16 (5/6/5) Modes 1, 2 Ons 25ns 50ns 75ns 100ns 125ns 150ns pice SVS VS \VYCANABYNS VAS SNS | BLANK* f X <a_ >< B porr [_______ X|@tXGR XRD X|BLXGR XRD X_X_) DAC-BL So NY DAC-GR La DAC-RD a a on System Timing Bypass True Color 24 (8,8,8) Mode 3 11493 21ICS5300 GENDAC Preliminary t wow WR* RSO-RS1 DO0-D7 Basic Write Cycle Timing taLeH RD* RSO-RSt t pov DO-D7 trax Basic Read Cycle Timing twew1t t wHRLt WR* RD* RSO RS1 Write to Pixel Mask Register Followed by Write Write to Pixel Mask Register Followed by Read WwR* UAL t pew RD* Read from Pixel or Pixel Address Register Read from Pixel or Pixe! Address Register (Read or Write) followed by Read (Read or Write) followed by Write 11493 22ICS5300 GENDAC Preliminary WR* t wHALa RD* RSO RS1 RS2 ADDRESS ADDRESS +1} DO-D7 Write and Read Back Pixel Address Register (Read Mode) t wHALs WR* RD* RSO RS1 RS2 pen ADDRESS Write and Read Back Pixel Address Register (Write Mode) twrris WR* t RHRLI __tRHRL ture RD* _ - RSO RS1 RS2 DO-D7 0-D ADDRESS ( RED } GREEN BLUE ADDRESS +2 Read Color Value then Pixel Address Register (Read Mode) 11/93 23ICS5300 GENDAC Preliminary rv 4 Tt ing nt Ty Lt Ty WR* RD* RSO RS1 RS2 DO-D7 Color Value Write followed by any Read WR* RD* RSO RS1 RS2 Color Value Write followed by any Write 11493 24ICS5300 GENDAC Preliminary WR* RD* Color Value Read followed by any Read WR* t RHALI trHAL RD* RSO RS1 RS2 Color Value Read followed by any Write 11/93 25ICS5300 GENDAC Preliminary t wuats WR* RD* RSO RS1 RS2 V DO-D7 ADDRESS Write and Read back PLL Address Register (Write Mode) t wHALs WR* RD* RSo RS1 RS2 Write and Read back PLL Address Register (Read Mode) 11493 26ICS5300 GENDAC Preliminary t wHALs WR* tari t RHALZ taAHAL OTT aT LT Ss CT VA fA LJ \ Sf VS VS DO0-D7 / \ / \ mucow) {hus nor) {noon =) Read Two bytes PLL Register then PLL Address Register twas WR* tanAt | tRHRL2 t RHAL | RD* me Ee VS VS VS rst [7 \ \ f \ of \ RS2 | / \ / \ / DO-D7 PLL ADD +1 Read One Byte PLL Register then PLL Address Register 11493 27ICS5300 GENDAC Preliminary Monitor SENSE Sig nal The ground plane is continuous, but the power plane is sepa- rated into analog and digital sections as shown. Power is supplied to the analog power plane through the ferrite bead, RED, and bypassed at the power entry point by C3, a 10 LF tantalum GREEN. aa5v capacitor. These high current connections should have mul- tiple vias to the ground and power planes, if possible. Power tsop connections should be connected to the analog or digital power SeNse__ plane, as shown in the diagram. Power pins 5 and 29 should be connected to digital power, power pins 20 and 24 to analog power. Decoupling capacitors (indicated by Cl) should be placed as close to the GENDAC as possible. The analog and digital I/O lines are notshown. Analog signals . ; . (DAC outputs, Vref, Rset) should only be routed above the The high performance of which the ICS5300 GENDAC is analog power plane. Digital signals should only be routed capable is dependent on careful PC board layout. The useof above the digital power plane. a four layer board (internal power and ground planes, signals on the two surface layers) is recommended. The layout below shows a suggested configuration. Recommended Layout CFOs] DIGITAL Power cl cl Plane + Y1 /, 100 mil Separation ze OO Prin} SBESRSIASRZ o Afr 41 7 Cy 42 CeO UC] 43 Sp OW 1s5300 pom CT eo] A Analog Power Cl ~ Cl O=ll 3 Plane Island GN 2 Ce 5 2+ O Oe CFO) + \ OL VIA to ground plane O4 VIA to power plane Cl Oluf chip capacitor C2 C3 FB1 c2 /luf chip capacitor + C3 10uf tantulum capacitor FBI Ferrite Bead Rl 140 ohm 1% resistor Yl - 14.318 Mhz parallel resonant crysal cut for C 1 =12 1193 28ICS5300 GENDAC Preliminary Notes: 11493 29ICS5300 GENDAC Preliminary Notes: 11493 30ICS5300 GENDAC Preliminary Notes: 1193 31ICS5300 GENDAC Preliminary a oi Tro an i an Lig BI ST] Package Outline 0.045 0.050 + 0.001 . 0.045 (1.143) LEAD #1 (1.270 + 0.025) > cc 0.354 + 0.005 (8.992 + 0.127) ULIWINWUULI ou a Fle als nina -+||.- 3 S ais 8 MOU WOOO | >| 0.021 0.390 + 0.005 (0.660) (9.906 + 0.127) 0.102 (0.553) 0.170 (4.318) Ordering Information ICS5300V Example: ICS XXXX M Package Type V=PLCC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device Integrated Circuit Systems reserves the right to make any changes in the circuitry or specifications at any time without notice and assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. Integrated Circuit Systems 1271 Parkmoor Avenue San Jose, CA 95126 (408) 297-1201 Fax (408) 925-9460 2435 Boulevard of the Generals P.O. Box 968 * Valley Forge, PA 19482-0968 (215) 630-5300 Fax (215) 630-5399 11193 32