Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 LMC7101, LMC7101Q-Q1 Tiny Low-Power Operational Amplifier With Rail-to-Rail Input and Output 1 Features 3 Description * The LMC7101 device is a high-performance CMOS operational amplifier available in the space-saving 5pin SOT-23 tiny package. This makes the LMC7101 ideal for space- and weight-critical designs. The performance is similar to a single amplifier of the LMC6482 and LMC6484 types, with rail-to-rail input and output, high open-loop gain, low distortion, and low-supply currents. 1 * * * * * * * Tiny 5-Pin SOT-23 Package Saves Space--Typical Circuit Layouts Take Half the Space of 8-Pin SOIC Designs Ensured Specifications at 2.7-V, 3-V, 5-V, 15-V Supplies Typical Supply Current 0.5 mA at 5 V Typical Total Harmonic Distortion of 0.01% at 5 V 1-MHz Gain Bandwidth Similar to Popular LMC6482 and LMC6484 Rail-to-Rail Input and Output Temperature Range -40C to 125C (LMC7101Q-Q1) The main benefits of the tiny package are most apparent in small portable electronic devices, such as mobile phones, pagers, notebook computers, personal digital assistants, and PCMCIA cards. The tiny amplifiers can be placed on a board where they are needed, thus simplifying board layout. Device Information(1) 2 Applications * * * * * PART NUMBER Mobile Communications Notebooks and PDAs Battery Powered Products Sensor Interface Automotive Applications (LMC7101Q-Q1) LMC7101, LMC7101Q-Q1 PACKAGE SOT-23 (5) BODY SIZE (NOM) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Example Application R2 V+ R1 - OUT IN + V- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings: LMC7101............................................ 4 ESD Ratings: LMC7101Q-Q1 ................................... 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Electrical Characteristics: 2.7 V ................................ 5 DC Electrical Characteristics: 3 V ............................ 6 DC Electrical Characteristics: 5 V ............................. 7 DC Electrical Characteristics: 15 V .......................... 8 AC Electrical Characteristics: 5 V ........................... 9 AC Electrical Characteristics: 15 V ......................... 9 Typical Characteristics .......................................... 10 Detailed Description ............................................ 20 7.1 7.2 7.3 7.4 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 20 20 20 21 Application and Implementation ........................ 22 8.1 Application Information............................................ 22 8.2 Typical Application ................................................. 23 9 Power Supply Recommendations...................... 25 10 Layout................................................................... 25 10.1 Layout Guidelines ................................................. 25 10.2 Layout Example .................................................... 25 11 Device and Documentation Support ................. 26 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Related Links ........................................................ Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 26 12 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2013) to Revision G * Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision E (March 2013) to Revision F * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 22 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 OUTPUT O Output 2 V+ P Positive Supply 3 INPUT+ I Noninverting Input 4 INPUT- I Inverting Input 5 V- P Negative Supply Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 3 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Difference input voltage UNIT (V+) + 0.3, (V-) - 0.3 Voltage at input and output pins + MAX Supply Voltage - Supply voltage (V - V ) V 16 V Current at input pin -5 5 mA Current at output pin (3) -35 35 mA Current at power supply pin 35 mA Lead temperature (soldering, 10 sec.) 260 C 150 C 150 C Junction temperature (4) Storage temperature (1) (2) (3) (4) -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the TI Sales Office or Distributors for availability and specifications. Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150C. The maximum power dissipation is a function of TJ(MAX), RJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly into a PC board. 6.2 ESD Ratings: LMC7101 VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 Machine model (MM) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings: LMC7101Q-Q1 VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 1000 Machine model (MM) 200 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted). (1) MIN MAX 2.7 15.5 V LMC7101AI, LMC7101BI -40 85 C LMC7101Q-Q1 -40 125 C Supply voltage, V+ Junction Temperature, TJ (1) 4 UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 6.5 Thermal Information LMC7101 THERMAL METRIC (1) DBV (SOT-23) UNIT 5 PINS RJA Junction-to-ambient thermal resistance 170.9 C/W RJC(top) Junction-to-case (top) thermal resistance 124.7 C/W RJB Junction-to-board thermal resistance 30.8 C/W JT Junction-to-top characterization parameter 17.7 C/W JB Junction-to-board characterization parameter 30.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance n/a C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 Electrical Characteristics: 2.7 V Unless otherwise specified, all limits specified for TJ = 25C, V+ = 2.7 V, V- = 0 V, VCM = VO = V+ / 2 and RL > 1 M. PARAMETER TEST CONDITIONS V+ = 2.7 V TYP (1) LMC7101AI MIN 0.11 LMC7101Q-Q1 (2) LMC7101BI MAX MIN 6 MAX MIN 9 UNIT MAX VOS Input offset voltage average drift TCVOS Input offset voltage 9 IB Input bias current -40C TJ 125C 1 64 64 1000 IOS Input offset current -40C TJ 125C 0.5 32 32 2000 RIN Input resistance CMRR Common-mode rejection ratio 0 V VCM 2.7 V V+ = 2.7 V VCM Input common mode voltage range For CMRR 50 dB PSRR Power supply rejection ratio V+ = 1.35 V to 1.65 V V- = -1.35 V to -1.65 V VCM = 0 CIN Common-mode input capacitance mV V/C 1 pA Tera >1 70 55 0 0 3 60 pA 50 50 0 2.7 dB 0 2.7 V 2.7 50 45 45 V dB 3 pF RL = 2 k 2.45 2.15 2.15 2.15 RL = 10 k 2.68 2.64 2.64 2.64 RL = 2 k 0.25 0.5 0.5 0.5 RL = 10 k 0.025 0.06 0.06 0.06 0.5 0.81 0.81 0.81 0.5 0.95 0.95 0.95 VO Output swing, min VO Output swing, max IS Supply current SR Slew rate (3) 0.7 V/s GBW Gain-bandwidth product 0.6 MHz (1) (2) (3) -40C TJ 125C V V mA Typical values represent the most likely parametric normal. When operated at temperature between -40C and 85C, the LMC7101Q-Q1 will meet LMC7101BI specifications. V+ = 15 V. Connected as a voltage follower with a 10-V step input. Number specified is the slower of the positive and negative slew rates. RL = 100 k connected to 7.5 V. Amplifier excited with 1 kHz to produce VO = 10 VPP. Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 5 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 6.7 DC Electrical Characteristics: 3 V Unless otherwise specified, all limits specified for TJ = 25C, V+ = 3 V, V- = 0 V, VCM = 1.5 V, VO = V+ / 2 and RL = 1 M. PARAMETER TEST CONDITIONS TYP (1) 64 1000 0.5 32 32 2000 -40C TJ 125C IOS Input offset current -40C TJ 125C RIN Input resistance CMRR Common-mode rejection ratio 0 V VCM 3 V V+ = 3 V VCM Input common-mode voltage range For CMRR 50 dB PSRR Power supply rejection ratio V+ = 1.5 V to 7.5 V V- = -1.5 V to -7.5 V VO = VCM = 0 80 CIN Common-mode input capacitance RL = 2 k 2.8 RL = 600 0.2 RL = 2 k 2.7 RL = 600 0.37 -40C TJ 125C 0.5 Supply current (1) (2) 6 MAX 64 Input current IS MIN 1 Input offset voltage average drift Output swing, max MAX 9 IB VO MIN 7 TCVOS Output swing, min MAX 6 Input offset voltage VO MIN LMC7101Q-Q1 (2) LMC7101BI 4 VOS -40C TJ 125C LMC7101AI 0.11 7 UNIT mV V/C 1 pA pA Tera >1 74 64 0 0 3.3 60 60 0 3 db 0 3 3 68 60 60 2.6 2.6 2.6 V dB 3 pF 0.4 2.5 0.4 2.5 0.4 2.5 0.6 0.6 0.6 0.81 0.81 0.81 0.95 0.95 0.95 V V mA Typical values represent the most likely parametric normal. When operated at temperature between -40C and 85C, the LMC7101Q-Q1 will meet LMC7101BI specifications. Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 6.8 DC Electrical Characteristics: 5 V Unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = 1.5 V, VO = V+/ 2 and RL = 1 M. PARAMETER TEST CONDITIONS V+ = 5 V TYP (1) LMC7101AI MIN LMC7101Q-Q1 (2) LMC7101BI MAX MIN MAX MIN MAX 0.11 3 7 7 0.11 5 9 9 VOS Input offset voltage TCVOS Input offset voltage average drift IB Input current -40C TJ 125C 1 64 64 1000 IOS Input offset current -40C TJ 125C 0.5 32 32 2000 RIN Input resistance CMRR Positive power supply +PSRR rejection ratio Negative power supply -PSRR rejection ratio VCM mV + V = 5 V, -40C TJ 125C Common-mode rejection ratio Input common-mode voltage range VO 0 V VCM 5 V LMC7101Q-Q1 at 125C 0.2 V VCM 4.8 V db 55 55 V+ = 5 V to 15 V V- = 0 V, VO = 1.5 V 82 70 65 65 V+ = 5 V to 15 V V- = 0 V, VO = 1.5 V -40C TJ 125C 82 65 62 62 V- = -5 V to -15 V V+ = 0 V, VO = -1.5 V 82 70 65 65 V- = -5 V to -15 V V+ = 0 V, VO = -1.5 V -40C TJ 125C 82 65 62 62 dB dB For CMRR 50 dB -0.3 -0.2 -0.2 -0.2 For CMRR 50 dB -40C TJ 125C -0.3 0 0 0.2 V 5.3 5.2 5.2 5.2 5.3 5 5 4.8 3 4.9 4.7 4.7 4.7 RL = 2 k, -40C TJ 125C 4.9 4.6 4.6 4.54 V 0.1 0.18 0.18 0.18 -40C TJ 125C 0.1 0.24 0.24 0.28 RL = 600 4.7 4.5 4.5 4.5 RL = 600 , -40C TJ 125C 4.7 4.24 4.24 4.28 0.5 0.5 0.5 0.3 0.65 0.65 0.8 24 16 16 16 VO = 0 V 24 -40C TJ 125C 24 11 11 9 VO = 5 V 19 11 11 11 VO = 5 V -40C TJ 125C 19 7.5 7.5 5.8 V V 0.3 VO = 0 V 24 -40C TJ 125C V pF RL = 2 k Sinking (1) (2) pA 60 60 Output short circuit current Supply current 60 82 Sourcing IS 65 0 V VCM 5 V LMC7101Q-Q1 at 125C 0.2 V VCM 4.8 V -40C TJ 125C -40C TJ 125C ISC 82 pA Tera >1 Common-mode input capacitance Output swing V/C 1 -40C TJ 125C CIN UNIT V mA mA 0.5 0.85 0.85 0.85 0.5 1 1 1 mA Typical values represent the most likely parametric normal. When operated at temperature between -40C and 85C, the LMC7101Q-Q1 will meet LMC7101BI specifications. Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 7 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 6.9 DC Electrical Characteristics: 15 V Unless otherwise specified, all limits specified for TJ = 25C, V+ = 15 V, V- = 0 V, VCM = 1.5 V, VO = V+ / 2 and RL = 1 M. PARAMETER TEST CONDITIONS TYP (1) LMC7101AI MIN LMC7101Q-Q1 (2) LMC7101BI MAX MIN MAX MIN MAX UNIT VOS Input offset voltage 0.11 mV TCVOS Input offset voltage average drift 1 V/C IB Input current -40C TJ 125C 1 64 64 1000 IOS Input offset current -40C TJ 125C 0.5 32 32 2000 RIN Input resistance CMRR +PSRR Common-mode rejection ratio Negative power -PSRR supply rejection ratio 0 V VCM 15 V LMC7101Q-Q1 at 125C 0.2 V VCM 14.8 V 82 70 65 65 0 V VCM 15 V LMC7101Q-Q1 at 125C 0.2 V VCM 14.8 V -40C TJ 125C 82 65 60 60 V+ = 5 V to 15 V V- = 0 V, VO = 1.5 V 82 70 65 65 82 65 62 62 V- = -5 V to -15 V V+ = 0 V, VO = -1.5 V 82 70 65 65 V- = -5 V to -15 V V+ = 0 V, VO = -1.5 V -40C TJ 125C 82 65 62 62 -0.3 -0.2 -0.2 -0.2 -0.3 0 0 0.2 V+ = 5 V For CMRR 50 dB dB dB dB V + VCM Input common-mode voltage range V =5V For CMRR 50 dB -40C TJ 125C -40C TJ 125C Sourcing AV Large signal voltage gain (3) Sinking Sourcing Sinking CIN VO 8 15.2 15.2 15 15 14.8 340 80 80 80 340 40 40 30 RL = 2 k 24 15 15 15 RL = 2 k -40C TJ 125C 24 10 10 4 300 34 34 34 15 6 6 6 V max V/mV V/mV 3 pF V+ = 15 V RL = 2 k 14.7 14.4 14.4 14.4 V+ = 15 V RL = 2 k -40C TJ 125C 14.7 14.2 14.2 14.2 V 0.16 0.32 0.32 0.32 -40C TJ 125C 0.16 0.45 0.45 0.45 V+ = 15 V RL = 600 14.1 13.4 13.4 13.4 V+ = 15 V RL = 600 -40C TJ 125C 14.1 13 13 12.85 -40C TJ 125C (1) (2) (3) 15.2 15.3 RL = 2 k -40C TJ 125C Input capacitance Output swing 15.3 RL = 2 k RL = 600 pA Tera >1 Positive power supply V+ = 5 V to 15 V rejection ratio V- = 0 V, VO = 1.5 V -40C TJ 125C pA V V 0.5 1 1 1 0.5 1.3 1.3 1.5 V Typical values represent the most likely parametric normal. When operated at temperature between -40C and 85C, the LMC7101Q-Q1 will meet LMC7101BI specifications. V+ = 15 V, VCM = 1.5 V and RL connect to 7.5 V. For sourcing tests, 7.5 V VO 12.5 V. For sinking tests, 2.5 V VO 7.5 V. Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 DC Electrical Characteristics: 15 V (continued) Unless otherwise specified, all limits specified for TJ = 25C, V+ = 15 V, V- = 0 V, VCM = 1.5 V, VO = V+ / 2 and RL = 1 M. PARAMETER TEST CONDITIONS Sourcing Output short circuit current (4) ISC Sinking IS (4) Supply current TYP (1) LMC7101AI MIN LMC7101Q-Q1 (2) LMC7101BI MAX MIN MAX MIN VO = 0 V 50 30 30 30 VO = 0 V -40C TJ 125C 50 20 20 20 VO = 12 V 50 30 30 30 VO = 12 V -40C TJ 125C 50 20 20 20 0.8 -40C TJ 125C MAX UNIT mA 1.5 1.5 1.5 1.71 1.71 1.75 mA Do not short circuit output to V+ when V+ is greater than 12 V or reliability will be adversely affected. 6.10 AC Electrical Characteristics: 5 V Unless otherwise specified, all limits specified for TJ = 25C, V+ = 5 V, V- = 0 V, VCM = 1.5 V, VO = V+ / 2 and RL = 1 M. PARAMETER TYP (1) TEST CONDITIONS f = 10 kHz, AV = -2 RL = 10 k, VO = 4 VPP LMC7101AI LIMIT (2) LMC7101BI LIMIT (2) UNIT THD Total harmonic distortion SR Slew rate 1 V/s GBW Gain bandwidth product 1 MHz (1) (2) 0.01% Typical values represent the most likely parametric normal. All limits are specified by testing or statistical analysis. 6.11 AC Electrical Characteristics: 15 V Unless otherwise specified, all limits specified for TJ = 25C, V+ = 15 V, V- = 0 V, VCM = 1.5 V, VO = V+ / 2 and RL = 1 M. PARAMETER Slew rate (3) SR TEST CONDITIONS V+ = 15 V TYP (1) Gain-bandwidth product m Gm V+ = 15 V MIN MAX MIN 0.5 0.5 0.5 0.4 0.4 0.4 MAX UNIT V/s min MHz Phase margin 45 deg Gain margin 10 Input-referred voltage noise f = 1 kHz, VCM = 1 V 37 In Input-referred current noise f = 1 kHz 1.5 Total harmonic distortion f = 10 kHz, AV = -2 RL = 10 k VO = 8.5 VPP (1) (2) (3) MAX LMC7101Q-Q1 (2) 1.1 en THD MIN LMC7101BI 1.1 + V = 15 V, -40C TJ 125C GBW LMC7101AI dB nV Hz fA Hz 0.01% Typical values represent the most likely parametric normal. When operated at temperature between -40C and 85C, the LMC7101Q-Q1 will meet LMC7101BI specifications. V+ = 15 V. Connected as a voltage follower with a 10-V step input. Number specified is the slower of the positive and negative slew rates. RL = 100 k connected to 7.5 V. Amplifier excited with 1 kHz to produce VO = 10 VPP. Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 9 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 6.12 Typical Characteristics 6.12.1 Typical Characteristics: 2.7 V V+ = 2.7 V, V- = 0 V, TA = 25C, unless otherwise specified. 10 Figure 1. Open Loop Frequency Response Figure 2. Input Voltage vs Output Voltage Figure 3. Gain and Phase vs Capacitance Load Figure 4. Gain and Phase vs Capacitance Load Figure 5. dVOS vs Supply Voltage Figure 6. dVOS vs Common Mode Voltage Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Typical Characteristics: 2.7 V (continued) Figure 7. Sinking Current vs Output Voltage Figure 8. Sourcing Current vs Output Voltage 6.12.2 Typical Characteristics: 3 V V+ = 3 V, V- = 0 V, TA = 25C, unless otherwise specified. Figure 9. Open Loop Frequency Response Figure 10. Input Voltage vs Output Voltage Figure 11. Input Voltage Noise vs Input Voltage Figure 12. Sourcing Current vs Output Voltage Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 11 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics: 3 V (continued) Figure 13. Sinking Current vs Output Voltage Figure 14. CMRR vs Input Voltage 6.12.3 Typical Characteristics: 5 V V+ = 5 V, V- = 0 V, TA = 25C, unless otherwise specified. 12 Figure 15. Open Loop Frequency Response Figure 16. Input Voltage vs Output Voltage Figure 17. Input Voltage Noise vs Input Voltage Figure 18. Sourcing Current vs Output Voltage Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Typical Characteristics: 5 V (continued) Figure 19. Sinking Current vs Output Voltage Figure 20. CMRR vs Input Voltage 6.12.4 Typical Characteristics: 15 V V+ = +15 V, V- = 0 V, TA = 25C, unless otherwise specified. Figure 21. Open Loop Frequency Response Figure 22. Input Voltage vs Output Voltage Figure 23. Input Voltage Noise vs Input Voltage Figure 24. Sourcing Current vs Output Voltage Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 13 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics: 15 V (continued) 14 Figure 25. Sinking Current vs Output Voltage Figure 26. CMRR vs Input Voltage Figure 27. Supply Current vs Supply Voltage Figure 28. Input Current vs Temperature Figure 29. Output Voltage Swing vs Supply Voltage Figure 30. Input Voltage Noise vs Frequency Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Typical Characteristics: 15 V (continued) Figure 31. Positive PSRR vs Frequency Figure 32. Negative PSRR vs Frequency Figure 33. CMRR vs Frequency Figure 34. Open Loop Frequency Response at -40C Figure 35. Open Loop Frequency Response at 25C Figure 36. Open Loop Frequency Response at 85C Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 15 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics: 15 V (continued) Figure 37. Maximum Output Swing vs Frequency Figure 38. Gain and Phase vs Capacitive Load Figure 39. Gain and Phase vs Capacitive Load Figure 40. Output Impedance vs Frequency Figure 41. Slew Rate vs Temperature 16 Submit Documentation Feedback Figure 42. Slew Rate vs Supply Voltage Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Typical Characteristics: 15 V (continued) Figure 43. Inverting Small Signal Pulse Response Figure 44. Inverting Small Signal Pulse Response Figure 45. Inverting Small Signal Pulse Response Figure 46. Inverting Large Signal Pulse Response Figure 47. Inverting Large Signal Pulse Response Figure 48. Inverting Large Signal Pulse Response Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 17 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics: 15 V (continued) 18 Figure 49. Noninverting Small Signal Pulse Response Figure 50. Noninverting Small Signal Pulse Response Figure 51. Noninverting Small Signal Pulse Response Figure 52. Noninverting Large Signal Pulse Response Figure 53. Noninverting Large Signal Pulse Response Figure 54. Noninverting Large Signal Pulse Response Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Typical Characteristics: 15 V (continued) Figure 55. Stability vs Capacitive Load Figure 56. Stability vs Capacitive Load Figure 57. Stability vs Capacitive Load Figure 58. Stability vs Capacitive Load Figure 59. Stability vs Capacitive Load Figure 60. Stability vs Capacitive Load Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 19 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LMC7101 is a single channel, low-power operational amplifier available in a space-saving SOT-23 package, offering rail-to-rail input and output operation across a wide range of power supply configurations. The LMC7101Q-Q1 is the automotive Q-grade variant. 7.2 Functional Block Diagram V+ IN- - OUT IN+ + V- 7.3 Feature Description 7.3.1 Benefits of the LMC7101 Tiny Amplifier 7.3.1.1 Size The small footprint of the SOT-23-5 packaged tiny amplifier, (0.12 x 0.118 inches, 3.05 x 3 mm) saves space on printed circuit boards, and enable the design of smaller electronic products. Because they are easier to carry, many customers prefer smaller and lighter products. 7.3.1.2 Height The 0.056 inches (1.43 mm) height of the tiny amplifier makes is suitable for use in a wide range of portable applications in which a thin profile is required. 7.3.1.3 Signal Integrity Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier package, the tiny amplifier can be placed closer to the signal source, thus reducing noise pickup and increasing signal integrity. The tiny amplifier can also be placed next to the signal destination, such as a buffer, for the reference of an analog-to-digital converter. 7.3.1.4 Simplified Board Layout The tiny amplifier can simplify board layout in several ways. Avoid long PCB traces by correctly placing amplifiers instead of routing signals to a dual or quad device. By using multiple tiny amplifiers instead of duals or quads, complex signal routing and possibly crosstalk can be reduced. 7.3.1.5 Low THD The high open-loop gain of the LMC7101 amp allows it to achieve very low audio distortion--typically 0.01% at 10 kHz with a 10-k load at 5-V supplies. This makes the tiny amplifier an excellent for audio, modems, and low frequency signal processing. 7.3.1.6 Low Supply Current The typical 0.5-mA supply current of the LMC7101 extends battery life in portable applications, and may allow the reduction of the size of batteries in some applications. 20 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Feature Description (continued) 7.3.1.7 Wide Voltage Range The LMC7101 is characterized at 15 V, 5 V and 3 V. Performance data is provided at these popular voltages. This wide voltage range makes the LMC7101 a good choice for devices where the voltage may vary over the life of the batteries. 7.4 Device Functional Modes 7.4.1 Input Common Mode 7.4.1.1 Voltage Range The LMC7101 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 61 shows an input voltage exceeding both supplies with no resulting phase inversion of the output. The absolute maximum input voltage is 300-mV beyond either rail at room temperature. Voltages greatly exceeding this maximum rating, as in Figure 62, can cause excessive current to flow in or out of the input pins, thus adversely affecting reliability. An input voltage signal exceeds the LMC7101 power supply voltages with no output phase inversion. Figure 61. Input Voltage A 7.5-V input signal greatly exceeds the 3-V supply in Figure 63 causing no phase inversion due to RI. Figure 62. Input Signal Applications that exceed this rating must externally limit the maximum input current to 5 mA with an input resistor as shown in Figure 63. Figure 63. RI Input Current Protection for Voltages Exceeding the Supply Voltage Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 21 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Rail-to-Rail Output The approximate output resistance of the LMC7101 is 180- sourcing and 130- sinking at VS = 3 V and 110- sourcing and 80- sinking at VS = 5 V. Using the calculated output resistance, maximum output voltage swing can be estimated as a function of load. 8.1.2 Capacitive Load Tolerance The LMC7101 can typically directly drive a 100-pF load with VS = 15 V at unity gain without oscillating. The unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of operational amplifiers. The combination of the output impedance and the capacitive load of the operational amplifier induces phase lag, which results in either an underdamped pulse response or oscillation. Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 64. This simple technique is useful for isolating the capacitive input of multiplexers and A/D converters. Figure 64. Resistive Isolation of a 330-pF Capacitive Load 8.1.3 Compensating for Input Capacitance When Using Large Value Feedback Resistors When using very large value feedback resistors, (usually > 500 k) the large feed back resistance can react with the input capacitance due to transducers, photo diodes, and circuit board parasitics to reduce phase margins. The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor (as in Figure 65), Cf is first estimated by Equation 1 and Equation 2, which typically provides significant overcompensation. 1 1 2pR1CIN 2pR2Cf (1) R1 CIN R2 Cf (2) Printed circuit board stray capacitance may be larger or smaller than that of a breadboard, so the actual optimum value for CF may be different. The values of CF must be checked on the actual circuit (refer to CMOS Quad Operational Amplifier (SNOSBZ3) for a more detailed discussion). 22 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 Application Information (continued) Figure 65. Cancelling the Effect of Input Capacitance 8.2 Typical Application Figure 66 shows a high input impedance noninverting circuit. This circuit gives a closed-loop gain equal to the ratio of the sum of R1 and R2 to R1 and a closed-loop 3-dB bandwidth equal to the amplifier unity-gain frequency divided by the closed-loop gain. This design has the benefit of a very high input impedance, which is equal to the differential input impedance multiplied by loop gain. (Open loop gain/Closed loop gain.) In DC coupled applications, input impedance is not as important as input current and its voltage drop across the source resistance. The amplifier output will go into saturation if the input is allowed to float, which may be important if the amplifier must be switched from source to source. R2 V+ R1 - IN OUT + V- Figure 66. Example Application Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 23 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) 8.2.1 Design Requirements For this example application, the supply voltage is 5 V, and 100 x 5% of noninverting gain is necessary. The signal input impedance is approximately 10 k. 8.2.2 Detailed Design Procedure Use the equation for a noninverting amplifier configuration; G = 1 + R2 / R1, set R1 to 10 k, and R2 to 99 x the value of R1, which would be 990 k. Replacing the 990-k resistor with a more readily available 1-M resistor will result in a gain of 101, which is within the desired gain tolerance. The gain-frequency characteristic of the amplifier and its feedback network must be such that oscillation does not occur. To meet this condition, the phase shift through amplifier and feedback network must never exceed 180 for any frequency where the gain of the amplifier and its feedback network is greater than unity. In practical applications, the phase shift must not approach 180 because this is the situation of conditional stability. The most critical case occurs when the attenuation of the feedback network is zero. 8.2.3 Application Curve VO (V) VDD Gain = 1 + R2/R1 = 101 (as shown) VIN (mV) Figure 67. Output Response 24 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 LMC7101, LMC7101Q-Q1 www.ti.com SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 9 Power Supply Recommendations For proper operation, the power supplies must be decoupled. For supply decoupling, TI recommends placing 10-nF to 1-F capacitors as close as possible to the operational-amplifier power supply pins. For single supply configurations, place a capacitor between the V+ and V- supply pins. For dual supply configurations, place one capacitor between V+ and ground, and place a second capacitor between V- and ground. Bypass capacitors must have a low ESR of less than 0.1 . 10 Layout 10.1 Layout Guidelines Care must be taken to minimize the loop area formed by the bypass capacitor connection between supply pins and ground. A ground plane underneath the device is recommended; any bypass components to ground must have a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the power-supply inductance and provide a more stable power supply. The feedback components must be placed as close as possible to the device to minimize stray parasitics. 10.2 Layout Example Figure 68. LMC7101 Example Layout Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 Submit Documentation Feedback 25 LMC7101, LMC7101Q-Q1 SNOS719G - SEPTEMBER 1999 - REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support For additional information, see LMC660 CMOS Quad Operational Amplifier (SNOSBZ3). 11.2 Related Links Table 1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMC7101 Click here Click here Click here Click here Click here LMC7101Q-Q1 Click here Click here Click here Click here Click here 11.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright (c) 1999-2015, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q-Q1 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMC7101AIM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A00A LMC7101AIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00A LMC7101AIM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A00A LMC7101AIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00A LMC7101BIM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A00B LMC7101BIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00B LMC7101BIM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A00B LMC7101BIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00B LMC7101QM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT6A LMC7101QM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT6A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 8-Apr-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMC7101AIM5 SOT-23 DBV 5 1000 178.0 8.4 LMC7101AIM5/NOPB SOT-23 DBV 5 1000 178.0 LMC7101AIM5X SOT-23 DBV 5 3000 178.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 LMC7101BIM5 SOT-23 DBV 5 LMC7101BIM5/NOPB SOT-23 DBV LMC7101BIM5X SOT-23 DBV LMC7101BIM5X/NOPB SOT-23 LMC7101QM5/NOPB LMC7101QM5X/NOPB 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC7101AIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101AIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101AIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101BIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101BIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101QM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101QM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LMC7101AIM5 LMC7101AIM5/NOPB LMC7101AIM5X LMC7101AIM5X/NOPB LMC7101BIM5 LMC7101BIM5/NOPB LMC7101BIM5X LMC7101BIM5X/NOPB