MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-1
INDEX
–A–
AC timing (electricals) A-6
ACKERR D-91
Acknowledge error (ACKERR) D-91
ADDR D-80
bus signals 5-20
definition 2-7
signal 5-24
starting address D-17
Address
bus (ADDR) 5-20
-mark wakeup 9-31
space 8-7
encoding 5-21
maps 3-13–3-17
strobe (AS) 5-20
Advanced Microcontroller Unit (AMCU) Literature
1-1
AN 8-3, 8-5
Analog
front-end multiplexer 8-15
input
multiplexed 8-5
port A 8-3
port B 8-4
section contents 8-1
submodule block diagram
8-12
supply pins 8-5
APS D-84
Arbitration 9-3
AS 5-20, 5-26, 5-29, 5-36
ASPC 7-2, 7-3, D-24
Asserted (definition) 2-7
ATEMP 4-21
Auto power save (APS) D-84
AVEC 5-13, 5-22, 5-52, 5-57
enable bit 5-59, D-20
–B–
Background
debug mode 4-19, 5-30
commands 4-22
connector pinout 4-26
enabling 4-20
entering 4-21
registers
fault address register (FAR) 4-23
instruction program counter (PCC) 4-23
return program counter (RPC) 4-23
returning from 4-24
serial
data word 4-26
I/O block diagram 4-25
interface 4-24
peripheral interface protocol (SPI) 4-25
sources 4-20
debugging mode
freeze assertion diagram A-18
serial
communication diagram A-18
timing A-18
Base ID mask bits D-90
Basic operand size 5-24
Baud
clock 9-27
rate generator 9-2
BC D-74
BCD 4-4
Beginning of queue 2 (BQ2) D-34
Berg connector (male) 4-26
BERR 5-25, 5-26, 5-30, 5-35, 5-36, 5-52
assertion results 5-34
BG 5-37, 5-57
BGACK 5-37, 5-57
BGND instruction 4-21
BH D-74
Binary
-coded decimal (BCD) 4-4
divider 8-23
-weighted capacitors 8-15
Bit stuff error (STUFFERR) D-92
BITERR D-91
BITS D-48
encoding field 9-19
Bits per transfer
enable (BITSE) D-53
field (BITS) D-48
BITSE 9-21, D-53
Bit-time 9-26
BIUMCR D-55
BIUSM 10-3
FREEZE D-55
interrupt vector base number (VECT) D-56
LPSTOP 10-4
registers 10-4
module configuration register (BIUMCR) D-55
test configuration register (BIUTEST) D-56
time base register (BIUTBR) D-56
STOP 10-3, D-55
BIUTBR D-56
BIUTEST D-56
BKPT 4-20, 5-30, 5-40, 5-49
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USER’S MANUAL Rev. 15 Oct 2000 Index-2
external signal 4-21
BKPT (TPU asserted) D-74
BL D-74
BLC D-73
Block size (BLKSZ) 5-57, D-17
encoding 5-58, D-17
BM D-74
BME 5-14, D-12
BMT 5-13, D-13
BOFFINT D-92
BOFFMSK D-85
BOOT 7-3, D-24
Boot ROM
control(BOOT) D-24
Bootstrap words (ROMBS) 7-1
Boundary conditions 8-19
BP D-74
BQ2 D-34
BR 5-36, 5-37, 5-57
Branch latch control (BLC) D-73
Break frame 9-27
Breakpoint
acknowledge cycle 5-30
asserted flag (BKPT) D-74
enable bits D-74
flag (PCBK) D-74
hardware breakpoints 5-30
instruction 4-19
mode selection 5-44
operation 5-32
software breakpoints 5-30
Brushless motor commutation (COMM) 11-12
BSA 4-20
BSL D-63
BT D-74
Built-in emulation memory C-1
Bus
arbitration
single device 5-38
timing diagrams
active A-14
idle A-15
cycle
regular 5-26
termination sequences 5-33
error
exception processing 5-35
signal (BERR) 5-13, 5-22, 5-35
timing of 5-35
grant (BG) 5-37
grant acknowledge (BGACK) 5-37
interface
unit submodule.
See
BIUSM 10-1, 10-3
monitor 5-13
external enable (BME) D-12
timeout period 5-13
timing (BMT) 5-13, D-13
off interrupt
(BOFFINT) D-92
mask (BOFFMSK) D-85
request (BR) 5-37
select (BSL) D-63
state analyzer (BSA) 4-20
BUSY 13-5, 13-15
BYP 8-14, D-36
Bypass mode 8-14
BYTE (upper/lower byte option) 5-58, D-18
–C–
C (carry) flag 4-6, D-4
CAN2.0B
controller module.
See
TouCAN 13-1
protocol 13-1
system 13-2
CANCTRL0 D-85
CANCTRL1 D-87
CANCTRL2 D-88
CANICR D-85
CANMCR D-82
CANRX/TX pins 13-2
CCL D-74
CCR 4-6
CCW 8-1, 8-28, D-36
CF1 D-34
CF2 D-34
CFSR D-75
CH D-75, D-77, D-78
CHAN D-36
CHANNEL D-76
Channel
assignments
multiplexed D-38
nonmultiplexed D-37
conditions latch (CCL) D-74
control registers 11-15
function select registers 11-15
interrupt
base vector (CIBV) D-75
enable
/disable field (CH) D-75
and status registers 11-15
request level (CIRL) D-75
status (CH) D-78
invalid D-37
number (CHAN) D-36
orthogonality 11-4
priority registers 11-17
register breakpoint flag (CHBK) D-74
reserved D-37
CHBK D-74
Chip-select
base address
register boot ROM (CSBARBT) D-17
registers (CSBAR) 5-56, 5-57, D-17
reset values 5-62
operation 5-59
option
register boot ROM (CSORBT) D-18
registers (CSOR) 5-56, 5-58, D-18
reset values 5-62
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-3
pin
assignment registers (CSPAR) 5-55, D-15
field encoding 5-57, D-16
pin
assignments D-16
reset operation 5-61
signals for interrupt acknowledge 5-60
timing diagram A-17
CIBV D-75
CIE1 D-31
CIE2 D-32
CIER 11-15, D-75
CIRL D-75
CISR 11-13, 11-15, D-78
Clear (definition) 2-7
CLK D-59, D-60, D-68
CLKOUT 5-25, 5-40
output timing diagram A-8
CLKRST (clock reset) 5-40
CLKS D-73
Clock
block diagram 8-24
control
multipliers 5-7
timing (electricals) A-3
generation 8-23
input pin status (FCSM) D-58
input pin status (MCSM) D-60
mode
pin (MODCLK) 5-43
selection 5-43
output (CLKOUT) 5-25
phase (CPHA) D-48
polarity (CPOL) D-48
rate selection (CLK) field D-68
synthesizer
control register (SYNCR) D-7
operation 5-5
Code 13-4
COF D-58, D-59
Coherency 8-6, 8-22, 11-4
COMM 11-12
Command
RAM 9-9
word pointer (CWP) D-36
Common in-circuit emulator 4-20
Comparator 8-15
Completed queue pointer (CPTQP) D-52
Condition code register (CCR) 4-6, 11-5
CONT D-53
Contention 5-51
Continue (CONT) D-53
Continuous transfer mode 9-7
Conventions 2-7
Conversion
command word table (CCW) 8-1, 8-16, 8-28
cycle times 8-13
stages 8-30
Counter
clock select (CLK) field
FCSM D-59
MCSM D-60
overflow flag (COF) bit D-58, D-59
prescaler submodule.
See
CPSM 10-4
CPCR D-57
CPHA 9-17, D-48
CPOL 9-17, D-48
CPR D-77
CPSM 10-4
block diagram 10-5
registers 10-5
control register (CPCR) D-57
test register (CPTR) D-57
CPTQP 9-9, D-52
CPTR D-57
CPU
space
address encoding 5-30
cycles 5-29
encoding for interrupt acknowledge 5-60
CPU32 5-39
address registers/address organization in 4-5
addressing modes 4-9
block diagram 4-2
data registers 4-4
data organization 4-5
development support 4-18
exception processing 4-16
features 3-1
generated message encoding 4-26
instructions 4-10
LPSTOP 4-15
MOVEC 4-7
MOVES 4-7
RESET 5-40
special control instructions 4-15
table lookup and interpolate (TBL) 4-15
umimplemented MC68020 instructions 4-10
loop mode 4-15
memory organization 4-7
processing states 4-9
register
mnemonics 2-2
model 4-3, D-2
registers 4-2
alternate function code registers (SFC/DFC) 4-7
condition code register (CCR) 4-6, D-3
control registers 4-6
program counter (PC) 4-1
stack pointer (SP) 4-1
status register (SR) 4-6, D-3
vector base register (VBR) 4-7
virtual memory 4-9
CPU32 Reference Manual
4-1
CR D-53
CRCERR D-91
CREG D-21
CSBAR D-17
CSBARBT D-17
CSBOOT 5-49, 5-55, 5-57, 7-3
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-4
reset values 5-63
CSOR D-18
CSORBT D-18
CSPAR D-15
CTD9 D-60
CTM Reference Manual
10-1
CTM2C D-60
CTM4
address map 10-2, D-54
block diagram 10-1
bus interface unit submodule (BIUSM) 10-3
components 10-1
counter prescaler submodule (CPSM) 10-4
double-action submodule (DASM) 10-10
features 3-2
free-running counter submodule (FCSM) 10-5
interrupt priority and vector/pin allocation 10-20
interrupts 10-19
modulus counter submodule (MCSM) 10-5, 10-7
pulse width modulation submodule (PWMSM) 10-13
CWP D-36
Cyclic redundancy check error (CRCERR) D-91
–D–
DAC 8-1
DASM 10-10
block diagram 10-12
channels 10-11
interrupts 10-12
mode flag status bit states D-62
modes of operation 10-11
registers 10-12
data register A (DASMA) D-65
data register B (DASMB) D-65
status/interrupt/control register (DASMSIC)
D-62
timing (electricals) A-30
DASMA D-65
operations D-65
DASMB D-65
operations D-66
DASMSIC D-62
DATA 5-20
Data
and size acknowledge (DSACK) 5-13, 5-22
bus
mode selection 5-41
signals (DATA) 5-20
field for RX/TX frames (TouCAN) 13-4
frame 9-27
multiplexer 5-24
strobe (DS) 5-20
types 4-4
DATA (definition) 2-7
DBcc 4-16
DC characteristics (electricals) A-4
DCNR D-78
DDRE 5-63, D-9
DDRF 5-63, D-11
DDRQA 8-2, D-29
DDRQS 9-4, 9-17, 9-21, D-46
Delay
after transfer (DT) 9-19, D-53
before SCK (DSCKL) D-49
Designated CPU space 5-21
Development
support and test registers (TPU) 11-17
tools and support C-1
DFC 4-7
Digital
control section
contents 8-1, 8-16–??
input
/output port (PQA) 8-4
port (PQB) 8-4
to analog converter (DAC) 8-1, 8-15
DIO 11-6
DIS D-65, D-66
Disabled mode 8-20
Discrete input/output (DIO) 11-6
Distributed register (DREG) D-21
DIV8 clock 11-14
Divide by 2/divide by 3 (DIV23) D-57
Double
-action submodule.
See
DASM 10-10
-buffered 9-28, 9-30
bus fault 4-21, 5-35
-row header 4-26
DREG D-21
Drive time base bus (DRV) D-58, D-60
DRV D-58, D-60
DS 5-20, 5-26, 5-36
DSACK 5-13, 5-25, 5-26, 5-30, 5-52, 5-57, 5-59
assertion results 5-34
external/internal generation 5-29
option fields 5-29
signal effects 5-23
source specification in asynchronous mode 5-59,
D-19
DSCK D-54
DSCKL D-49
DSCLK 4-25
DSCR D-73
DSSR D-74
DT D-53
DTL D-50
Dynamic bus sizing 5-23
–E–
EBI 5-51
ECLK 5-10
bus timing A-19
output timing diagram A-9
timing diagram A-20
Edge polarity (EDPOL) bit D-64
EDGEN D-60
EDGEP D-60
EDIV 5-10, D-8
EDPOL D-64
EMPTY 13-5
EMU 11-5, 11-15, D-72
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USER’S MANUAL Rev. 15 Oct 2000 Index-5
EMUL D-24
Emulation
control (EMU) 11-15, D-72
mode control (EMUL) D-24
support 11-5
EN D-68
Encoded
one of three channel priority levels (CH) D-77
time function for each channel (CHANNEL) D-76
type of host service (CH) D-77
Ending queue pointer (ENDQP) D-51
End-of-
frame (EOF) 13-16
queue condition 8-30
ENDQP 9-9, D-51
EOF 13-16
ERRINT D-93
ERRMSK D-86
Error
conditions 9-30
counters 13-9
detection circuitry 9-2
interrupt (ERRINT) D-93
interrupt mask (ERRMSK) D-86
ESTAT D-91
ETRIG 8-4
Event flag (FLAG) D-62
Event timing 11-3
Exception
instruction (RTE) 5-35
processing 4-16, 5-39
sequence 4-18
types of exceptions 4-17
vectors 4-16
exception vector assignments 4-17
vector 5-39, 11-6
EXOFF D-6
EXT D-9
Extended message format 13-1
frames 13-4
External
bus
arbitration 5-37
clock
division (EDIV) D-8
division bit (EDIV) 5-10
operation during LPSTOP 5-11
signal (ECLK) 5-10
interface (EBI) 5-18
control signals 5-20
clock input timing diagram A-8
clock off (EXOFF) D-6
digital supply pin 8-6
multiplexing 8-10
reset (EXT) D-9
trigger pins 8-4
Externally
input clock frequency D-14
multiplexed mode (MUX) D-30
EXTRST (external reset) 5-47
–F–
Factory test 5-64
FAR 4-23
Fast
quadrature decode (FQD) 11-12
reference 5-4
circuit 5-4
termination
cycles 5-25, 5-28
read cycle timing diagram A-12
write cycle timing diagram A-13
Fast reference frequency D-14
Fault confinement state (FCS) 13-10, D-92
FC 5-21
FCS 13-10, D-92
FCSM 10-5
block diagram 10-6
clock sources 10-6
counter 10-6
external event counting 10-7
interrupts 10-7
registers 10-7
counter register (FCSMCNT) D-59
status/interrupt/control register (FCSMSIC)
D-58
time base bus drivers 10-7
timing (electricals) A-29
FCSMCNT D-59
FCSMSIC D-58
FE 9-30, D-45
Final sample time 8-13
FLAG D-62, D-66
FORCA D-63
FORCB D-63
Force (FORCA/B) D-63
FORMERR D-91
fPWM 10-17
fQCLK 8-23
FQD 11-12
FQM 11-12
Frame 9-27
size 9-30
Frames
overload 13-16
remote 13-15
Framing error (FE) flag 9-30, D-45
Free-running counter submodule.
See
FCSM 10-5
FREEZ ACK 13-16
FREEZE
assertion response (FRZ)
BIUSM 10-3, D-55
QADC 8-7, D-27
QSM 9-3, D-40
SIM 5-3
TouCAN D-82
TPU D-73
bus monitor (FRZBM) 5-3, D-6
software enable (FRZSW) 5-3, D-6
Frequency
control
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-6
counter (Y) D-8
prescaler (X) D-8
VCO (W) D-8
measurement (FQM) 11-12
FRZ 8-7, 13-11, D-27, D-40, D-73, D-82
FRZACK 13-11, D-83
FRZBM 5-3, D-6
FRZSW 5-3, D-6
fsys 8-24, 10-17, D-7
F-term encoding 5-29
FULL 13-5
Function
code (FC) signals 5-21, 5-29
library for TPU 11-5
–G–
Global registers 8-2
–H–
Hall effect decode (HALLD) 11-13
HALLD 11-13
HALT 13-11, D-51, D-83
HALT 5-14, 5-22, 5-25, 5-26, 5-36
assertion results 5-34
Halt
acknowledge flag (HALTA) D-52
monitor
enable (HME) 5-14, D-12
reset (HLT) D-9
operation 5-36
negating/reasserting 5-36
QSPI (HALT) D-51
TouCAN S-clock (HALT) D-83
HALTA D-52
HALTA/MODF interrupt enable (HMIE) bit D-51
Handshaking 5-25
Hang on T4 (HOT4) D-73
Hardware breakpoints 5-30
HLT D-9
HME 5-14, D-12
HMIE D-51
Host
sequence registers 11-16
service registers 11-16
HOT4 D-73
HSQR D-76
HSSR D-77
Hysteresis 5-50
–I–
I/O port operation 8-8
IARB
BIUSM D-56
QADC 8-8, D-28
QSM D-40
SIM 5-2, 5-3, 5-51, D-7
TouCAN D-85
TPU 11-5, D-73
IARB3 D-58, D-60, D-62, D-67
IC D-65, D-66
ICD16/ICD32 C-1
ID
Extended (IDE) field 13-6
HIGH field 13-6
LOW field 13-6
IDD 5-45
IDE 13-6
Identifier (ID) 13-1
bit field 13-6
IDLE 9-30, D-44, D-92
Idle
CAN status (IDLE) D-92
frame 9-27
-line
detect type (ILT) D-43
detected (IDLE) 9-30, D-44
detection process 9-30
interrupt enable (ILIE) 9-31, D-43
type (ILT) bit 9-31
IFLAG D-93
IL D-58, D-60, D-62, D-67
ILIE 9-31, D-43
ILQSPI D-41
ILSCI D-41
ILT 9-31, D-43
IMASK D-93
IMB 8-1, 10-1
IN D-58, D-63
IN1 D-60
IN2 D-60
In-circuit debugger (ICD16/ICD32) C-1
Information processing time (IPT) 13-9
Initial sample time 8-13
Input
capture/input transition counter (ITC) 11-6
pin status (IN)
DASM D-63
sample time (IST) 8-26, D-36
Interchannel communication 11-4
Intermission 13-16
Intermodule bus (IMB) 3-3, 8-1, 10-1
Internal
bus
error (BERR) 5-13, 5-14
monitor 5-13
clock signals (PCLK) D-61
register map 3-12
Interrupt
acknowledge
and arbitration 5-51
bus cycles 5-53
arbitration 5-2, 9-3
IARB field
BIUSM D-56
QADC 8-8, D-28
QSM D-40
SIM 5-2, 5-3, 5-51, D-7
TouCAN D-85
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USER’S MANUAL Rev. 15 Oct 2000 Index-7
TPU 11-5, D-73
IARB3 bit
DASM D-62
FCSM D-58
MCSM D-60
PWMSM D-67
exception processing 5-49
initializing 8-33
level (IL)
DASM D-62
FCSM D-58
for QSPI (ILQSPI) D-41
for SCI (ILSCI) D-41
MCSM D-60
PWMSM D-67
priority
and recognition 5-50
level field (IPL) 5-59, D-20
mask (IP) field 4-6, 5-50, 9-3, 11-5, D-3
processing summary 5-52
request level (IRL) bit field D-85
sources 8-31
vector
base (IVB) field D-28
base address (IVBA) field D-85
number 9-3
field (INTV) D-41
vectors for QADC 8-32
Interrupts
CTM4 10-19
DASM 10-12
FCSM 10-7
MCSM 10-9
QADC 8-31
QSM 9-3
SIM 5-49
TouCAN 13-18
TPU 11-5
Inter-transfer delay 9-6
INTV D-41
Invalid channel number D-37
IP 9-3, 11-5
IPL D-20
IPM D-65, D-66
IPT 13-9
IPWM D-65, D-66
IRL D-85
IRLQ1 D-28
IRLQ2 D-28
IRQ 5-50, 5-52, 11-5
ISB 6-2
IST 8-26, D-36
ITC 11-6
IVB 8-32, D-28
IVBA D-85
–L–
LBUF D-87
Least significant bit (LSB) 8-15
Left justified
signed result word table (LJSRR) D-38
unsigned result word table (LJURR) D-38
Length of delay after transfer (DTL)
D-50
Level-sensitivity 5-50
LJSRR D-38
LJURR D-38
LOAD D-67
LOC D-9
LOCK 7-3, D-24
Lock
/release/busy mechanism 13-14
registers (LOCK) D-24
Logic
analyzer pod connectors C-2
levels (definition) 2-7
LOOP D-87
Loop
back (LOOP) D-87
mode 4-15
(LOOPS) D-42
instruction sequence 4-15
LOOPQ D-51
LOOPS D-42
Loss of clock reset (LOC) D-9
Low power stop (LPSTOP)
BIUSM 10-4
broadcast cycle 5-33
CPU space cycle 5-33
CPU32 4-15
interrupt mask level 5-33
MRM 7-3
QADC 8-6
QSM 9-2
SIM 5-18
SRAM 6-2
TPU 11-15
TPURAM 12-3
Lowest buffer transmitted first (LBUF) D-87
Low-power
stop mode enable (STOP)
BIUSM D-55
MRM D-23
QADC D-27
QSM D-40
SRAM D-21
TouCAN D-82
TPU D-71
TPURAM D-80
LPSTOP 4-15, 5-11, 5-18, 5-33, 10-4
LR D-78
LSB 2-7, 4-4, 8-15
LSW 2-7
–M–
M 9-27, D-43
M68000 family
compatibility 4-14
development support 4-19
M68MEVB1632 C-1
modular evaluation board (MEVB) C-1
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-8
M68MMDS1632 C-1
Mask
examples for normal/extended messages 13-8
registers (RX) 13-7
Masked ROM module (MRM).
See
MRM 7-1
Master
/slave mode select (MSTR) D-47
shift registers (TSTMSR) D-20
Maximum
ratings (electrical) A-1
MC68010 4-14
MC68020 4-10, 4-14
MCSM 10-5, 10-7
block diagram 10-8
clock sources 10-9
counter 10-8
external event counting 10-9
interrupts 10-9
modulus latch 10-8
registers 10-10
counter register (MCSMCNT) D-61
modulus latch register (MCSMML) D-61
status/interrupt/control register (MCSMSIC)
D-59
time base bus drivers 10-9
timing (electricals) A-29
MCSMCNT D-61
MCSMML D-61
MCSMSIC D-59
MCU
basic system 5-19
block diagram 3-4
features 3-1
personality board (MPB) C-1
pin assignment package
MC68336 160-pin package 3-5, B-1
MC68376 160-pin package 3-6, B-2
Mechanical information B-4
Memory
CPU32 organization 4-7
maps
overall memory 3-14
separate supervisor and user space 3-15
supervisor space (separate program/data space)
3-16
user space (separate program/data space) 3-17
virtual 4-9
Message
buffer
address map D-82
code for RX/TX buffers 13-5
deactivation 13-13
structure 13-3
format error (FORMERR) D-91
Mid-analog supply voltage 8-15
Misaligned operand 5-24
MISO 9-17, 9-21
MM 6-1, 7-1, 9-2, D-7
MMDS C-1
Mnemonics
pin and signal 2-2
range (definition) 2-7
register 2-4
specific (definition) 2-7
MODCLK 5-48
MODE 5-58, D-18, D-64
Mode
fault flag (MODF) 9-10, D-52
select (M) D-43
Modes
disabled 8-20
reserved 8-20
scan.
See
Scan modes
MODF 9-10, D-52
Modular platform board C-1
Module
mapping (MM) bit 5-2, 6-1, 7-1, 9-2, D-6, D-7
pin functions 5-44
Modulus
counter 9-27
counter submodule (MCSM).
See
MCSM 10-5, 10-7
load
edge sensitivity (EDGEN, EDGEP) bits D-60
input pin status (IN1) D-60
MOSI 9-17, 9-21
Most significant bit (MSB) 8-15
Motorola
Microcontroller Development Tools Directory
(MCUDEVTLDIR/D Rev. 3) C-1
modular development system (MMDS) C-1
MPB C-1
MQ1 D-31
MQ2 D-32
MRM 7-1
address map D-23
array address mapping 7-1
features 3-1
low-power stop operation 7-3
normal access 7-2
registers
module configuration register (MRMCR) 7-1,
D-23
ROM
array base address registers (ROM-
BAH/BAL) 7-1, D-25
bootstrap words (ROMBS) 7-1, D-26
signature registers (RSIGHI/LO) 7-1, D-25,
D-26
reset 7-3
ROM signature 7-3
MRMCR 7-1, D-23
MSB 2-7, 4-4, 8-15
MSTR D-47
MSTRST (master reset) 5-40, 5-47, 5-49
MSW 2-7
Multichannel pulse width modulation (MCPWM) 11-11
Multimaster operation 9-10
Multiplexed analog inputs 8-5
MUX 8-8, D-30
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-9
–N–
N (negative) flag 4-6, D-4
NCLOCK 10-17
Negated (definition) 2-7
New
input capture/transition counter (NITC) 11-11
queue pointer value (NEWQP)
D-51
NEWQP 9-9, 9-22, D-51
NF 9-30, D-45
NITC 11-11
Noise
error flag (NF) D-45
errors 9-30
flag (NF) 9-30
Non-maskable interrupt 5-50
NOT ACTIVE 13-5
Not ready (NOTRDY) 13-3
NOTRDY 13-3, 13-16, D-83
NPERIOD 10-17
NRZ 9-2
–O–
OC 11-7
OCAB D-65, D-66
OCB D-65, D-66
On-chip breakpoint hardware 4-27
OP (1 through 3) 5-23
Opcode tracking 4-26
Open drain drivers 8-4
Operand
alignment 5-24
byte order 5-24
destination 4-4
misaligned 5-24
source 4-4
transfer cases 5-24
Operators 2-1
OPWM D-65, D-66
OR D-44
Ordering information B-4
Output
compare (OC) 11-7
driver types 3-8
flip-flop 10-14
pin
polarity control (POL) bit D-67
status (PIN) bit D-67
Overload frames 13-16
OVERRUN 13-5
Overrun error (OR) D-44
–P–
P D-36
Parallel I/O ports 5-63
Parentheses (definition) 2-7
Parity
(PF) flag 9-30
checking 9-28
enable (PE) D-43
error (PF) bit D-45
errors 9-30
type (PT) D-43
type (PT) bit 9-28
Pause (P) 8-17, D-36
PCBK D-74
PCC 4-23
PCLK D-61
PCLK6 D-57
PCS D-54
to SCK delay (DSCK) D-54
PCS0/SS 9-21
PE D-43
PEPAR 5-63, D-10
Period
/pulse width accumulator (PPWA) 11-9
and pulse width register load control (LOAD) bit D-67
completion status (FLAG) bit D-66
measurement
additional transition detect (PMA) 11-7
missing transition detect (PMM) 11-8
Periodic
/interval timer 8-27
interrupt
control register (PICR) 5-17, D-13
modulus counter 5-16
priority 5-17
request level (PIRQL) 5-17, D-13
timer 5-16
components 5-16
modulus (PITM field 5-16
PIT period calculation 5-17, D-14
register (PITR) D-13
timing modulus (PITM) D-13
vector (PIV) 5-17, D-13
timer prescaler control (PTP) 5-16, D-13
Peripheral
breakpoints 4-21
chip-selects (PCS) 9-22, D-54
PF 9-30, D-45
PF1 D-34
PF2 D-34
PFPAR 5-63, D-11
Phase buffer segment 1/2 (PSEG1/2) bit field D-88
PICR 5-17, 5-52, D-13
PIE1 D-31
PIE2 D-32
PIN D-67
Pin
characteristics 3-7
electrical state 5-45
function 5-45
reset states 5-46
PIRQL 5-17, D-13
PITM 5-16, D-13
PITR 5-16, D-13
PIV 5-17, D-13
PMA 11-7
PMM 11-8
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-10
Pointer 9-7
POL D-67
Port
parallel I/O in SIM 5-63
replacement unit (PRU) C-2
size 5-57
Port C data register (PORTC) 5-59, D-14
Port E
data direction register (DDRE) 5-63, D-9
data register (PORTE) 5-63, D-9
pin assignment register (PEPAR) 5-63, D-10
Port F
data direction register (DDRF) 5-63, D-11
data register (PORTF) 5-63, D-10
pin assignment register (PFPAR) 5-63, D-11
PORTC D-14
PORTE 5-63, D-9
PORTF 5-63, D-10
PORTQA 8-2, D-29
PORTQB 8-2, D-29
PORTQS 9-4, D-45
Position-synchronized pulse generator (PSP) 11-8
POW D-9
Power
connections 3-8
consumption reduction 5-11
-up reset (POW) D-9
PPWA 11-9
PQA 8-4, 8-9
PQB 8-4, 8-9
PQSPAR 9-4, 9-17, 9-21, D-46
Prescaler
add a tick (PSA) 8-24, D-30
clock
(PSCK) D-73
high time (PSH) 8-24, D-30
low time (PSL) 8-24, D-30
control
for TCR1 11-13
for TCR2 11-14
divide
factor field D-88
register (PRESDIV) 13-8, D-88
division ratio select (PSEL) D-57
field values for QACR0 8-25
running (PRUN) D-57
PRESDIV (bit field) D-88
PRESDIV (register) 13-8, 13-9, D-88
Program counter (PC) 4-1, 4-6
Programmable
channel service priority 11-4
time accumulator (PTA) 11-11
transfer length 9-6
Propagation segment time (PROPSEG) D-87
PROPSEG 13-11, D-87
PRU C-2
PRUN D-57
PSA 8-24, 8-26, D-30
PSCK 11-13, D-73
PSEG1 D-88
PSEG2 13-9, 13-11, D-88
PSEGS1 13-11
PSEL D-57
PSH 8-24, D-30
PSL 8-24, D-30
PSP 11-8
PT 9-28, D-43
PTA 11-11
PTP D-13
Pulse width modulation
submodule.
See
PWMSM 10-13
TPU waveform (PWM) 11-7
PWM 11-7
duty cycle boundary cases
10-18
PWMA D-69
PWMB D-69
PWMC D-70
PWMSIC D-66
PWMSM 10-13
block diagram 10-14
clock selection 10-14
coherency 10-16
counter 10-15
enable (EN) D-68
output flip-flop 10-14
period registers and comparator 10-15
pulse width registers and comparator 10-16
PWM
frequency 10-17
period and pulse width register values 10-18
pulse width 10-18
registers 10-19
PWM
counter register (PWMC) D-70
period register (PWMA) D-69
pulse width register (PWMB) D-69
status/interrupt/control register (PWMSIC)
D-66
timing (electricals) A-31
–Q–
QACR0 8-2, 8-27, D-30
QACR1 8-2, 8-28, D-31
QACR2 8-2, 8-28, D-32
QADC
address map D-26
clock (QCLK) 8-14
conversion characteristics (operating) A-28
electrical characteristics (operating)
AC A-27
DC A-26
features 3-2
maximum ratings A-25
pin functions diagram 8-3
registers
control register 0 (QACR0) 8-2, 8-27, D-30
control register 1 (QACR0) 8-2, 8-28
control register 1 (QACR1) D-31
control register 2 (QACR0) 8-2, 8-28
control register 2 (QACR2) D-32
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-11
conversion command word table (CCW) D-36
interrupt register (QADCINT) 8-2, D-28
module configuration register (QADCMCR) 8-2,
8-6, D-27
port
A data register (PORTQA) 8-2
B data register (PORTQB) 8-2
data direction register (DDRQA) 8-2
QA data direction register (DDRQA) D-29
QA data register (PORTQA) D-29
QB data register (PORTQB) D-29
result word table D-38
status register (QASR) 8-2, 8-28, D-34
test register (QADCTEST) 8-2, D-28
QADCINT 8-2, D-28
QADCMCR 8-2, 8-6, D-27
QADCTEST 8-2, D-28
QASR 8-2, 8-28, D-34
QCLK 8-14, 8-23
frequency 8-23
QDEC 11-10
QILR 9-2, D-41
QIVR 9-2, D-41
QOM 11-11
QS D-35
QSM
address map 9-2, D-39
block diagram 9-1
features 3-2
general 9-1
initialization sequence 9-32
interrupts 9-3
pin function 9-5, D-47
QSPI 9-5
operating modes 9-10
operation 9-9
pins 9-9
RAM 9-8
registers 9-7
reference manual 9-1
registers
command RAM (CR) D-53
global registers 9-2
interrupt
level register (QILR) 9-2, D-41
vector register (QIVR) 9-2, D-41
test register (QTEST) 9-2
module configuration register (QSMCR) D-40
pin control registers 9-4
port QS
data direction register (DDRQS) 9-4,
D-46
data register (PORTQS) 9-4, D-45
pin assignment register (PQSPAR)
D-46
QSPI
control register 0 (SPCR0) D-47
control register 1 (SPCR1) D-49
control register 2 (SPCR2) D-50
control register 3 (SPCR3) D-51
status register (SPSR) D-51
receive data RAM (RR) D-52
SCI
control register 0 (SCCR0) D-42
control register 1 (SCCR1) D-42
data register (SCDR) D-45
status register (SCSR) D-44
test register (QTEST) D-40
transmit data RAM (TR) D-53
types 9-2
SCI 9-22
operation 9-26
pins 9-26
registers 9-22
QSMCR D-40
QSPI 9-1, 9-5
block diagram 9-6
enable (SPE) D-49
finished flag (SPIF) D-52
initialization operation 9-11
loop mode (LOOPQ) D-51
master operation flow 9-12
operating modes 9-10
master mode 9-10, 9-17
wraparound mode 9-20
slave mode 9-10, 9-20
wraparound mode 9-22
operation 9-9
peripheral chip-selects 9-22
pins 9-9
RAM 9-8
command RAM 9-9
receive RAM 9-8
transmit RAM 9-8
registers 9-7
control registers 9-7
status register 9-8
timing A-21
master A-22
slave A-23
QTEST 9-2, D-40
Quadrature decode (QDEC) 11-10
Quad-word data 4-4
Queue 8-16
pointers
completed queue pointer (CPTQP) 9-9
end queue pointer (ENDQP) 9-9
new queue pointer (NEWQP)
9-9
status (QS) D-35
Queue 1
completion
flag (CF1) D-34
interrupt enable (CIE1) D-31
interrupt level (IRLQ1) D-28
operating mode (MQ1) D-31
pause
flag (PF1) D-34
interrupt enable (PIE1) D-31
single-scan enable (SSE1) D-31
trigger overrun (TOR1) D-34
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-12
Queue 2
completion
flag (CF2) D-34
interrupt enable (CIE2) D-32
interrupt level (IRLQ2) D-28
operating mode (MQ2) D-32
pause
flag (PF2) D-34
interrupt enable (PIE2) D-32
resume (RES) D-33
single-scan enable bit (SSE2) D-32
trigger overrun (TOR2) D-35
Queued
analog-to-digital converter.
See
QADC 8-1
output match (QOM) 11-11
serial
module (QSM).
See
QSM 9-1
peripheral interface (QSPI) 9-1, 9-5
–R–
R/W 5-21, 5-26
field 5-58, D-18
RAF D-44
RAM
array
disable (RAMDS) D-80
space (RASP) D-22
base address lock (RLCK) bit D-22
RAMBAH 6-1, D-22
RAMBAL 6-1, D-22
RAMDS 12-1, D-80
RAMMCR 6-1, D-21
RAMTST 6-1, D-22
RASP 6-1, D-22, D-80
encoding D-22
RDR 9-26
RDRF 9-30, D-44
RE 9-30, D-43
Read
/write signal (R/W) 5-21
cycle 5-27
flowchart 5-27
timing diagram A-10
system register command (RSREG) 4-22
Receive
data
(RXD) pin 9-26
register full (RDRF) D-44
error status flag (RXWARN) D-92
pin configuration control (RXMODE) D-86
RAM 9-8
time sample clock (RT) 9-28, 9-30
Receiver
active (RAF) D-44
data register (RDRF) flag 9-30
enable (RE) 9-30, D-43
interrupt enable (RIE) D-43
wakeup (RWU) 9-31, D-43
Reception of transmitted frames 13-13
Remote
frames 13-15
transmission request (RTR) 13-4, 13-6
RES 8-30, D-33
Reserved
channel number D-37
mode 8-20
RESET 4-20, 5-39, 5-41, 5-45, 5-46
Reset
control logic in SIM 5-39
exception processing 5-39
mode selection
timing diagram A-17
use in determining SIM configuration 5-40
module pin function out of reset 5-44
operation in SIM 5-39
power-on 5-47
processing summary 5-48
source summary in SIM 5-40
states of pins assigned to other MCU modules 5-46
status register (RSR) 5-13, 5-49, D-8
timing 5-46
Resistor-divider chain 8-15
Resolution time 8-13
Result word table 8-1, 8-16, 8-31
Resynchronization jump width (RJW) bit field D-88
Retry operation 5-36
RIE D-43
Right justified, unsigned result word table (RJURR) D-38
RJURR D-38
RJW 13-11, D-88
RLCK 6-1, D-22
RMC 3-8, 3-10, 3-12, 5-37
ROM array space (ASPC) D-24
ROMBAH 7-1, D-25
ROMBAL 7-1, D-25
ROMBS 7-1
ROMBS0-3 D-26
RPC 4-23
RR D-52
RS-232C terminal C-2
RSIGHI 7-1, 7-3, D-25, D-26
RSIGLO 7-1, 7-3, D-25, D-26
RSR 5-13, D-8
RSREG 4-22
RT 9-30
RTE 5-35
RTR 13-4, 13-6, 13-15
RWU 9-31, D-43
RX
Length 13-4
RX14MSKHI D-90
RX14MSKLO D-90
RX15MSKHI D-90
RX15MSKLO D-90
RXD 9-26
RXECTR D-94
RXGMSKHI D-90
RXGMSKLO D-90
RXMODE D-86
RXWARN D-92
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-13
–S–
S D-3
SAMP D-87
Sample amplifier bypass (BYP) D-36
Sampling mode (SAMP) D-87
SAR 8-1, 8-16
SASM
timing (electricals) A-30
SBK 9-29, D-44
Scan modes
SCBR D-42
SCCR 9-23
SCCR0 D-42
SCCR1 D-42
SCDR 9-26, D-45
SCI 9-1, 9-2, 9-17, 9-22
baud
clock 9-27
rate (SCBR) D-42
equation D-42
idle-line detection 9-30
internal loop 9-32
operation 9-26
parity checking 9-28
pins 9-26
receiver
block diagram 9-25
operation 9-30
wakeup 9-31
registers 9-22
control registers (SCCR) 9-23
data register (SCDR) 9-26
status register (SCSR) 9-26
transmitter
block diagram 9-24
operation 9-28
SCK 9-16, 9-21
actual delay before SCK (equation) 9-18
baud rate (equation) 9-18
S-clock 13-8
SCSR 9-26, D-44
Self wake enable (SELFWAKE) D-84
Send break (SBK) 9-29, D-44
Serial
clock baud rate (SPBR) D-49
communication interface (SCI) 9-1, 9-22
formats 9-27
interface 4-24
mode (M) bit 9-27
shifter 9-26, 9-28
Service
request breakpoint flag (SRBK) D-74
Set (definition) 2-7
SFC 4-7
SGLR D-78
SHEN 5-38, D-6
Show cycle
enable (SHEN) 5-3, 5-38, D-6
operation 5-38
timing diagram A-16
Signal
characteristics 3-9
functions 3-11
Signature registers (RSIGHI/LO) 7-1
SIM 5-1
address map D-4
block diagram 5-2
bus operation 5-25
chip-selects 5-53
external bus interface (EBI) 5-18
features 3-1
functional blocks 5-1
halt monitor 5-14
interrupt arbitration 5-3
interrupts 5-49
low-power stop operation 5-18
module configuration register (SIMCR) D-6
parallel I/O ports 5-63
periodic interrupt timer 5-16
block diagram (with software watchdog) 5-15
register access 5-3
registers
chip-select
base address
register boot ROM (CSBARBT) D-17
registers (CSBAR) 5-56, 5-57, D-17
option
register boot ROM (CSORBT) D-18
registers (CSOR) 5-56, 5-58, D-18
pin assignment registers (CSPAR) 5-56,
D-15
clock synthesizer control register (SYNCR) D-7
distributed register (DREG) D-21
master shift register A/B (TSTMSRA/B) D-20
module configuration register (SIMCR) 5-2
periodic interrupt
control register (PICR) D-13
timer register (PITR) 5-16, D-13
port C data register (PORTC) 5-59, D-14
port E
data direction register (DDRE) 5-63, D-9
data register (PORTE) 5-63, D-9
pin assignment register (PEPAR) 5-63,
D-10
port F
data direction register (DDRF) 5-63, D-11
data register (PORTF) 5-63, D-10
pin assignment register (PFPAR) 5-63,
D-11
reset status register (RSR) D-8
software service register (SWSR) D-14
system
integration
test register - ECLK (SIMTRE) D-9
test register (SIMTR) D-7
protection control register (SYPCR) D-12
test
module
repetition count (TSTRC) D-21
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-14
shift count register (TSTSC) D-21
submodule control register (CREG) D-21
reset 5-39
state of pins 5-45
software watchdog 5-14
block diagram (with PIT) 5-14
spurious interrupt monitor 5-14
system
clock 5-3
block diagram 5-4
synthesizer operation 5-5
configuration 5-2
protection 5-12
SIM Reference Manual
5-53
SIMCR 5-2, 9-2, 12-1, D-6
SIMTR D-7
SIMTRE D-9
SIZ 5-21, 5-24, 5-39
Size signals (SIZ) 5-21
encoding 5-21
Slave select signal (SS) 9-21
SLOCK D-8
SM 11-9
SMB 10-1
SOF 13-9
Soft reset (SOFTRST) D-83
SOFTRST 13-11, D-83
Software
breakpoints 5-30
service register (SWSR) D-14
watchdog 5-14
block diagram 5-15
clock rate 5-14
enable (SWE) D-12
enable (SWE) bit 5-14
prescale (SWP) D-12
prescale (SWP) bit 5-14
ratio of SWP and SWT bits 5-15
reset (SW) D-9
timeout period calculation 5-15
timing field (SWT) 5-14, D-12
SPACE (address space select) 5-59, D-19
SPBR D-49
SPCR0 D-47
SPCR1 D-49
SPCR2 D-50
SPCR3 D-51
SPE 9-7, D-49
SPI 4-25
finished interrupt enable (SPIFIE) D-50
SPIF D-52
SPIFIE D-50
SPSR D-51
SPWM 11-7
SR 4-6
SRAM
address map D-21
array address mapping 6-1
features 3-1
normal access 6-2
registers
array base address register
high (RAMBAH) 6-1, D-22
low (RAMBAL) 6-1, D-22
module configuration register (RAMMCR) 6-1,
D-21
test register (RAMTST) 6-1, D-22
reset 6-3
standby and low-power stop operation 6-2
SRBK D-74
SRR 13-6
SS 9-21
SSE1 D-31
SSE2 D-32
SSP 4-10
Stack pointer (SP) 4-1
Standard
message format 13-1
frames 13-4
nonreturn to zero (NRZ) 9-2
Standby RAM module w/ TPU emulation (TPURAM).
See
TPURAM 12-1
Start
bit (beginning of data frame) 9-27
-of-frame (SOF) symbol 13-9
State machine 8-23, 9-30
Stepper motor (SM) 11-9
STEXT 5-11, D-8
STF D-72
STOP 13-17, D-21, D-23, D-27, D-40, D-55, D-71,
D-80, D-82
Stop
acknowledge (STOPACK) D-84
clocks to TCRs (CLKS) D-73
enable (STOP) bit
BIUSM 10-3
QADC 8-6
QSM 9-2
SRAM 6-2
TouCAN 13-17
TPU 11-15
flag (STF) D-72
mode
external clock (STEXT) 5-11, D-8
SIM clock (STSIM) 5-11, D-8
SCI end of data frame bit 9-27
STOPACK D-84
STRB (address strobe/data strobe) bit 5-29, 5-59, D-19
STSIM 5-11, D-8
STUFFERR D-92
Submodule bus (SMB) 10-1
Subqueue 8-17
Substitute remote request (SRR) 13-6
Successive approximation register (SAR) 8-1, 8-16
Supervisor
/unrestricted data space (SUPV)
CPU32 D-3
QADC D-27
QSM D-40
SIM 5-3, D-7
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-15
TouCAN D-84
TPU D-72
stack pointer (SSP) 4-10
SUPV 5-3, 8-7, D-27, D-28, D-40, D-84
SW D-9
SWE 5-14, D-12
SWP 5-14, D-12
SWSR D-14
SWT 5-14, D-12
Symbols 2-1
Synchronized pulse width modulation (SPWM) 11-7
SYNCR D-7
Synthesizer lock flag (SLOCK) D-8
SYPCR D-12
SYS D-9
SYSRST (system reset) 5-40
System
clock 5-3
block diagram 5-4
output (CLKOUT) 5-25
sources 5-4
frequencies 5-9
integration
module.
See
SIM 5-1, D-4
test register - ECLK (SIMTRE) D-9
memory maps.
See
Memory maps 3-13
protection control register (SYPCR) D-12
reset (SYS) D-9
–T–
T D-3
T2CG 11-14, D-72
Table stepper motor (TSM) 11-10
TBB 10-1
TBL 4-15
TBRS1 D-56
TBRS2 D-56
TC 9-29, D-44
TCIE 9-29, D-43
TCR D-73
TCR1P 11-13, D-71
TCR2 clock/gate control (T2CG) D-72
TCR2P D-72
TDR 9-26
TDRE 9-28, D-44
TE D-43
Temporary register A (ATEMP) 4-21
Test
module
repetition count (TSTRC) D-21
shift count register (TSTSC) D-21
submodule
control register (CREG) D-21
reset (TST) D-9
Thermal characteristics A-2
Three-state control (TSC) 5-48
TICR 11-13, D-75
TIE 9-29, D-43
Time
base
bus driver for MCSM 10-9
buses (TBB) 10-1, 10-2
allocation 10-3
register bus select bits (TBRS1/0) D-56
processor unit.
See
TPU 11-1
quanta clock 13-8
stamp 13-4, 13-10
TIMER D-89
Timer
count register
1 prescaler control (TCR1P) D-71
2 prescaler control (TCR2P) D-72
synchronize mode (TSYNC) D-87
TOR1 D-34
TOR2 D-35
TouCAN
address
map D-80
space 13-2
bit timing configuration 13-8
operation 13-9
block diagram 13-1
disable (FRZACK) D-83
external pins 13-2
features 3-3
function 13-1
initialization sequence 13-11
interrupts 13-18
message buffer address map D-82
not ready (NOTRDY) D-83
operation 13-3
receive process 13-13
registers
control register 0 (CANCTRL0) D-85
control register 1 (CTRL1) 13-8
control register 1(CANCTRL1) D-87
control register 2 (CANCTRL2) D-88
control register 2 (CTRL2) 13-8
error and status register (ESTAT) D-91
free running timer register (TIMER) D-89
interrupt
configuration register (CANICR) D-85
flag register (IFLAG) D-93
mask register (IMASK) D-93
module configuration register (CANMCR) D-82
receive
buffer 14 mask registers (RX14MSKHI/LO)
D-90
buffer 15 mask registers (RX15MSKHI/LO)
D-90
global mask registers (RXGMSKLO/HI
D-90
RX/TX error counter registers (RXECTR/TXEC-
TR) D-94
test configuration register (CANTCR) D-85
special operating modes 13-16
auto power save mode 13-18
debug mode 13-16
low-power stop mode 13-17
transmit process 13-12
MOTOROLA MC68336/376
Index16 USER’S MANUAL
TPU
A mask functions 11-6
discrete input/output (DIO) 11-6
input capture/input transition counter (ITC) 11-6
output compare (OC) 11-7
period
/pw accumulator (PPWA) 11-9
measurement
add transition detect (PMA) 11-7
missing transition detect (PMM) 11-8
position-synch pulse generator (PSP) 11-8
pulse width modulation (PWM) 11-7
quadrature decode (QDEC) 11-10
stepper motor (SM) 11-9
synch pw modulation (SPWM) 11-7
address map D-70, D-71
block diagram 11-1
components 11-2
features 3-2
FREEZE flag (TPUF) D-75
function library 11-5
G mask functions 11-10
brushless motor commutation (COMM) 11-12
fast quadrature decode (FQD) 11-12
frequency measurement (FQM) 11-12
hall effect decode (HALLD) 11-13
multichannel pulse width modulation (PCPWM)
11-11
new input capture/transition counter (NITC)
11-11
programmable time accumulator (PTA) 11-11
queued output match (QOM) 11-11
table stepper motor (TSM) 11-10
universal asynchronous receiver/transmitter
(UART) 11-12
host interface 11-3
interrupts 11-5
microengine 11-3
operation 11-3
coherency 11-4
emulation support 11-5
event timing 11-3
interchannel communication 11-4
programmable channel service priority 11-4
overview 11-1
parameter RAM 11-3, D-78
address map D-79
registers
channel
function select registers (CFSR) D-75
interrupt
enable register (CIER) 11-5, D-75
status register (CISR) 11-5, D-78
priority registers (CPR) D-77
decoded channel number register (DCNR) D-78
development
support control register (DSCR) D-73
support status register (DSSR) D-74
host
sequence registers (HSQR) D-76
service request registers (HSSR) D-77
link register (LR) D-78
module configuration register (TPUMCR) D-71
service grant latch register (SGLR) D-78
test configuration register (TCR) D-73
TPU interrupt configuration register (TICR) D-75
scheduler 11-3
time
bases 11-2
timer channels 11-2
timing (electricals) A-24
TPU Reference Manual
11-3, 11-16, 11-17
TPUF D-75
TPUMCR 11-13, D-71
TPURAM
address map D-79
array
address mapping 12-1
base address (ADDR) D-80
space (RASP) D-80
features 3-2
general 12-1
operation
normal 12-2
standby 12-2
privilege level 12-2
register block 12-1
registers
base address and status register (TRAMBAR)
D-80
module configuration register (TRAMMCR) D-80
test register (TRAMTST) D-80
reset 12-3
TPU microcode emulation 12-3
tPWMAX 10-18
tPWMIN 10-18
TR D-53
Trace
enable field (T) D-3
on instruction execution 4-19
TRAMBAR 12-1, D-80
TRAMMCR 12-1, D-80
TRAMTST 12-1, D-80
Transfer
length options 9-18
time 8-13
Transistion-sensitivity 5-50
Transmission
complete
(TC) flag 9-29
interrupt enable (TCIE) 9-29
Transmit
/receive status (TX/RX) D-92
bit error (BITERR) D-91
complete
bit (TC) D-44
interrupt enable (TCIE) D-43
data
(TXD) pin 9-26
register empty (TDRE) flag 9-28, D-44
error status flag (TXWARN) D-92
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-17
interrupt enable (TIE) 9-29, D-43
pin configuration control (TXMODE) D-86
RAM 9-8
Transmitter enable (TE) 9-28, D-43
Trigger event 8-29
TSC 5-48
TSM 11-10
TSR 8-6
TST D-9
TSTME 3-8, 3-10, 3-12
TSTMSR D-20
TSTRC D-21
TSTSC D-21
TSYNC D-87
TX
Length 13-4
TX/RX D-92
TXD 9-26
TXECTR D-94
TXMODE D-86
TXWARN D-92
Typical ratings (electrical) A-2
–U–
UART 11-12
Unimplemented instruction emulation 4-19
Universal asynchronous receiver/transmitter (UART)
11-12
User stack pointer (USP) 4-10
Using the TPU Function Library and TPU Emulation
Mode
11-5
USP 4-10
–V–
V (overflow) flag 4-6, D-4
Variable pulse width signal generator (prescaler) 8-25
VBR 4-7, 4-16
VDD 3-8, 5-47, 6-1, 8-6, 12-1
ramp time 5-47
VDDA 3-8, 8-5
VDDA/2 8-15
VDDSYN 3-8, 5-47
VECT D-56
Vector base register (VBR) 3-13, 4-7, 4-16, 5-49
VIH 8-8
VIL 8-8
Virtual memory 4-9
Voltage
controlled oscillator (VCO)
frequency ramp time 5-47
reference pins 8-5
VPP C-2
VRH 3-8, 8-5, 8-15, D-37
VRL 3-8, 8-5, 8-15, D-37
VSS 3-8, 8-6, 12-2
VSSA 3-8, 8-5
VSTBY 3-8, 6-2, 12-1, 12-2
–W–
W bit D-8
WAIT 7-3, D-24
Wait states (WAIT) D-24
WAKE 9-31, D-43
Wake interrupt (WAKEINT) D-93
WAKEINT 13-17, D-93
WAKEMSK 13-17, D-83
Wakeup
address mark (WAKE) 9-31, D-43
functions 9-2
interrupt mask (WAKEMSK) D-83
Wired-OR
mode
for QSPI pins (WOMQ) D-48
for SCI pins (WOMS) 9-28, D-43
mode (WOR) D-62
WOMQ D-48
WOMS 9-28, D-43
WOR D-62
Wrap
enable (WREN) D-50
to (WRTO) D-50
Wraparound mode 9-7
master 9-20
slave 9-22
WREN D-50
Write cycle 5-27
flowchart 5-28
timing diagram A-11
WRTO D-50
–X–
X
(extend) flag 4-6, D-4
bit in SYNCR D-8
XTRST (external reset) 5-40
–Y–
Y field D-8
–Z–
Z (zero) flag 4-6, D-4
MC68336/376 INDEX MOTOROLA
USER’S MANUAL Rev. 15 Oct 2000 Index-18
