DS-11802 FOUR QUADRANT MULTIPLYING SIN/COS DAC, MICROPROCESSOR COMPATIBLE, 16-BIT HYBRID FEATURES DESCRIPTION The DS-11802 is a small size, high accuracy, 16-bit digital-to-sine/cosine converter. Available in accuracies up to 1 arc minute, the DS-11802 is contained in a 28-pin DDIP and requires +15 Vdc and -15 Vdc power supplies. The reference input is buffered through an op-amp to minimize loading on the input signal and can accept up to 10 V peak. The DS-11802 is pin programmable for gains of 0.5, 1.0, and 2.0. Two registers for the input of the 16-bit (CMOS/TTL) natural binary angle data allow for compatibility with an 8-bit or 16-bit data bus. Internally, the DS-11802 has a multiplying digital-to-sin/cos converter consisting of two function generators and a quadrant select network. Quadrant information is available from the two most significant bits (MSBs). The two function generators use the remaining angular data along with the buffered reference voltage. Similar to a multiplying DAC (digital- * * * * to-analog converter), the DS-11802 uses high-accuracy resistive ladder networks and solid-state switching to control the attenuation of the reference voltage. The output buffer amplifiers allow for up to 2 mA output drive. APPLICATIONS 28-Pin Ceramic DDIP Package 1 Arc Minute Accuracy 0.03% Radius Accuracy Microprocessor Compatible 8- and 16-Bit * Double-Buffered Inputs * Pin-Programmable Gain - Due to the high accuracy, high reliability, small size, low power consumption and MIL-PRF-38534 processing available, the DS-11802 is suitable for industrial and military ground or avionic applications. Possible applications include digital remote positioning, resolver angle simulation, flight trainers, flight instrumentation, radar and navigational systems, and PPI displays including moving target indicators. Other applications are synchro/resolver system development and testing, and wraparound test of synchro/resolver-to-digital converters. 0.5, 1.0 or 2.0 * Buffered Reference Input * DC-Coupled Reference and Outputs * Requires Only 15 V Power Supplies * TTL and CMOS Compatible * Pin-for-Pin Replacement for Natel's HDSC2306 +VS -VS 27 26 HBE 9 (MSB) B1 1 CK B2 2 B3 3 B4 4 Q1 8-BIT INPUT REGISTER B5 5 BIT 1 (MSB) D B7 7 B8 8 B9 11 B10 12 B11 13 B12 14 B13 15 INPUT BUFFERS B6 6 16-BIT HOLDING REGISTER B14 16 B15 17 28 SIN BUFFER AMPLIFIERS 21 COS 8-BIT INPUT REGISTER D Q16 (LSB) B16 18 16-BIT HIGH ACCURACY MULTIPLYING DIGITAL TO SIN / COS CONVERTER CK CK BIT16 (LSB) LBE 10 LDC 19 REFERENCE CONDITIONER 25 GND 20 VIN 22 23 TP1 GC1 24 GC2 FIGURE 1. DS-11802 BLOCK DIAGRAM (c) 1996, 1999 Data Device Corporation TABLE 1. DS-11802 SPECIFICATIONS PARAMETER VALUE REMARKS DIGITAL ANGULAR Resolution 16 Bits Bit 1 = MSB, Bit 16 = LSB Accuracy 4 arc-minutes Accuracy applies over 2 arc-minutes operating temperature 1 arc-minutes range. TABLE 1. DS-11802 SPECIFICATIONS (CONTINUED) PARAMETER VALUE REMARKS REGISTER CONTROLS (Continued) 200 sec min Before data transfer. Data Set-up Time Data Hold Time Before input data 200 sec min changes. ANALOG INPUT (VIN) Voltage Frequency Range Input Resistance POWER SUPPLIES Supply Voltages (Vs) Supply Current Supply Rejection 15 V dc 10% 25 mA max 80 db typ TEMPEATURE RANGES Operating Case -3XX and -8XX -5XX and -2XX -1XX and -4XX Storage 0C to +70C -40C to +85C -55C to +125C -65C to +135C 0 to 10 Vp ac or dc dc to 1000 Hz 1 M min Op amp buffer ANALOG OUTPUTS SIN COS Converter Gain (K) K * Vin * SIN K * Vin * COS 0.5 0.2% 1.0 0.2% Radius Accuracy Output Current Output Impedance Zero Offset (dc) Offset Drift Output Settling Time 2.0 0.2% 0.1% 2 mA rms < 1 ohm 10 mV typical 25 mV max 25 V/C 30 sec max to accuracy of converter DIGITAL INPUTS Logic Voltage Levels Logic 0 Logic 1 Loading Input Current Data Bits (B1-B16) HBE, LBE, LDC REGISTER CONTROLS HBE (High Byte Enable) Weight For any digital step change. ABSOLUTE MAXIMUM RATINGS Reference Input: Power Supply Voltage (Vs): Digital Inputs: Logic 1 Logic 1 Logic 0 -Vs to +Vs 18 V dc -0.3 V dc to +6.5 V dc ANALOG OUTPUT GAIN CONTROL AND PHASING The DS-11802 is pin-programmable for gains of 0.5, 1.0 and 2.0. TABLE 2 details the programming of gain control pins 23 (GC1) and 24 (GC2). When both pins are left unconnected or open, the gain of the converter is 2.0. The output signal would be: 2 Vin sin and 2 Vin cos. When GC2 is connected to GND and GC1 is left open, the converter gain is 1.0. When GC1 is connected to GND and GC2 is left open, the converter gain is 0.5. When looking at the equivalent gain circuit (see FIGURE 2) the gain of the converter can be modified by adding a resistor between GC1 or GC2 and GND. 15 A typ, "active" For less than 16 bits, unused pins can be pull-down to gnd left unconnected. -15 A typ, "active" pull-up to internal Pins not used can be left unconnected. logic supply Logic 1 28 Pin Double DIP 0.6 x 1.4 x 0.2 in. (15 x 36 x 5) mm 0.5 oz (15 gm) max Op amp output. -0.3 V DC to 0.8 V DC 2.4 V DC to 5.5 V DC 0.1 TTL load CMOS transient protected. Logic 0 LDC (Load Converter) PHYSICAL CHARACTERISTICS Type Size No external logic voltages required. Logic 0 LBE (Low Byte Enable) 10 Vp AC or DC 10 Vp AC or DC Pin 23 connected to gnd. Pin 24 no connection. Pin 24 connected to gnd. Pin 23 no connection. Pin 23 and 24 floating. Guaranteed, but not tested. For 10 V pk output. 8 MSBs enter high byte input register. High byte register remains unaffected. GC1 (PIN 23) Gnd 8 LSBs enter low byte input register. Low byte register remains unaffected. TABLE 2. GAIN CONTROL PINS GC2 (PIN 24) Open GAIN (K) 0.5 Open Gnd 1.0 Open Open 2.0 Users are cautioned against using a large value resistor to modify the gain, as the temperature coefficient of the external resistor will not be matched with the TCR of the internal resistor. The internal gain resistors have an accuracy of 0.05%. Data from input registers transferred to holding register. Data in holding register remains unaffected. FIGURE 3 illustrates the output phasing between the reference voltage Vin and the analog output signals as a function of the digital angle and the converter gain K (0.5, 1.0, or 2.0). 2 DIGITAL INTERFACE DATA TRANSFER FROM AN 8-BIT DATA BUS The DS-11802 has double-buffered input registers which allow easy implementation of an interface with 8-bit or 16-bit data buses. The DS-11802 can also be set up for asynchronous data inputs. If the LBE, HBE and LDC input pins are left open, the internal pull-up circuitry will set these pins to a high state and the information at the data inputs (B1-B16) is continuously converted to sin and cos at the analog outputs. For applications requiring less than 16-bit resolution, the unused data bit pins can be left open. The data bits (B1-B16) are internally pulled-down to apply a logic "0" to unconnected data inputs. Applications with a 8-bit data bus require two-byte loading of the digital input (see FIGURE 4). FIGURE 5 shows the timing for two-byte data transfers. 1 TP1 22 2 3 VIN 20 21K INTERNAL REFERENCE DATA BUS 2.92K GC2 24 10 5 9 6 2.33K GC1 23 4 (MSB) 8.75K (LSB) 7 19 LBE LOAD LSBs HBE LOAD MSBs LDC LOAD CONVERTER 8 DS-11802 11 D7 D6 12 D5 13 D4 14 D3 15 D2 16 D1 17 D0 18 HBE LBE FIGURE 4. DATA TRANSFER FROM 8-BIT BUS FIGURE 2. REFERENCE CONDITIONER +V SIN MAX 8 LSBs TRANSFERRED TO INPUT REGISTERS DATA CHANGING DATA STEADY (MSBs) (LSBs) In Phase with Vin 0 90 180 270 360 DATA (DEGREES) DATA SET UP Data Hold 200 ns MIN -V MAX LBE COS SIN OUTPUT = K * Vin * (1+n) SIN HBE COS OUTPUT = K * Vin * (1+n) COS WHERE: LDC K IS THE GAIN OF THE CONVERTER. 8 MSBs TRANSFERRED TO INPUT REGISTERS PULSE WIDTH 800 ns MIN DATA HOLD 200ns MIN PULSE WIDTH 800 ns MIN 600ns MIN DATA TRANSFERRED TO HOLDING REGISTERS PULSE WIDTH n IS THE SCALE FACTOR VARIATION AS A FUNCTION OF DIGITAL ANGLE( 0.2%) FIGURE 3. OUTPUT PHASING FIGURE 5. TIMING FOR 8-BIT BUS TRANSFER 3 1. The LDC is low (logic 0) so that the contents of the holding register are latched and will remain unaffected by the changes on the input registers. DIGITAL-TO-RESOLVER/SYNCHRO CONVERTERS The output of the DS-11802 is a single-ended sin/cos. FIGURE 8 illustrates a schematic for a 4-Wire Digital-to-Resolver Converter (S1, S2, S3, and S4) using external power amplifiers and transformers. 2. When the LBE is set high (logic 1) the 8 LSBs (B9-B16) are transferred to the low byte. The LBE must remain high for a minimum of 800 nsec after the data is stable. The data should remain stable for 200 nsec after the LBE is set low (logic 0). FIGURE 9 illustrates a schematic for 3-Wire Digital-to-Synchro Converter (S1, S2, and S3) using an additional power stage and external transformers. 3. When the HBE is set high (logic 1) the 8 MSBs (B1-B8) are transferred to the low byte. The HBE must remain high for a minimum of 800 nsec after the data is stable. The data should remain stable for 200 nsec after the HBE is set low (logic 0). A benefit to the designs shown in FIGURES 8 and 9 is the ability to keep the converters near the digital data and control signals, and to mount the power amplifiers and transformers in a better thermal location. This would isolate heat dissipating circuits from high-accuracy computing circuits. 4. When the LDC is set high (logic 1) the data is transferred from the two input registers to the holding register. The LDC should be held high for 600 nsec minimum. Once the LDC is set low, the cycle can begin again. Note: LBE, HBE, and LDC are level-actuated functions. Refer to TABLE 3 for bit values. (MSB) TABLE 3. DIGITAL ANGLE INPUTS BIT 1 MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DEG/BIT 180.0 90.0 45.0 22.5 11.25 5.625 2.813 1.406 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 MIN/BIT 10800.0 5400.0 2700.0 1350.0 675.0 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 B1 1 B2 2 B3 3 B4 4 DS-11802 B5 5 B6 6 B7 7 10 9 B8 8 B9 11 B10 12 B11 B12 13 14 B13 15 B14 16 B15 17 19 LBE HBE LDC NOT CONNECTED OR LOAD DATA PULSE LOAD CONVERTER 18 B16 (LSB) FIGURE 6. DATA TRANSFER FROM 16-BIT BUS DATA TRANSFERRED TO INPUT REGISTERS Note: HBE enables the MSBs and LBE enables the LSBs. DATA CHANGING DATA DATA STEADY ALL 16 BITS 200 ns MIN 200 ns MIN DATA TRANSFER FROM A 16-BIT DATA BUS HBE LBE Applications interfacing with a 16-bit data bus require only single byte loading (see FIGURE 6). LBE and HBE are either unconnected or tied together and pulsed high to load data. 800 ns MIN DATA TRANSFERRED TO HOLDING REGISTERS As shown in the timing diagram (see FIGURE 7) 200 nsec after the data has been stable, the LDC is set high (logic 1) to transfer the data to the holding register. Since LDC is level actuated, it must remain high for the time specified (600 nsec). 600 ns MIN LDC FIGURE 7. TIMING FOR 16-BIT BUS TRANSFER 4 LOW FREQUENCY SINE WAVE OSCILLATOR POWER SUPPLY DECOUPLING The DS-11802 can be used to create a low frequency sine wave oscillator with very low distortion (see FIGURE 10). The output amplitude is determined by the amplitude of the dc reference input and the gain control pin configuration. When using a 16-bit counter and a square wave of 65,536 Hz (2N, where N = 16 bit resolution) the output will be at 1 Hz. Decoupling capacitors are recommended on the +Vs and -Vs. supplies. A 1 F tantalum capacitor in parallel with a 0.01 F ceramic capacitor should be mounted as close to the supply as possible. VIN 1:n RH 20 RL 28 SIN P.A. 1:N S3 S1 DS-11802 DIGITAL ANGLE 21 COS P.A. 1:N S2 S4 INTERFACE CONTROLS FIGURE 8. 4-WIRE DIGITAL-TO-RESOLVER CONVERTER 1:n RH VIN RL 20 28 SIN 1:N P.A. S1 S3 DS-11802 DIGITAL ANGLE 21 COS P.A. 1: 3 N 2 S2 INTERFACE CONTROLS FIGURE 9. 3-WIRE DIGITAL-TO-SYNCHRO CONVERTER SQUARE WAVE OSCILLATOR DC REFERENCE (Vref) REFERENCE INPUT K * Vref * SIN SINE WAVE OUTPUT 16-BIT COUNTER DIGITAL INPUT DS-11802 K * Vref * COS QUADRATURE OUTPUT FIGURE 10. LOW FREQUENCY SINEWAVE OSCILLATOR 5 TABLE 4. DS-11802 PINOUTS PIN FUNCTION PIN FUNCTION 1 B1 15 B13 2 B2 16 B14 3 B3 17 B15 4 B4 18 B16 5 B5 19 LDC 6 B6 20 VIN 7 B7 21 COS 8 B8 22 TP1 9 HBE 23 GC1 10 LBE 24 GC2 11 B9 25 GND 12 B10 26 -Vs 13 B11 27 +Vs 14 B12 28 SIN TOP VIEW .015 1.400 (35.56) .18 (4.57) 15 28 .600 .594 (15.1) 1 SIDE VIEW (15.2) 14 PIN #1 I.D. .010 .002 (.254) SIDE VIEW .050 TYP (1.25) .150 MIN (3.81) .020 (.51) .002 .002 .100 (2.54) TOLERANCES .XX = .02 ( .50) .XXX = .005 ( .25) NOTES: 1. CASE IS ELECTRICALLY FLOATING 2. PINS ARE ALLOY 42 WITH GOLD PLATED 60 INCH MIN OVER 100 INCH NICKEL 3. CASE & LID ARE 91% PURE ALUMINA CERAMIC 4. DIMENSIONS SHOWN IN INCHES AND (MM). .015 .050 (1.27) FIGURE 11. DS-11802 MECHANICAL OUTLINE 6 ORDERING INFORMATION DS-11802DX-XXXX Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test Blank = None of the Above Accuracy: 3 = 4 Minutes 4 = 2 Minutes 5 = 1 Minute Process Requirements*: 0 = Standard DDC Processing, no Burn-In (See table below.) 2 = B* 6 = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.) Temperature Grade/Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 8 = 0C to +70C with Variables Test Data Frequency Range: 4 = DC to 1 kHz * For availability of Fully Compliant MIL-PRF-38534 parts, please contact the DDC office nearest you. **Standard DDC Processing with burn-in and full temperature test -- see table below. STANDARD DDC PROCESSING MIL-STD-883 TEST METHOD(S) CONDITION(S) INSPECTION 2009, 2010, 2017, and 2032 -- SEAL 1014 A and C TEMPERATURE CYCLE 1010 C CONSTANT ACCELERATION 2001 A BURN-IN 1015, Table 1 -- 7 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7389 or 7413 Headquarters - Tel: (631) 567-5600 ext. 7389 or 7413, Fax: (631) 567-7358 Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988 Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com ILC DATA DEVICE CORPORATION REGISTERED TO ISO 9001 FILE NO. A5976 A-03/98-1M PRINTED IN THE U.S.A. 8