Data Sheet Rev. 1.03
www.infineon.com 1 2018-06-14
BTS7040-2EPA
1 Overview
Potential Applications
• Suitable for resistive, inductive and capacitive loads
• Replaces electromechanical relays, fuses and discrete circuits
• Driving capability suitable for 3.5 A loads and high inrush current loads
such as P27W + R5W lamps or LED equivalent
Figure 1 BTS7040-2EPA Application Diagram. Further information in Chapter 10
PROFET™+2 2x 40 mΩ
Smart High-Side Power Switch
Package PG-TSDSO-14-22
Marking 7040-2A
GPIO
GPIO
GPIO
GPIO
A/D IN
VSS
VDD
Microcontroller
IN0
IN1
DEN
DSEL
IS GND
OUT0
OUT1
VS
V
BAT
C
SENSE
D
Z1
R/L cable
R/L cable
R/L cable
C
OUT1
C
OUT0
R
IN
R
IN
R
DEN
R
DSEL
R
AD
R
IS_PROT
R
SENSE
R
GND
V
DD
R
PD
R
PD
C
VS
R
OL
T
1
D
Z2
App_2CH_LI_INTDIO_Cover.emf
Control
Protection
Diagnosis
T
T
Data Sheet 2 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Overview
Basic Features
• High-Side Switch with Diagnosis and Embedded Protection
• Part of PROFET™+2 Family
• ReverSave™ for low power dissipation in Reverse Polarity
• Switch ON capability while Inverse Current condition (InverseON)
• Green Product (RoHS compliant)
• Qualified in accordance with AEC Q100 grade 1
Protection Features
• Absolute and dynamic temperature limitation with controlled restart
• Overcurrent protection (tripping) with Intelligent Restart Control
• Undervoltage shutdown
• Overvoltage protection with external components
Diagnostic Features
• Proportional load current sense
• Open Load in ON and OFF state
• Short circuit to ground and battery
Description
The BTS7040-2EPA is a Smart High-Side Power Switch, providing protection functions and diagnosis. The
device is integrated in SMART7 technology.
Table 1 Product Summary
Parameter Symbol Values
Minimum Operating voltage (at switch ON) VS(OP) 4.1 V
Minimum Operating voltage (cranking) VS(UV) 3.1 V
Maximum Operating voltage VS28 V
Minimum Overvoltage protection (TJ = 25 °C) VDS(CLAMP)_25 35 V
Maximum current in Sleep mode (TJ ≤ 85 °C) IVS(SLEEP) 0.5 µA
Maximum operative current IGND(ACTIVE) 4 mA
Maximum ON-state resistance (TJ = 150 °C) RDS(ON)_150 36 mΩ
Nominal load current (TA = 85 °C) IL(NOM) 3.5 A
Typical current sense ratio at IL = IL(NOM) kILIS 1800
Data Sheet 3 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Block Diagram and Terms
2 Block Diagram and Terms
2.1 Block Diagram
Figure 2 Block Diagram of BTS7040-2EPA
IN0
ESD
Protection
+
Input Logic
IS
DEN
DSEL
IN1
Internal Power Supply
Block_PROFET2ch_REVON.emf
GND Circuitry
Supply Voltage
Monitoring
Overvoltage
Protection
Intelligent Restart
Control
SENSE Output
VS
GND
OUT1
OUT0
Internal Reverse
Polarity Protection
Channel 1
T
dr iver
logic
Gate Control
+
Chargepump
Load Current Sense
Overtemperat
ure Overvoltage
Clamping
Overcurrent
Protection
Output Voltage Limitation
Voltage Sensor
ReverSave
TM
InverseON
Channel 0
T
Driver
Logic
Gate Control
+
Chargepump
Overtemperature Overvoltage
Clamping
Overcurrent
Protection
Output Voltage Limitation
Voltage Sensor
ReverSave
TM
InverseON
Load Current Sense
Data Sheet 4 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Block Diagram and Terms
2.2 Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
Figure 3 Voltage and Current Convention
I
INn
I
DEN
I
IS
V
S
I
GND
I
Ln
I
DSEL
INn
DEN
DSEL
IS
GND
VS
OUTn
V
INn
V
DEN
V
DSEL
V
IS
V
OUTn
V
DSn
I
VS
Terms_PROFET.emf
V
SIS
Data Sheet 5 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 4 Pin Configuration
VS
GND OUT0
IN0
DEN
IS
DSEL
IN1
n.c.
OUT0
OUT0
n.c.
OUT1
OUT1
OUT1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PinOut_PROFET2ch.emf
expos ed pad (bo tto m)
Data Sheet 6 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Pin Configuration
3.2 Pin Definitions and Functions
Table 2 Pin Definition
Pin Symbol Function
EP VS
(exposed pad)
Supply Voltage
Battery voltage
1GND Ground
Signal ground
2, 6 INn Input Channel n
Digital signal to switch ON channel n (“high” active)
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
3DEN Diagnostic Enable
Digital signal to enable device diagnosis (“high” active) and to clear the
protection counter of channel selected with DSEL pin
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
4IS SENSE current output
Analog/digital signal for diagnosis
If not used: left open
5DSEL Diagnosis Selection
Digital signal to select one channel to perform ON and OFF state diagnosis
(“high” active)
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
7, 11 n.c. Not connected, internally not bonded
8-10, 12-
14
OUTn Output n
Protected high-side power output channel n1)
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected
together. PCB traces have to be designed to withstand the maximum current which can flow.
Data Sheet 7 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings - General
Table 3 Absolute Maximum Ratings1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply pins
Power Supply Voltage VS-0.3 – 28 V – P_4.1.0.1
Load Dump Voltage VBAT(LD) – – 35 V suppressed
Load Dump
acc. to
ISO16750-2
(2010).
Ri = 2 Ω
P_4.1.0.3
Supply Voltage for Short Circuit
Protection
VBAT(SC) 0–24VSetup acc. to
AEC-Q100-012
P_4.1.0.25
Reverse Polarity Voltage -VBAT(REV) ––16Vt ≤ 2 min
TA = +25 °C
Setup as
described in
Chapter 10
P_4.1.0.5
Current through GND Pin IGND -50 – 50 mA RGND according
to Chapter 10
P_4.1.0.9
Logic & control pins (Digital Input = DI)
DI = INn, DEN, DSEL
Current through DI Pin IDI -1 – 2 mA 2) P_4.1.0.14
Current through DI Pin
Reverse Battery Condition
IDI(REV) -1 – 10 mA 2)
t ≤ 2 min
P_4.1.0.36
IS pin
Voltage at IS Pin VIS -1.5 – VSVIIS = 10 μAP_4.1.0.16
Current through IS Pin IIS -25 – IIS(SAT),M
AX
mA – P_4.1.0.18
Temperatures
Junction Temperature TJ-40 – 150 °C – P_4.1.0.19
Storage Temperature TSTG -55 – 150 °C – P_4.1.0.20
ESD Susceptibility
Data Sheet 8 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
General Product Characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2 Absolute Maximum Ratings - Power Stages
4.2.1 Power Stage - 40 mΩ
ESD Susceptibility all Pins
(HBM)
VESD(HBM) -2 – 2 kV HBM3) P_4.1.0.21
ESD Susceptibility OUTn vs GND
and VS connected (HBM)
VESD(HBM)_OU
T
-4 – 4 kV HBM3) P_4.1.0.22
ESD Susceptibility all Pins
(CDM)
VESD(CDM) -500 – 500 V CDM4) P_4.1.0.23
ESD Susceptibility Corner Pins
(CDM)
(pins 1, 7, 8, 14)
VESD(CDM)_CR
N
-750 – 750 V CDM4) P_4.1.0.24
1) Not subject to production test - specified by design.
2) Maximum VDI to be considered for Latch-Up tests: 5.5 V.
3) ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002.
4) ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011.
Table 4 Absolute Maximum Ratings1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Maximum Energy Dissipation
Single Pulse
EAS ––36mJIL = 2*IL(NOM)
TJ(0) = 150 °C
VS = 28 V
P_4.2.6.1
Table 3 Absolute Maximum Ratings1) (continued)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 9 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
General Product Characteristics
4.3 Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
tables.
Maximum Energy Dissipation
Repetitive Pulse
EAR ––13mJIL = IL(NOM)
TJ(0) = 85 °C
VS = 13.5 V
1M cycles
P_4.2.6.2
Load Current |IL|––IL(OVL),M
AX
A– P_4.2.6.3
1) Not subject to production test - specified by design.
Table 5 Functional Range - Supply Voltage and Temperature1)
1) Not subject to production test - specified by design.
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply Voltage Range for
Normal Operation
VS(NOR) 6 13.5 18 V – P_4.3.0.1
Lower Extended Supply
Voltage Range for Operation
VS(EXT,LOW) 3.1 – 6 V 2)3)
(parameter
deviations possible)
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN =3.1V. In case of VS voltage increasing: VS(EXT,LOW),MIN =4.1V.
P_4.3.0.2
Upper Extended Supply
Voltage Range for Operation
VS(EXT,UP) 18 – 28 V 3)
(parameter
deviations possible)
3) Protection functions still operative.
P_4.3.0.3
Junction Temperature TJ-40 – 150 °C – P_4.3.0.5
Table 4 Absolute Maximum Ratings1) (continued)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 10 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
General Product Characteristics
4.4 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
4.4.1 PCB Setup
Figure 5 1s0p PCB Cross Section
Figure 6 2s2p PCB Cross Section
Table 6 Thermal Resistance1)
1) Not subject to production test - specified by design.
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Thermal Characterization
Parameter Junction-Top
ΨJTOP –2.44.1K/W
2)
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was
simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable
a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C,
PDISSIPATION = 1 W.
P_4.4.0.1
Thermal Resistance
Junction-to-Case
RthJC –1.62.7K/W
2)
simulated at
exposed pad
P_4.4.0.2
Thermal Resistance
Junction-to-Ambient
RthJA – 31.8 – K/W 2) P_4.4.0.3
70 µm modeled (traces, cooling area)
1,5 mm
70 µm, 5% metalization*
PCB_Zth_1s0p.emf
*: means percentual Cu metalization on each layer
70 µm modeled (traces)
35 µm, 90% metalization*
1,5 mm
70 µm, 5% metalization*
PCB_Zth_2s2p.emf
35 µm, 90% metalization*
*: means percentual Cu metalization on each layer
Data Sheet 11 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
General Product Characteristics
Figure 7 PCB setup for thermal simulations
Figure 8 Thermal vias on PCB for 2s2p PCB setup
4.4.2 Thermal Impedance
PCB_sim _setup_TSDSO 14.emf
PCB 1s0p + 600 mm² cooling PCB 2s2p / 1s0p footprint
PCB_ 2s2p_vi as_TSDS O14.emf
Data Sheet 12 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
General Product Characteristics
Figure 9 Typical Thermal Impedance. PCB setup according Chapter 4.4.1
Figure 10 Thermal Resistance on 1s0p PCB with various cooling surfaces
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZthJA (K/W)
TA= 105°C
Time (s)
BTS7040-2EPx
2s2p
1s0p - 600 mm
1s0p - 300 mm
1s0p - footprint
30
40
50
60
70
80
90
100
110
120
130
0 100 200 300 400 500 600
RthJA (K/W)
Cooling area (mm2)
BTS7040-EPx
1s0p - Ta = 105°C
Data Sheet 13 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Logic Pins
5 Logic Pins
The device has 4 digital pins for direct control.
5.1 Input Pins (INn)
The input pins IN0, IN1 activate the corresponding output channel. The input circuitry is compatible with 3.3V
and 5V microcontroller. The electrical equivalent of the input circuitry is shown in Figure 11. In case the pin is
not used, it must be connected with a 10 kΩ resistor either to GND pin or to module ground.
Figure 11 Input circuitry
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always
higher than the voltage needed to ensure a “low” state.
Figure 12 Input Threshold voltages and hysteresis
GND
IN
I
GND
I
DI
V
DI
Input_IN_INTDIO.emf
VS
V
S(CLAMP)
R
GND
I
DI
ESD
V
DI(CLAMP)
Input_VDITH_2.emf
V
DI(TH ),MAX
V
DI(HYS)
t
V
DI
V
DI(TH ),MIN
Internal channel
activation signal t
0 x 1 x 0
V
DI(TH)
Data Sheet 14 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Logic Pins
5.2 Diagnosis Pin
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is
set to “high”, the diagnosis is enabled (see Chapter 9.2 for more details). When it is set to “low”, the diagnosis
is disabled (IS pin is set to high impedance).
The Diagnosis Selection (DSEL) pin selects the channel where diagnosis is performed (see Chapter 9.1.1).
The transition from “high” to “low” of DEN pin clears the protection latch of the channel selected with DSEL
pin depending on the logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal
structure of diagnosis pins is the same as the one of input pins. See Figure 11 for more details.
Data Sheet 15 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Logic Pins
5.3 Electrical Characteristics Logic Pins
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Digital Input (DI) pins = IN, DEN, DSEL
Table 7 Electrical Characteristics: Logic Pins - General
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Digital Input Voltage
Threshold
VDI(TH) 0.8 1.3 2 V See Figure 11 and
Figure 12
P_5.4.0.1
Digital Input Clamping
Voltage
VDI(CLAMP1) –7–V
1)
IDI = 1 mA
See Figure 11 and
Figure 12
1) Not subject to production test - specified by design.
P_5.4.0.2
Digital Input Clamping
Voltage
VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA
See Figure 11 and
Figure 12
P_5.4.0.3
Digital Input Hysteresis VDI(HYS) –0.25–V
1)
See Figure 11 and
Figure 12
P_5.4.0.4
Digital Input Current
(“high”)
IDI(H) 21025µAVDI = 2 V
See Figure 11 and
Figure 12
P_5.4.0.5
Digital Input Current (“low”) IDI(L) 21025µAVDI = 0.8 V
See Figure 11 and
Figure 12
P_5.4.0.6
Data Sheet 16 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Supply
6 Power Supply
The BTS7040-2EPA is supplied by VS, which is used for the internal logic as well as supply for the power output
stages. VS has an undervoltage detection circuit, which prevents the activation of the power output stages and
diagnosis in case the applied voltage is below the undervoltage threshold.
6.1 Operation Modes
BTS7040-2EPA has the following operation modes:
•Sleep mode
•Active mode
•Stand-by mode
The transition between operation modes is determined according to these variables:
• Logic level at INn pins
• Logic level at DEN pin
The state diagram including the possible transitions is shown in Figure 13. The behavior of BTS7040-2EPA as
well as some parameters may change in dependence from the operation mode of the device. Furthermore,
due to the undervoltage detection circuitry which monitors VS supply voltage, some changes within the same
operation mode can be seen accordingly.
There are three parameters describing each operation mode of BTS7040-2EPA:
• Status of the output channels
• Status of the diagnosis
• Current consumption at VS pin (measured by IVS in Sleep mode, IGND in all other operative modes)
Table 8 shows the correlation between operation modes, VS supply voltage, and the state of the most
important functions (channel status, diagnosis).
Figure 13 Operation Mode State Diagram
PowerSupply_OpMode_PROFET.emf
Sleep
Active
IN = „high“
IN = „low“ &
DEN = „high“
Stand-by
IN = „low“
& DEN = „low“
Power-up
IN = „low“
& DEN = „high“
IN = „low“
& DEN = „low“
V
S
> V
S(OP)
Unsupplied
IN = „high“
DEN = „high“
DEN = „low“
Data Sheet 17 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Supply
6.1.1 Unsupplied
In this state, the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the
undervoltage threshold.
6.1.2 Power-up
The Power-up condition is entered when the supply voltage (VS) is applied to the device. The supply is rising
until it is above the undervoltage threshold VS(OP) therefore the internal Power-On signals are set.
6.1.3 Sleep mode
The device is in Sleep mode when all Digital Input pins (INn, DEN, DSEL) are set to “low”. When BTS7040-2EPA
is in Sleep mode, all outputs are OFF. The current consumption is minimum (see parameter IVS(SLEEP)). No
Overtemperature or Overload protection mechanism is active when the device is in Sleep mode. The device
can go in Sleep mode only if the protection is not active (counter = 0, see Chapter 8.3.1 for further details).
6.1.4 Stand-by mode
The device is in Stand-by mode as long as DEN pin is set to “high” while input pins are set to “low”. All channels
are OFF therefore only Open Load in OFF diagnosis is possible. Depending on the load condition, either a fault
current IIS(FAULT) or an Open Load in OFF current IIS(OLOFF) may be present at IS pin. In such situation, the current
consumption of the device is increased.
6.1.5 Active mode
Active mode is the normal operation mode of BTS7040-2EPA. The device enters Active mode as soon as one IN
pin is set to “high”. Device current consumption is specified with IGND(ACTIVE) (measured at GND pin because the
current at VS pin includes the load current). Overload, Overtemperature and Overvoltage protections are
active. Diagnosis is available.
6.2 Undervoltage on VS
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active mode)
and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the
output channels.
As soon as the supply voltage VS is above the operative threshold VS(OP), the channels having the corresponding
input pin set to “high” are switched ON again. The restart is delayed with a time tDELAY(UV) which protects the
device in case the undervoltage condition is caused by a short circuit event (according to AEC-Q100-012), as
shown in Figure 14.
Table 8 Device function in relation to operation modes and VS voltage
Operative Mode Function VS in undervoltage VS not in undervoltage
Sleep Channels OFF OFF
Diagnosis OFF OFF
Active Channels OFF available
Diagnosis OFF available in OFF and ON states
Stand-by Channels OFF OFF
Diagnosis OFF available in OFF state
Data Sheet 18 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Supply
If the device is in Sleep mode and one input is set to “high”, the corresponding channel is switched ON if
VS>VS(OP) without waiting for tDELAY(UV).
Figure 14 VS undervoltage behavior
PowerSupply_UVRVS.emf
t
VS(OP)
VS(UV)
VS(HYS)
t
VOUT
VS
tDELAY(UV)
Channel
activation signal
t
Data Sheet 19 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Supply
6.3 Electrical Characteristics Power Supply
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
6.4 Electrical Characteristics Power Supply - Product Specific
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
6.4.1 BTS7040-2EPA
Table 9 Electrical Characteristics: Power Supply - General
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
VS pin
Power Supply Undervoltage
Shutdown
VS(UV) 1.8 2.3 3.1 V VS decreasing
IN = “high”
From VDS ≤ 0.5 V to
VDS =VS
See Figure 14
P_6.4.0.1
Power Supply Minimum
Operating Voltage
VS(OP) 2.0 3.0 4.1 V VS increasing
IN = “high”
From VDS = VS to
VDS ≤0.5 V
See Figure 14
P_6.4.0.3
Power Supply Undervoltage
Shutdown Hysteresis
VS(HYS) –0.7–V
1)
VS(OP) - VS(UV)
See Figure 14
1) Not subject to production test - specified by design.
P_6.4.0.6
Power Supply Undervoltage
Recovery Time
tDELAY(UV) 2.5 5 7.5 ms dVS/dt≤0.5 V/µs
VS≥-1 V
See Figure 14
P_6.4.0.7
Breakdown Voltage
between GND and VS Pins in
Reverse Battery
-VS(REV) 16 – 30 V 1)
IGND(REV) = 7 mA
TJ = 150 °C
P_6.4.0.9
Data Sheet 20 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Supply
Table 10 Electrical Characteristics: Power Supply BTS7040-2EPA
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Supply Current
Consumption in Sleep Mode
with Loads at TJ≤85 °C
IVS(SLEEP)_85 –0.030.5µA
1)
VS = 18 V
VOUT = 0 V
IN = DEN = “low”
TJ ≤ 85 °C
1) Not subject to production test - specified by design.
P_6.5.6.1
Power Supply Current
Consumption in Sleep Mode
with Loads at TJ= 150 °C
IVS(SLEEP)_150 –3.514µAVS = 18 V
VOUT = 0 V
IN = DEN = “low”
TJ = 150 °C
P_6.5.6.2
Operating Current in Active
Mode (all Channels ON)
IGND(ACTIVE) –34mAVS = 18 V
IN = DEN = “high”
P_6.5.6.3
Operating Current in Stand-
by Mode
IGND(STBY) –1.21.8mAVS = 18 V
IN = “low”
DEN = “high”
P_6.5.6.5
Data Sheet 21 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
7 Power Stages
The high-side power stages are built using a N-channel vertical Power MOSFET with charge pump.
7.1 Output ON-State Resistance
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 15 shows the variation of
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured
at TJ = 150 °C.
Figure 15 RDS(ON) variation factor
The behavior in Reverse Polarity is described in Chapter 8.4.1.
7.2 Switching loads
7.2.1 Switching Resistive Loads
When switching resistive loads, the switching times and slew rates shown in Figure 16 can be considered. The
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF.
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
-40-30-20-100 102030405060708090100110120130140150160
RDS(ON) variation factor
Junction Temperature (°C)
RDS(ON) variation over TJ
Typical
Reference value:
"2" = R
DS(ON),MAX
@ 150 °C
Data Sheet 22 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
Figure 16 Switching a Resistive Load
7.2.2 Switching Inductive Loads
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative
output voltage so that VDS = VDS(CLAMP). Figure 17 shows a concept drawing of the implementation. The
clamping structure protects the device in all operation modes listed in Chapter 6.1.
Figure 17 Output Clamp concept
IN
t
V
OUT
V
IN(TH)
(dV/dt)
ON
V
IN(HYS)
P
DMOS
t
t
Pow er St age _Swi tch Res. emf
E
ON
E
OFF
t
ON
t
ON(DELAY)
t
OFF(DELAY)
-(dV/dt)
OFF
t
OFF
10% of V
S
90% of V
S
70% of V
S
30% of V
S
30% of V
S
70% of V
S
PowerStage_Clamp_INTDIO.emf
High-side
Channel
V
S
L,
R
L
V
OU Tn
I
L
V
DS(CLAMP)
I
L
VS
OUTn
V
DS
GND
V
S(CLAMP)
IS
V
SIS(CLAMP)
R
SENSE
R
GND
Data Sheet 23 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
During demagnetization of inductive loads, energy has to be dissipated in BTS7040-2EPA. The energy can be
calculated with Equation (7.1):
(7.1)
The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design
of the component.
7.2.3 Output Voltage Limitation
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while
the channel is diagnosed (DEN pin set to “high”, channel selected with DSEL pins - see Figure 18) bringing VDS
equal or lower than VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance
so that VDS = VDS(SLC) even for very small output currents. The VDS increase allows the current sensing circuitry
to work more efficiently, providing better kILIS accuracy for output current in the low range.
Figure 18 Output Voltage Limitation activation during diagnosis
7.3 Advanced Switching Characteristics
7.3.1 Inverse Current behavior
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 19). This condition is known
as “Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses
therefore an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due
to Overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output
stage is comparable to normal operation in RDS(ON).
During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV). If one channel
has inverse current applied, the neighbor channel is not influenced, meaning that switching ON and OFF
timings, protection (Overcurrent, Overtemperature) and current sensing (kILIS) are still within specified limits.
EV
DS CLAMP()
VSVDS CLAMP()
–
RL
--------------------------------------------1RLI⋅L
VSVDS CLAMP()
–
--------------------------------------------
–
⎝⎠
⎛⎞
IL
+ln⋅L
RL
------
⋅⋅=
IN
I
L
t
t
PowerStage_GBR_diag.emf
t
DEN
t
sIS(ON)
t
sIS(OFF)
t
V
DS
V
DS(SLC)
V
S
Data Sheet 24 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as IINV < IL(INV)
(see Figure 20).
Figure 19 Inverse Current Circuitry
Figure 20 InverseON - Channel behavior in case of applied Inverse Current
OUT
V
S
V
BAT
I
INV
INV
Comp.
V
INV
= V
OUT
> V
S
Gate
Driver
Device
Logic
GND
PowerStage_InvCurr_INTDIO.emf
R
GND
OFF
OFF
CASE 2 : Switch is OFF
IN
t
I
L
t
DMOS state
t
INVERSE
NORMALNORMAL
ON
INVERSE
NORMAL
I
L
t
DMOS state
t
ON
CASE 1 : Switch is ON
IN
t
NORMAL
OFF
ON
CASE 4 : Switch OFF into Inverse Current
IN
t
I
L
t
DMOS state
t
INVERSE
NORMALNORMAL
ON
INVERSE
NORMAL
I
L
t
DMOS state
t
OFF
CASE 3 : Switch ON into Inverse Current
IN
t
NORMAL
OFF
ON
ON
OFF
PowerStage_InvCurr_INVON.emf
Data Sheet 25 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
Note: No protection mechanism like Overtemperature or Overload protection is active during applied
Inverse Currents.
7.3.2 Switching Channels in Parallel
In case of appearance of a short circuit with connected in parallel to drive a single load, it may happen that the
two channels switch OFF asynchronously, therefore bringing an additional thermal stress to the channel that
switches OFF last. For this reason it is not recommended to use the device with channels in parallel.
7.3.3 Cross Current robustness with H-Bridge configuration
When BTS7040-2EPA is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-side
switch as shown in Figure 21), the maximum slew rate applied to the output by the low-side switch must be
lower than | dVOUT / dt |.
Figure 21 High-Side switch used in Bridge configuration
IN0 IN1
OUT0 OUT1
VS
PowerStage_PassiveSl ew_PROFET.emf
TT
V
BAT
R/L cable
M
ON (DC) OFF
ON (PWM)
OFF
Current through Motor Cross
Current
| dV
OUT
/ dt |
Data Sheet 26 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
7.4 Electrical Characteristics Power Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
7.4.1 Electrical Characteristics Power Stages - PROFET™
Table 11 Electrical Characteristics: Power Stages - General
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Voltages
Drain to Source Clamping
Voltage at TJ = -40 °C
VDS(CLAMP)_-40 33 36.5 42 V IL = 5 mA
TJ = -40°C
See Figure 17
P_7.4.0.1
Drain to Source Clamping
Voltage at TJ ≥ 25 °C
VDS(CLAMP)_25 35 38 44 V 1)
IL = 5 mA
TJ ≥ 25°C
See Figure 17
1) Tested at TJ = 150°C.
P_7.4.0.2
Table 12 Electrical Characteristics: Power Stages - PROFET™
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Timings
Switch-ON Delay tON(DELAY) 10 35 60 μsVS = 13.5 V
VOUT = 10% VS
See Figure 16
P_7.4.1.1
Switch-OFF Delay tOFF(DELAY) 10 25 50 μsVS = 13.5 V
VOUT = 90% VS
See Figure 16
P_7.4.1.2
Switch-ON Time tON 30 60 110 μsVS = 13.5 V
VOUT = 90% VS
See Figure 16
P_7.4.1.3
Switch-OFF Time tOFF 15 50 100 μsVS = 13.5 V
VOUT = 10% VS
See Figure 16
P_7.4.1.4
Switch-ON/OFF Matching
tON - tOFF
ΔtSW -20 20 60 μsVS = 13.5 V P_7.4.1.5
Voltage Slope
Data Sheet 27 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
7.5 Electrical Characteristics - Power Output Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
7.5.1 Power Output Stage - 40 mΩ
Switch-ON Slew Rate (dV/dt)ON 0.3 0.6 0.9 V/μsVS = 13.5 V
VOUT = 30% to 70%
of VS
See Figure 16
P_7.4.1.6
Switch-OFF Slew Rate -(dV/dt)OFF 0.3 0.6 0.9 V/μsVS = 13.5 V
VOUT = 70% to 30%
of VS
See Figure 16
P_7.4.1.7
Slew Rate Matching
(dV/dt)ON - (dV/dt)OFF
Δ(dV/dt)SW -0.15 0 0.15 V/μsVS = 13.5 V P_7.4.1.8
Voltages
Output Voltage Drop
Limitation at Small Load
Currents
VDS(SLC) 2718mV
1)
DEN = “high”
channel selected
with DSEL pin
IL = IL(OL) = 20 mA
See Figure 18
P_7.4.1.9
1) Not subject to production test - specified by design.
Table 13 Electrical Characteristics: Power Stages - 40 mΩ
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Output characteristics
ON-State Resistance at
TJ=25°C
RDS(ON)_25 –19–mΩ1)
TJ = 25 °C
P_7.5.6.1
ON-State Resistance at
TJ= 150 °C
RDS(ON)_150 ––36mΩTJ = 150 °C
IL = 2 A
P_7.5.6.2
ON-State Resistance in
Cranking
RDS(ON)_CRAN
K
––45mΩTJ = 150 °C
VS = 3.1 V
IL = 0.75 A
P_7.5.6.3
Table 12 Electrical Characteristics: Power Stages - PROFET™ (continued)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 28 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
ON-State Resistance in
Inverse Current at TJ = 25 °C
RDS(INV)_25 –21–mΩ1)
TJ = 25 °C
VS = 13.5 V
IL = -2 A
P_7.5.6.4
ON-State Resistance in
Inverse Current at TJ = 150 °C
RDS(INV)_150 ––45mΩTJ = 150 °C
VS = 13.5 V
IL = -2 A
P_7.5.6.5
ON-State Resistance in
Reverse Polarity at TJ = 25 °C
RDS(REV)_25 –21–mΩ1)
TJ = 25 °C
VS = -13.5 V
IL = -2 A
RSENSE = 1.2 kΩ
P_7.5.6.6
ON-State Resistance in
Reverse Polarity at
TJ= 150 °C
RDS(REV)_150 ––74mΩTJ = 150 °C
VS = -13.5 V
IL = -2 A
RSENSE = 1.2 kΩ
P_7.5.6.7
Nominal Load Current per
Channel (all Channels
Active)
IL(NOM) –3.5–A
1)
TA = 85 °C
TJ ≤ 150 °C
P_7.5.6.8
Output Leakage Current at
TJ ≤ 85 °C
IL(OFF)_85 –0.010.5μA1)
VOUT = 0 V
VIN = “low”
TA ≤ 85 °C
P_7.5.6.9
Output Leakage Current at
TJ= 150 °C
IL(OFF)_150 –1.24μAVOUT = 0 V
VIN = “low”
TA = 150 °C
P_7.5.6.10
Inverse Current Capability IL(INV) –3.5–A
1)
VS < VOUT
IN = “high”
P_7.5.6.11
Voltage Slope
Passive Slew Rate (e.g. for
Half Bridge Configuration)
|dVOUT / dt |– – 10 V/μs1)
VS = 13.5 V
P_7.5.6.12
Voltages
Drain Source Diode Voltage |VDS(DIODE)| – 650 700 mV IL = -190 mA
TJ = 150 °C
P_7.5.6.13
Switching Energy
Switch-ON Energy EON –0.44–mJ
1)
VS = 18 V
see Figure 16
P_7.5.6.14
Switch-OFF Energy EOFF –0.55–mJ
1)
VS = 18 V
see Figure 16
P_7.5.6.15
Table 13 Electrical Characteristics: Power Stages - 40 mΩ (continued)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 29 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Power Stages
1) Not subject to production test - specified by design.
Data Sheet 30 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
8 Protection
The BTS7040-2EPA is protected against Overtemperature, Overload, Reverse Battery (with ReverSave™) and
Overvoltage. Overtemperature and Overload protections are working when the device is not in Sleep mode.
Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS
pins are reverse supplied.
8.1 Overtemperature Protection
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for
each channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN))
switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until
junction temperature has reached the “Restart” condition described in Table 14. The behavior is shown in
Figure 22 (absolute Overtemperature Protection) and Figure 23 (dynamic Overtemperature Protection).
TJ(REF) is the reference temperature used for dynamic temperature protection.
Figure 22 Overtemperature Protection (Absolute)
I
L(OVL)
I
L
t
T
J
I
IS
Protection_PROFET_OT_IRC.emf
DEN
In ter nal
counter
T
J(ABS)
t
t
t
t
1
0
IN
t
I
IS(SAT)
I
IS(FAULT)
T
HYS(ABS)
t
IS(FAULT)_D
I
L
/ k
ILIS
Data Sheet 31 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
Figure 23 Overtemperature Protection (Dynamic)
When the Overtemperature protection circuitry allows the channel to be switched ON again, the retry strategy
described in Chapter 8.3 is followed.
8.2 Overload Protection
The BTS7040-2EPA is protected in case of Overload or short circuit to ground. Two Overload thresholds are
defined (see Figure 24) and selected automatically depending on the voltage VDS across the power DMOS:
•IL(OVL0) when VDS < 13 V
•IL(OVL1) when VDS > 22 V
I
L(OVL)
I
L
t
T
J
I
IS
Protection_PROFET_dT_IRC.emf
DEN
In ter nal
counter
T
J(ABS)
t
t
t
t
10
IN
t
I
IS(FAULT)
T
J(DYN)
t
IS(FAUL T)_D
I
L
/ k
ILIS
T
J(REF)
2
Data Sheet 32 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
Figure 24 Overload Current Thresholds variation with VDS
In order to allow a higher load inrush at low ambient temperature, Overload threshold is maximum at low
temperature and decreases when TJ increases (see Figure 25). IL(OVL0) typical value remains constant up to a
junction temperature of +75 °C.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
4 6 8 10 12 14 16 18 20 22 24 26 28
Drain Source Voltage (V)
Overload threshold variation ("1" = IL(OVL) typ @ VDS = 5 V)
IL(OVL0)
IL(OVL1)
Data Sheet 33 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
Figure 25 Overload Current Thresholds variation with TJ
Power supply voltage VS can increase above 18 V for short time, for instance in Load Dump or in Jump Start
condition. Whenever VS ≥ VS(JS), the overload detection current is set to IL(OVL_JS) as shown in Figure 26.
Figure 26 Overload Detection Current variation with VS voltage
When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1)), the channel is switched OFF. The channel is allowed to restart
according to the retry strategy described in Chapter 8.3.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
-40 -20 0 20 40 60 80 100 120 140 160
I
L(OVL0)
variation factor
Junction Temperature (°C)
I
L(OVL0)
variation over T
J
Typ
reference value
"1" = I
L(OVL0)
typ @ -40 °C
Protection_JS.emf
I
L(OVL )
V
S
V
S(JS)
I
L(OVL_ JS)
Data Sheet 34 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
8.3 Protection and Diagnosis in case of Fault
Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:
• The affected channel switches OFF and the internal counter is incremented
• If the diagnosis is active for the affected channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2
for further details)
The channel can be switched ON again if all the protection mechanisms fulfill the “restart” conditions
described in Table 14. Furthermore, the device has an internal retry counter (one for each channel) to
maximize the robustness in case of fault.
8.3.1 Retry Strategy
When IN is set to “high”, the channel is switched ON. In case of fault condition the output stage is switched
OFF. The channel can be allowed to restart only if the “restart” conditions for the protection mechanisms are
fulfilled (see Table 14).
The channel is allowed to switch ON for nRETRY(CR) times before switching OFF. After a time tRETRY, if the input pin
is set to “high”, the channel switches ON again for nRETRY(NT) times before switching OFF again (“retry” cycle).
After nRETRY(CYC) consecutive “retry” cycles, the channel latches OFF. It is necessary to set the input pin to “low”
for a time longer than tDELAY(CR) to de-latch the channel (“counter reset delay” time) and to reset the internal
counter to the default value.
During the “counter reset delay” time, if the input is set to “high” the channel remains switched OFF and the
timer counting tDELAY(CR) is reset, starting to count again as soon as the input pin is set to “low” again. If the
input pin remains “low” for a time longer than tDELAY(CR) the internal retry counter is reset to the default value,
allowing nRETRY(CR) retries at the next channel activation.
The retry strategy is shown in Figure 29 (flowchart), Figure 27 (timing diagram - input pin always “high”) and
Figure 28 (timing diagram - channel controlled in PWM).
Table 14 Protection “Restart” Condition
Fault condition Switch OFF event “Restart” Condition
Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN) TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)
(including hysteresis)
Overload IL ≥ IL(OVL) IL < 50 mA
TJ within TJ(ABS) and TJ(DYN) ranges
(including hysteresis)
Data Sheet 35 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
Figure 27 Retry Strategy Timing Diagram
Figure 28 Retry Strategy Timing Diagram - Channel operated in PWM
t
IN
t
RETRY
Short c ircu it
to ground
I
L
0 1 n
RETRY(CR)
In ter nal
counter n
RETRY(CR)
+ n
RETRY(NT)
n
RETRY(CR)
+ (n
RETRY(CYC)
* n
RETRY(NT)
)
t
DELAY(CR)
t
RETRY
0
n
RETRY(CR)
n
RETRY(NT)
"retry" cycle
n
RETRY(NT)
t
t
t
Protection_PROFET_time_noPWM.emf
n
RETRY(CYC)
t
DEN
t
I
IS
I
IS(FAULT)
I
L
/ k
ILIS
I
L
/ k
ILIS
t
IN
t
RETRY
Short c ircu it
to ground
I
L
0 1 n
RETRY(CR)
In ter nal
counter n
RETRY(CR)
+ n
RETRY(NT)
n
RETRY(CR)
+ (n
RETRY(CYC)
* n
RETRY(NT)
)
t
DELAY(CR)
t
RETRY
0
n
RETRY(CR)
n
RETRY(NT)
"retry" cycle
n
RETRY(NT)
t
t
t
Protection_PROFET_Timings.emf
n
RETRY(CYC)
Data Sheet 36 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
Figure 29 Retry Strategy Flowchart
Protection_PROFET_Flow.emf
Fault
(Overtemperature or
Overload)
Switch channel ON
no
Channel remains ON
Switch channel OFF
yes
Counter++
IN is "high"
yes
Channel remains OFF
yes
"Retry" cycles =
n
RETRY(CYC)
no
Wait for t
RETRY
"Retry" cycles++
yes
Wait until IN is "low" then
start counting for t
DEL AY(CR)
IN is "low"
t
DE L AY ( CR )
elapsed
Continue counting for
t
DEL AY (CR)
yes
no
no
yes
Counter = 0
"Retry" cycles = 0
Counter < n
RETRY(CR)
no
"Retry" cycles =
n
RETRY(CYC)
yes
yes
IN is "high" yes
Switch channel OFF
no
START
no
ALL "Restart"
conditions fulfilled
no
no
Data Sheet 37 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
It is possible to “force” a reset of the internal counter without waiting for tDELAY(CR) by applying a pulse (rising
edge followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have
a duration longer than tDEN(CR) to ensure a reset of the internal counter. The DSEL pin must select the channel
that has to be de-latched and keep the same logic value while DEN pin toggles twice (rising edge followed by
a falling edge).
The timings are shown in Figure 30.
Figure 30 Retry Strategy Timing Diagram with Forced Reset
8.4 Additional protections
8.4.1 Reverse Polarity Protection
In Reverse Polarity condition (also known as Reverse Battery), the output stages are switched ON (see
parameter RDS(REV)) because of ReverSave™ feature which limits the power dissipation in the output stages.
Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output
stages must be limited by the connected loads. The current through digital input pins has to be limited as well
by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application
Information in Chapter 10).
Figure 31 shows a typical application including a device with ReverSave™. A current flowing into GND pin (-
IGND) during Reverse Polarity condition is necessary to activate ReverSave™, therefore a resistive path between
module ground and device GND pin must be present.
t
IN
Short c ircu it
to ground
I
L
0 1
In ter nal
counter
n
RETRY(CR)
t
t
t
Protection_PROFET_DENforce_time2.emf
DEN
n
RETRY(CR)
1
t
t
DEN(CR)
0
t
DEN(CR)
n
RETRY(CR)
t
DEN(CR)
n
RETRY(CR)
0
Data Sheet 38 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
Figure 31 Reverse Battery Protection (application example)
8.4.2 Overvoltage Protection
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and
follow the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there
is a clamp mechanism available for Overvoltage protection for the logic and the output channels, monitoring
the voltage between VS and GND pins (VS(CLAMP)).
8.5 Protection against loss of connection
8.5.1 Loss of Battery and Loss of Load
The loss of connection to battery or to the load has no influence on device robustness when load and wire
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be
handled. PROFET™+2 devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In case of
applications where currents and/or the aforementioned inductivity are exceeded, an external suppressor
diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide a well-
defined path to the load current.
8.5.2 Loss of Ground
In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin
and the microcontroller to ensure a channel switch OFF (as described in Chapter 10).
Note: In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground
path is available, which could keep the device operational during loss of device ground.
Protection_RevBatt.emf
High-side
Channel
L, C, R
VS
OUTn
GND
IS
R
SENSE
R
GND
DI
MicrocontrollerDO R
DI
GND
-I
L
-I
GND
-I
IS
I
DI
-V
BAT(REV)
ReverSave
TM
Data Sheet 39 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
8.6 Electrical Characteristics Protection
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
8.6.1 Electrical Characteristics Protection - PROFET™
Table 15 Electrical Characteristics: Protection - General
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Thermal Shutdown
Temperature (Absolute)
TJ(ABS) 150 175 200 °C 1)2)
See Figure 22
1) Functional test only.
2) Tested at TJ = 150°C only.
P_8.6.0.1
Thermal Shutdown
Hysteresis (Absolute)
THYS(ABS) –30–K
3)
See Figure 22
3) Not subject to production test - specified by design.
P_8.6.0.2
Thermal Shutdown
Temperature (Dynamic)
TJ(DYN) –80–K
3)
See Figure 23
P_8.6.0.3
Power Supply Clamping
Voltage at TJ = -40 °C
VS(CLAMP)_-40 33 36.5 42 V IVS = 5 mA
TJ = -40 °C
See Figure 17
P_8.6.0.6
Power Supply Clamping
Voltage at TJ ≥ 25 °C
VS(CLAMP)_25 35 38 44 V 2)
IVS = 5 mA
TJ ≥ 25 °C
See Figure 17
P_8.6.0.7
Power Supply Voltage
Threshold for Overcurrent
Threshold Reduction in case
of Short Circuit
VS(JS) 20.5 22.5 24.5 V 3)
Setup acc. to AEC-
Q100-012
P_8.6.0.8
Table 16 Electrical Characteristics: Protection - PROFET™
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Automatic Retries in Case of
Fault after a Counter Reset
nRETRY(CR) –5– 1)
See Figure 27 and
Figure 28
P_8.6.1.1
Automatic Retries in Case of
Fault after the First tRETRY
Activation
nRETRY(NT) –1– 1)
See Figure 27 and
Figure 28
P_8.6.1.3
Maximum “Retry” Cycles
allowed before Channel
Latch OFF
nRETRY(CYC) –2– 1)
See Figure 27 and
Figure 28
P_8.6.1.4
Data Sheet 40 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
8.7 Electrical Characteristics Protection - Power Output Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
8.7.1 Protection Power Output Stage - 40 mΩ
Auto Retry Time after Fault
Condition
tRETRY 40 70 100 ms 1)
See Figure 27 and
Figure 28
P_8.6.1.5
Counter Reset Delay Time
after Fault Condition
tDELAY(CR) 40 70 100 ms 1)
See Figure 27 and
Figure 28
P_8.6.1.6
Minimum DEN Pulse
Duration for Counter Reset
tDEN(CR) 50 100 150 µs 2)
See Figure 30
P_8.6.1.7
1) Functional test only.
2) Not subject to production test - specified by design.
Table 17 Electrical Characteristics: Protection - 40 mΩ
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Overload Detection Current
at TJ = -40 °C
IL(OVL0)_-40 42 47 52 A 1)
TJ = -40 °C
dI/dt = 0.2 A/µs
see Figure 24
P_8.7.6.1
Overload Detection Current
at TJ = 25 °C
IL(OVL0)_25 40 46 52 A 2)
TJ = 25 °C
dI/dt = 0.2 A/µs
see Figure 24
P_8.7.6.7
Overload Detection Current
at TJ = 150 °C
IL(OVL0)_150 34 39 45 A 2)
TJ = 150 °C
dI/dt = 0.2 A/µs
see Figure 24
P_8.7.6.8
Overload Detection Current
at High VDS
IL(OVL1) –26–A
2)
dI/dt = 0.2 A/µs
see Figure 24
P_8.7.6.5
Overload Detection Current
Jump Start Condition
IL(OVL_JS) –26–A
2)
VS > VS(JS)
dI/dt = 0.2 A/µs
P_8.7.6.6
Table 16 Electrical Characteristics: Protection - PROFET™ (continued)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 41 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Protection
1) Functional test only.
2) Not subject to production test - specified by design.
Data Sheet 42 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9 Diagnosis
For diagnosis purpose, the BTS7040-2EPA provides a combination of digital and analog signals at pin IS. These
signals are generically named SENSE and written IIS. In case of disabled diagnostic (DEN pin set to “low”), IS
pin becomes high impedance.
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS
pin to the sense current output of other devices, if they are supplied by a different battery feed.
See Figure 32 for details as an overview.
Figure 32 Diagnosis Block Diagram
9.1 Overview
Table 18 gives a quick reference to the state of the IS pin during BTS7040-2EPA operation.
Channel 1
Diagnosis_PROFET_2CH.emf
IS Pin Control
Logic
Internal Counters
INn
DSEL
DEN
Overtemperature
I
IS(FAULT)
OUT0
VS
MUX
V
DS(OLOFF)
I
IS(OLOFF)
MUX
IS
R
SENSE
OUT1
MUX
+
Channel 0
T
I
L
/ k
ILIS
Data Sheet 43 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.1.1 SENSE signal truth table
In case DEN is set to “high”, the SENSE for the selected channel is enabled or disabled using DSEL pin. Table 19
gives the truth table.
9.2 Diagnosis in ON state
A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions
are fulfilled:
Table 18 SENSE Signal, Function of Application Condition
Application Condition Input level DEN level VOUT Diagnostic Output
Normal operation “low” “high” ~ GND Z
IIS(FAULT) if counter > 0
Short circuit to GND ~ GND Z
IIS(FAULT) if counter > 0
Overtemperature Z IIS(FAULT)
Short circuit to VSVSIIS(OLOFF)
(IIS(FAULT) if counter > 0)
Open Load < VS - VDS(OLOFF)
> VS - VDS(OLOFF)1)
1) With additional pull-up resistor.
Z
IIS(OLOFF)
(in both cases IIS(FAULT) if
counter > 0)
Inverse current ~ VINV = VOUT > VSIIS(OLOFF)
(IIS(FAULT) if counter > 0)
Normal operation “high” ~ VSIIS = IL / kILIS
Overcurrent < VSIIS(FAULT)
Short circuit to GND ~ GND IIS(FAULT)
Overtemperature Z IIS(FAULT)
Short circuit to VSVSIIS < IL / kILIS
Open Load ~ VS2)
2) The output current has to be smaller than IL(OL).
IIS = IIS(EN)
Under load (e.g. Output Voltage
Limitation condition)
~ VS3)
3) The output current has to be higher than IL(OL).
IIS(EN) < IIS < IL(NOM) / kILIS
Inverse current ~ VINV = VOUT > VSIIS = IIS(EN)
All conditions n.a. “low” n.a. Z
Table 19 Diagnostic Truth Table
DEN DSEL IS
“low” not relevant Z
“high” “low” SENSE output 0
“high” “high” SENSE output 1
Data Sheet 44 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
• The power output stage is switched ON with VDS < 2 V
• The diagnosis is enabled for that channel
• No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for
further details)
If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.
9.2.1 Current Sense (kILIS)
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in
Figure 34. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical
product.
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:
• A well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side
• The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
• Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by
ΔkILIS
The derating of kILIS after calibration is calculated using the formulas in Figure 33 and it is specified by ΔkILIS
Figure 33 ΔkILIS calculation formulas
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift
overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H.
Figure 34 Current Sense Ratio in Open Load at ON condition
Diagnosis_dKILIS.em f
IIS
ILIL(OL)
IIS(OL)
Di agn os is_ OLON _adv .em f
IIS(EN)
Data Sheet 45 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.2.2 Fault Current (IIS(FAULT))
As soon a protection event occurs, changing the value of the internal retry counter (see Chapter 8.3 for more
details) from its reset state, a current IIS(FAULT) is provided by pin IS when DEN is set to “high” and the affected
channel is selected. The following 3 situations may occur:
• If the channel is ON and the number of retries is lower than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current
IIS(FAULT) is provided for a time tIS(FAULT)_D after the channel is allowed to restart, after which IIS = IL / kILIS (as
shown in Figure 35). During a retry cycle (while timer tRETRY is running) the current IIS(FAULT) is provided each
time the channel diagnosis is checked
• If the channel is ON and the number of retries is equal than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current
IIS(FAULT) is provided until the internal counter is reset (either by expiring of tDELAY(CR) time or by DEN pin
pulse, as described in Chapter 8.3.1)
• If the channel is OFF and the internal counter is not in the reset state, the current IIS(FAULT) is provided each
time the channel diagnosis is checked
Figure 35 IIS(FAULT) at Load Switching
Figure 36 adds the behavior of SENSE signal to the timing diagram seen in Figure 28, while Figure 37 shows
the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT).
t
IN
I
L
0 1
In ter nal
counter
t
t
Diagnosis_PROFET_IISFAULT_load.emf
t
DEN
t
I
IS
I
IS(FAULT)
I
L
/ k
ILIS
t
IS(FAUL T)_D
2
I
IS(FAULT)
0
I
L(OVL)
Data Sheet 46 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
Figure 36 SENSE behavior in Fault condition
Figure 37 SENSE behavior - overview
9.3 Diagnosis in OFF state
When a power output stage is in OFF state, the BTS7040-2EPA can measure the output voltage and compare
it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and
a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to
battery. If a Fault condition was detected by the device (the internal counter has a value different from the
reset value, as described in Chapter 9.2.2) a current IIS(FAULT) is provided by IS pin each time the channel
diagnosis is checked also in OFF state.
t
IN
t
RETRY
Short c ircu it
to ground
I
L
0 1 n
RETRY(CR)
In ter nal
counter n
RETRY(CR)
+ n
RETRY(NT)
n
RETRY(CR)
+ (n
RETRY(CYC)
* n
RETRY(NT)
)
t
DELAY(CR)
t
RETRY
0
n
RETRY(CR)
n
RETRY(NT)
"retry" cycle
n
RETRY(NT)
t
t
t
Diagnosis_PROFET_IISFAULT.emf
t
DEN
t
I
IS
I
IS(FAULT)
I
IS(FAULT)
I
L
/ k
ILIS
n
RETRY(CYC)
I
IS(FAULT)
Diagnosis_PROFET_IISFAULT_IISSAT.emf
I
IS
I
L
I
IS(SAT)
I
IS(FAULT)
I
L
/ k
ILIS
I
IS(SAT),min
=
I
IS(FAUL T),min
I
IS(FAUL T),max
I
IS(SAT),max
I
L(OVL)
Data Sheet 47 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.3.1 Open Load current (IIS(OLOFF))
In OFF state, when DEN pin is set to “high” and a channel is selected using DSEL pin, the VDS voltage is
compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to
battery, VDS ~ VS therefore VDS > VDS(OLOFF). When the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is
provided by IS pin. Figure 38 shows the relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two
currents do not overlap making always possible to differentiate between Open Load in OFF and Fault
condition.
Figure 38 IIS in OFF State
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for
Open Load in OFF diagnosis to allow the internal comparator to settle. In Figure 39 the timings for an Open
Load detection are shown - the load is always disconnected.
Figure 39 Open Load in OFF Timings - load disconnected
Di agn os is_P ROFE T_I I SOL OFF . em f
I
IS
V
DS
I
IS(OLOFF)
V
DS(OLOFF)
I
IS(FAULT)
t
IN
t
DEN
V
OUT
~ V
S
t
IS(OLOFF)_D
t
I
IS(OLOFF)
I
IS
I
IS(OL)
V
DS(OLOFF)
t
Diagnosis_PROFET_OLOFF_time.emf
Load
conn ected
Data Sheet 48 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.4 SENSE Timings
Figure 40 and Figure 42 show the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including
the case of load change). As a proper signal cannot be established before the load current is stable (therefore
before tON), tsIS(DIAG) = tsIS(ON) + tON.
Figure 40 SENSE Settling / Disabling Timing
Figure 41 SENSE Timing with Small Load Current
t
t
t
I
L
I
IS
DEN
t
ONOFF OFF
Diagnose_PROFET_SENSE_timings.emf
IN
t
sIS(DIAG)
t
sIS(LC)
t
sIS(OFF)
t
sIS(ON)
t
sIS(OFF)
t
OFF
DEN
t
t
t
t
ON
OFF
IN
OFF
Di agnose_PROFE T_SENSE_timings_S LC.em f
tsIS(ON)_SLC tsIS(ON) tsIS(LC)_SLC
IL
IIS
Data Sheet 49 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
Figure 42 SENSE Settling Timing - Channel Change
Diagnose_PROFET_SENSE_timings_CC.emf
DSEL
I
IS
t
t
t
I
L1
t
t
sI S(CC)
t
sIS(OFF)
DEN
t
sIS(ON)
t
sI S(CC) _SLC
t
I
L0
I
L(CAL)_L
I
L(CAL)
I
L(CAL)_OL
Data Sheet 50 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.5 Electrical Characteristics Diagnosis
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
Table 20 Electrical Characteristics: Diagnosis - General
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
SENSE Saturation Current IIS(SAT) 4.4 – 15 mA 1)
VS = 8 V to 18 V
RSENSE = 1.2 kΩ
See Figure 37
P_9.6.0.13
SENSE Saturation Current IIS(SAT) 4.1 – 15 mA 1)
VS = 6 V to 18 V
RSENSE = 1.2 kΩ
See Figure 37
P_9.6.0.14
SENSE Leakage Current
when Disabled
IIS(OFF) –0.010.5µADEN = “low”
IL ≥ IL(NOM)
VIS = 0 V
P_9.6.0.2
SENSE Leakage Current
when Enabled at TJ ≤ 85 °C
IIS(EN)_85 –0.21µA
1)
TJ ≤ 85 °C
DEN = “high”
IL = 0 A
See Figure 34
P_9.6.0.3
SENSE Leakage Current
when Enabled at TJ = 150 °C
IIS(EN)_150 –0.21µATJ = 150 °C
DEN = “high”
IL = 0 A
See Figure 34
P_9.6.0.4
SENSE Operative Range for
kILIS Operation
(VS - VIS)
VSIS_k –0.51V
1)
VS = 6 V
IN = DEN = “high”
IL ≤ 1.2 * IL(NOM)
P_9.6.0.6
SENSE Operative Range for
Open Load at OFF Diagnosis
(VS - VIS)
VSIS_OL –0.51V
1)
VS = 6 V
IN = “low”
DEN = “high”
P_9.6.0.7
SENSE Operative Range for
Fault Diagnosis
(VS - VIS)
VSIS_F –0.51V
1)
VS = 6 V
IN = “low”
DEN = “high”
counter > 0
P_9.6.0.8
Data Sheet 51 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.5.1 Electrical Characteristics Diagnosis - PROFET™
Power Supply to IS Pin
Clamping Voltage at
TJ=-40°C
VSIS(CLAMP)_-
40
33 36.5 42 V IIS = 1 mA
TJ = -40 °C
See Figure 17
P_9.6.0.9
Power Supply to IS Pin
Clamping Voltage at
TJ≥25 °C
VSIS(CLAMP)_25 35 38 44 V 2)
IIS = 1 mA
TJ ≥ 25 °C
See Figure 17
P_9.6.0.10
1) Not subject to production test - specified by design.
2) Tested at TJ = 150°C.
Table 21 Electrical Characteristics: Diagnosis - PROFET™
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
SENSE Fault Current IIS(FAULT) 4.4 5.5 10 mA See Figure 37 and
Figure 38
P_9.6.1.1
SENSE Open Load in OFF
Current
IIS(OLOFF) 1.9 2.5 3.5 mA See Figure 37 and
Figure 38
P_9.6.1.2
SENSE Delay Time at
Channel Switch ON after
Last Fault Condition
tIS(FAULT)_D – 500 – µs 1)
See Figure 35
P_9.6.1.3
SENSE Open Load in OFF
Delay Time
tIS(OLOFF)_D 30 70 120 µs VDS < VOL(OFF)
from IN falling
edge to IIS =
IS(OLOFF),MIN * 0.9
DEN = “high”
counter = 0
See Figure 39
P_9.6.1.4
Open Load VDS Detection
Threshold in OFF State
VDS(OLOFF) 1.3 1.8 2.3 V See Figure 38 P_9.6.1.5
SENSE Settling Time with
Nominal Load Current
Stable
tsIS(ON) –520µsIL=IL(CAL)
from DEN rising
edge to IIS =IL/
(kILIS,MAX @IL) * 0.9
See Figure 40
P_9.6.1.6
SENSE Settling Time with
Small Load Current Stable
tsIS(ON)_SLC ––60µs
1)
IL=IL(CAL)_OL
from DEN rising
edge to IIS =IL/
(kILIS,MAX @IL) * 0.9
P_9.6.1.13
Table 20 Electrical Characteristics: Diagnosis - General (continued)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 52 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.6 Electrical Characteristics Diagnosis - Power Output Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
SENSE Disable Time tsIS(OFF) –520µs
1)
From DEN falling
edge to IIS =IIS(OFF)
See Figure 40
P_9.6.1.8
SENSE Settling Time after
Load Change
tsIS(LC) –520µs
1)
from IL=IL(CAL)_L to
IL=IL(CAL) (see
ΔkILIS(NOM))
See Figure 40
P_9.6.1.9
SENSE Settling Time after
Load Change with Small
Load Current
tsIS(LC)_SLC – 250 400 µs 1)
DEN = “high”
from Load Change
to IIS =IL/ (kILIS @IL)
from IL(CAL) to
IL(CAL)_OL
P_9.6.1.14
SENSE Settling Time after
Channel Change
tsIS(CC) –520µs
1)
Start channel:
IL=IL(CAL)
End channel:
IL=IL(CAL)_L
(see ΔkILIS(NOM))
See Figure 42
P_9.6.1.10
SENSE Settling Time after
Channel Change with Small
Load Current
tsIS(CC)_SLC ––60µs
1)
DEN = “high”
from DSEL toggling
to IIS =IL/
(kILIS,MIN @IL) * 1.1
Start channel:
IL=IL(CAL)
End Channel:
IL=IL(CAL)_OL
(see ΔkILIS(NOM) and
ΔkILIS(OL))
P_9.6.1.15
1) Not subject to production test - specified by design.
Table 21 Electrical Characteristics: Diagnosis - PROFET™ (continued)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 53 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Diagnosis
9.6.1 Diagnosis Power Output Stage - 40 mΩ
Table 22 Electrical Characteristics: Diagnosis - 40 mΩ
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Open Load Output Current
at IIS = 4 µA
IL(OL)_4u 1611mAIIS = IIS(OL) = 4 µA P_9.7.6.1
Current Sense Ratio at
IL = IL02
kILIS02 -40% 1800 +40% IL02 = 20 mA P_9.7.6.6
Current Sense Ratio at
IL = IL04
kILIS04 -35% 1800 +35% IL04 = 50 mA P_9.7.6.8
Current Sense Ratio at
IL = IL05
kILIS05 -30% 1800 +30% IL05 = 100 mA P_9.7.6.9
Current Sense Ratio at
IL = IL08
kILIS08 -26% 1800 +26% IL08 = 250 mA P_9.7.6.12
Current Sense Ratio at
IL = IL11
kILIS11 -11% 1800 +11% IL11 = 1 A P_9.7.6.15
Current Sense Ratio at
IL = IL13
kILIS13 -6% 1800 +6% IL13 = 2 A P_9.7.6.17
Current Sense Ratio at
IL = IL15
kILIS15 -5% 1800 +5% IL15 = 4 A P_9.7.6.19
SENSE Current Derating
with Low Current
Calibration
ΔkILIS(OL) -30 0 +30 % 1)
IL(CAL)_OL = IL04
IL(CAL)_OL_H = IL05
IL(CAL)_OL_L = IL02
TA(CAL) = 25 °C
See Figure 33
P_9.7.6.27
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM) -4 0 +4 % 1)
IL(CAL) = IL13
IL(CAL)_H = IL15
IL(CAL)_L = IL11
TA(CAL) = 25 °C
See Figure 33
1) Not subject to production test - specified by design.
P_9.7.6.29
Data Sheet 54 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Application Information
10 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
10.1 Application Setup
Figure 43 BTS7040-2EPA Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.
Table 23 Loads considered for Reverse Polarity setup (see P_4.1.0.5)
Output RDS(ON),max @ TJ = 150 °C Load connected
40 mΩ36 mΩP27W + R5W
GPIO
GPIO
GPIO
GPIO
A/D IN
VSS
VDD
Micro controller
IN0
IN1
DEN
DSEL
IS GND
OUT0
OUT1
VS
V
BAT
C
SENSE
D
Z1
R/L cable
R/L cable
R/L cable
C
OUT1
C
OUT0
R
IN
R
IN
R
DEN
R
DSEL
R
AD
R
IS_PROT
R
SENSE
R
GND
V
DD
R
PD
R
PD
C
VS
R
OL
T
1
D
Z2
App_2CH_LI_INTDIO.emf
Data Sheet 55 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Application Information
10.2 External Components
10.3 Further Application Information
• Please contact us for information regarding the Pin FMEA
• For further information you may contact http://www.infineon.com/
Table 24 Suggested Component values
Reference Value Purpose
RIN 4.7 kΩProtection of the microcontroller during Overvoltage and Reverse Polarity.
Necessary to switch OFF BTS7040-2EPA output during Loss of Ground
RDEN 4.7 kΩProtection of the microcontroller during Overvoltage and Reverse Polarity.
Necessary to switch OFF BTS7040-2EPA output during Loss of Ground
RDSEL 4.7 kΩProtection of the microcontroller during Overvoltage and Reverse Polarity.
Necessary to switch OFF BTS7040-2EPA output during Loss of Ground
RPD 47 kΩOutput polarization (pull-down).
Improves BTS7040-2EPA immunity to electromagnetic noise
ROL 1.5 kΩOutput polarization (pull-up).
Ensure polarization of BTS7040-2EPA output during Open Load in OFF
diagnosis
COUT 10 nF Protection of BTS7040-2EPA output during ESD events and BCI
T1BC 807 Switch the battery voltage for Open Load in OFF diagnosis
CVS 68 nF Filtering of voltage spikes on the battery line
DZ2 33 V Z-Diode Suppressor diode
Protection during Overvoltage and in case of Loss of Battery while driving
an inductive load
RSENSE 1.2 kΩSENSE resistor
RIS_PROT 4.7 kΩProtection during Overvoltage, Reverse Polarity, Loss of Ground.
Value to be tuned according to microcontroller specifications
DZ1 7 V Z-Diode Protection of microcontroller during Overvoltage
RA/D 4.7 kΩProtection of microcontroller ADC input during Overvoltage, Reverse
Polarity, Loss of Ground.
Value to be tuned according to microcontroller specifications
CSENSE 220 pF Sense signal filtering
A time constant (RA/D * CSENSE) longer than 1 µs is recommended
RGND 47 Ω
(1/16 W)
Protection in case of Overvoltage and Loss of Battery while driving
inductive loads
Data Sheet 56 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Package Outlines
11 Package Outlines
Figure 44 PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package Outline
Figure 45 PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil
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Data Sheet 57 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet 58 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
Revision History
12 Revision History
Table 25 BTS7040-2EPA - List of changes
Revision Changes
1.03, 2018-06-14 Chapter 7.4.1 updated chapter title (PROFET → PROFET™)
Table 12 updated table title (PROFET → PROFET™)
Chapter 8.6.1 updated chapter title (PROFET → PROFET™)
Table 16 updated table title (PROFET → PROFET™)
Chapter 9.5.1 updated chapter title (PROFET → PROFET™)
Table 21 updated table title (PROFET → PROFET™)
P_4.1.0.21, P_4.1.0.22, P_4.1.0.23, P_4.1.0.24 updated (footnote ESD standards)
Table 1 updated (RDS(ON) → RDS(ON)_150), (VDS(CLAMP) → VDS(CLAMP)_25)
Chapter 8.5.2 updated phrasing
P_7.5.6.14 Table subheading "Switching Energy" added
P_7.5.6.15 Table subheading "Switching Energy" added
Chapter 6.4 added conditions
Chapter 7.5 added conditions
P_7.5.6.14 updated (Test condition: add "See Figure")
P_7.5.6.15 updated (Test condition: add "See Figure")
Chapter 8.7 added conditions
Chapter 9.6 added conditions
P_9.7.6.27 updated (Test condition: add "See Figure")
P_9.7.6.29 updated (Test condition: add "See Figure")
Chapter 7.3.1 typo corrected (link to Figure 19 added)
1.02, 2017-11-17 Table 6 footnote updated ("Specified RthJA value is" removed)
Figure 17 symbol updated (VIS(CLAMP) → VSIS(CLAMP))
1.01, 2017-10-24 Figures updated (straight lines for signals that are crossing, points for connections; typos,
capitalization/lower case printing)
Typos and misspelling corrected according to style guidelines, inconsistencies among
document resolved
P_4.1.0.36 updated (symbol: IDI → IDI(REV))
P_5.4.0.5 symbol updated (IDI → IDI(H))
P_5.4.0.6 symbol updated (IDI → IDI(L))
Chapter 7.3.3 updated
Table 24 updated (RDSEL included)
1.00, 2017-08-24 Data Sheet available
Table of Contents
Data Sheet 59 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.1 Power Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.1 PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.2 Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Input Pins (INn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Diagnosis Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.1 Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.2 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.4 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.5 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Electrical Characteristics Power Supply - Product Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.1 BTS7040-2EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.1 Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.2 Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.3 Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.1 Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.2 Switching Channels in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.3 Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4.1 Electrical Characteristics Power Stages - PROFET™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5.1 Power Output Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table of Contents
Table of Contents
Data Sheet 60 Rev. 1.03
2018-06-14
BTS7040-2EPA
PROFET™+2
8 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2 Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3 Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.3.1 Retry Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.4 Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.4.1 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.4.2 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5 Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5.1 Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5.2 Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.6 Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.6.1 Electrical Characteristics Protection - PROFET™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.7 Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.7.1 Protection Power Output Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1.1 SENSE signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2 Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2.1 Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.2 Fault Current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3.1 Open Load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.4 SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5.1 Electrical Characteristics Diagnosis - PROFET™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.6 Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.6.1 Diagnosis Power Output Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1 Application Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.3 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-06-14
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
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WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.
Please read the Important Notice and Warnings at the end of this document
