Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-2946/7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• High-speed address/chip select time
— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)
— Commercial: 20/25/35/45ns (max.) Low Power only.
• Low-power operation
• Battery Backup operation — 2V data retention
• Produced with advanced high-performance CMOS
technology
• Input and output directly TTL-compatible
• Available in standard 28-pin (300 or 600 mil) ceramic
DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ
and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71256 is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology.
Address access times as fast as 20ns are available with
power consumption of only 350mW (typ.). The circuit also
offers a reduced power standby mode. When
CS
goes HIGH,
the circuit will automatically go to, and remain in, a low-power
standby mode as long as
CS
remains HIGH. In the full standby
mode, the low-power device consumes less than 15µW,
typically. This capability provides significant system level
power and cooling savings. The low-power (L) version also
offers a battery backup data retention capability where the
circuit typically consumes only 5µW when operating off a 2V
battery.
The lDT71256 is packaged in a 28-pin (300 or 600 mil)
ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600
mil) plastic DIP, and 32-pin LCC providing high board-level
packing densities.
The IDT71256 military RAM is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
1
FUNCTIONAL BLOCK DIAGRAM
A
ADDRESS
DECODER 262,144 BIT
MEMORY ARRAY
I/O CONTROL
2946 drw 01
INPUT
DATA
CIRCUIT
WE
CS
VCC
GND
0
A14
I/O 0
I/O 7
CONTROL
CIRCUIT
OE
7.2
CMOS STATIC RAM
256K (32K x 8-BIT) IDT71256S
IDT71256L
7.2 2
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
TRUTH TABLE(1)
WE
WE CS
CS OE
OE
I/O Function
X H X High-Z Standby (ISB)
XVHC X High-Z Standby (ISB1)
H L H High-Z Output Disabled
HLLDOUT Read Data
LLXD
IN Write Data
NOTE: 2946 tbl 02
1. H = VIH, L = VIL, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Com’l. Mil. Unit
VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
TAOperating 0 to +70 –55 to +125 °C
Temperature
TBIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
TSTG Storage –55 to +125 –65 to +150 °C
Temperature
PTPower Dissipation 1.0 1.0 W
IOUT DC Output 50 50 mA
Current
NOTE: 2946 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 0V 11 pF
CI/O I/O Capacitance VOUT = 0V 11 pF
NOTE: 2946 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
PIN DESCRIPTIONS
Name Description
A0–A14 Addresses
I/O0–I/O7Data Input/Output
CS
Chip Select
WE
Write Enable
OE
Output Enable
GND Ground
VCC Power
2946 tbl 01
2946 drw 02
5
6
7
8
9
10
11
12
A12
1
2
3
424
23
22
21
20
19
18
17
D28-3
P28-1
P28-2
D28-1
SO28-5
13
14
28
27
26
25
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
I/O 1
VCC
WE
A8
A9
A11
OE
A10
CS
I/O 7
16
15
I/O 2
GND
I/O 6
I/O 5
I/O 4
I/O 3
A14
A13
32-Pin LCC
TOP VIEW
DIP/SOJ
TOP VIEW
5
6
7
8
9
10
11
L32-1
29
28
27
26
25
24
23
15 16 17 18 19
32132 31
INDEX
A3
A2
VCC
A7
GND
WE
OE
NC
A8
A9
A11
A10
CS
12 22
13 21
A6
A5
A4
A12
2946 drw 03
A1
A0
I/O0
430
2014
NC
NC
I/O7
2
I/O
3
I/O4
I/O5
I/O
I/O6
NC
A14
A13
I/O 1
7.2 3
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71256S/L20 71256S/L25 71256S/L30 71256S/L35
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit
ICC Dynamic Operating Current S — — — 150 — 145 — 140 mA
CS
≤ VIL, Outputs Open
VCC = Max., f = fMAX(2) L 135 — 115 130 — 125 105 120
ISB Standby Power Supply S — — — 20 — 20 — 20 mA
Current (TTL Level)
CS
≥ VIH, VCC = Max., L 3 — 3 3 — 3 3 3
Outputs Open, f = fMAX(2)
ISB1 Full Standby Power Supply S — — — 20 — 20 — 20 mA
Current (CMOS Level)
CS
≥ VHC, VCC = Max., f = 0 L 0.4 — 0.4 1.5 — 1.5 0.4 1.5
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Temperature GND VCC
Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%
2946 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — 6.0 V
VIL Input Low Voltage –0.5(1) — 0.8 V
NOTE: 2946 tbl 06
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
NOTES: 2946 tbl 07
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling.
3. Also available: 120 and 150 ns military devices.
71256S/L45 71256S/L55 71256S/L70 71256S/L85(3) 71256S/L100(3)
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com'l. Mil. Unit
ICC Dynamic Operating Current S — 135 — 135 — 135 — 135 — 135 mA
CS
≤ VIL, Outputs Open
VCC = Max., f = fMAX(2) L 100 115 — 115 — 115 — 115 — 115
ISB Standby Power Supply S — 20 — 20 — 20 — 20 — 20 mA
Current (TTL Level)
CS
≥ VIH, VCC = Max., L 3 3 — 3 — 3 — 3 — 3
Outputs Open, f = fMAX(2)
ISB1 Full Standby Power Supply S — 20 — 20 — 20 — 20 — 20 mA
Current (CMOS Level)
CS
≥ VHC, VCC = Max., f = 0 L 0.4 1.5 — 1.5 — 1.5 — 1.5 — 1.5
7.2 4
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2946 tbl 08
Figure 1. AC Test Load Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
*Includes scope and jig capacitances
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC – 0.2V Typ. (1) Max.
VCC @VCC @
Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention — 2.0 — — — — V
ICCDR Data Retention Current MIL. — — — 500 800 µA
COM’L. — — — 120 200
tCDR Chip Deselect to Data
CS
≥ VHC 0————ns
Retention Time
tR(3) Operation Recovery Time tRC(2) ————ns
NOTES: 2946 tbl 10
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10% IDT71256S IDT71256L
Symbol Parameter Test Condition Min. Typ. Max. Min. Typ. Max. Unit
|ILI| Input Leakage Current VCC = Max., MIL. — — 10 — — 5 µA
VIN = GND to VCC COM’L. — — 5 — — 2
|ILO| Output Leakage Current VCC = Max.,
CS
= VIH, MIL. — — 10 — — 5 µA
VOUT = GND to VCC COM’L. — — 5 — — 2
VOL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 — — 0.4 V
IOL = 10mA, VCC = Min. — — 0.5 — — 0.5
VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — — 2.4 — — V
2946 tbl 09
2946 drw 05
480
Ω
5pF*
255
Ω
DATA
OUT
5V
2946 drw 04
480
Ω
30pF*
255
Ω
DATA
OUT
5V
7.2 5
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
2946 drw 06
DATA
RETENTION
MODE
4.5V 4.5V
VDR≥2V
VIH VIH
tRtCDR
VCC
CS VDR
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S25 71256S30(3) 71256S35 71256S45
71256L20(1) 71256L25 71256L30(3) 71256L35 71256L45
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 20 — 25 — 30 — 35 — 45 — ns
tAA Address Access Time — 20 — 25 — 30 — 35 — 45 ns
tACS Chip Select Access Time — 20 — 25 — 30 — 35 — 45 ns
tCLZ(2) Chip Select to Output in Low-Z 5 — 5 — 5 — 5 — 5 — ns
tCHZ(2) Chip Deselect to Output in High-Z — 10 — 11 — 15 — 15 — 20 ns
tOE Output Enable to Output Valid — 10 — 11 — 13 — 15 — 20 ns
tOLZ(2) Output Enable to Output in Low-Z 2 — 2 — 2 — 2 — 0 — ns
tOHZ(2) Output Disable to Output in High-Z 2 8 2 10 2 12 2 15 — 20 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — ns
Write Cycle
tWC Write Cycle Time 20 — 25 — 30 — 35 — 45 — ns
tCW Chip Select to End-of-Write 15 — 20 — 25 — 30 — 40 — ns
tAW Address Valid to End-of-Write 15 — 20 — 25 — 30 — 40 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 15 — 20 — 25 — 30 — 35 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
tDW Data to Write Time Overlap 11 — 13 —14—15— 20—ns
tWHZ(2) Write Enable to Output in High-Z — 10 — 11 — 15 — 15 — 20 ns
tDH Data Hold from Write Time 0 — 0 — 0 — 0 — 0 — ns
tOW(2) Output Active from End-of-Write 5 — 5 — 5 — 5 — 5 — ns
NOTES: 2946 tbl 11
1. 0° to +70°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. –55° to +125°C temperature range only.
7.2 6
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S55(1) 71256S70(1) 71256S85(1) 71256S100(1,3)
71256L55(1) 71256L70(1) 71256L85(1) 71256L100(1,3)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 55 — 70 — 85 — 100 — ns
tAA Address Access Time — 55 — 70 — 85 — 100 ns
tACS Chip Select Access Time — 55 — 70 — 85 — 100 ns
tCLZ(2) Chip Deselect to Output in Low-Z 5 — 5 — 5 — 5 — ns
tCHZ(2) Output Enable to Output in Low-Z — 25 — 30 — 35 — 40 ns
tOE Output Enable to Output Valid — 25 — 30 — 35 — 40 ns
tOLZ(2) Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns
tOHZ(2) Output Disable to Output in High-Z 0 25 0 30 — 35 — 40 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns
Write Cycle
tWC Write Cycle Time 55 — 70 — 85 — 100 — ns
tCW Chip Select to End-of-Write 50 — 60 — 70 — 80 — ns
tAW Address Valid to End-of-Write 50 — 60 — 70 — 80 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 40 — 45 — 50 — 55 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — ns
tDW Data to Write Time Overlap 25 — 30 — 35 — 40 — ns
tDH Data Hold from Write Time (
WE
)0—0—0—0—ns
tWHZ(2) Write Enable to Output in High-Z — 25 — 30 — 35 — 40 ns
tOW(2) Output Active from End-of-Write 5 — 5 — 5 — 5 — ns
NOTES: 2946 tbl 11
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. Also available: 120 and 150 ns military devices.
7.2 7
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
2946 drw 07
ADDRESS
CS
DATA OUT
tRC
tAA tOH
tACS
tCLZ tCHZ (5)
tOE
tOLZ
(5)
(5) tOHZ (5)
OE
2946 drw 08
ADDRESS
tRC
tAA tOH
tOH
DATA OUT
2946 drw 09
DATA
OUT
CS
t
ACS
(5)
t
CLZ (5)
t
CHZ
7.2 8
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
CONTROLLED TIMING)(1, 2, 3, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CS
CONTROLLED TIMING)(1, 2, 3, 5)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. tWR is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP. For a
CS
controlled write cycle,
OE
may be LOW with no degradation to tCW.
CS
2946 drw 10
tAW
tWR
tDW
DATA IN
ADDRESS
tWC
WE
tWP
DATA OUT
tWHZ tOW
(4)
(7)
tAS
(6)
(4)
tOHZ (6)
OE
tDH
t
CS
2946 drw 11
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH2
t
AS
t
WR
(7)
7.2 9
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
X
Power
XXX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
BMilitary (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
TD
D
Y
P
L
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
Leadless Chip Carrier (32-pin) (L32-1)
20
25
30
35
45
55
70
85
100
120
150
Commercial Only
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
S
LStandard Power
Low Power
71256
Device
Type
IDT
Speed in nanoseconds
2946 drw 12
