MO SEL VITELIC
1
V437316S04V
3.3 VOLT 16M x 72 HIGH PERFORMANCE
UNBUFFERED ECC SDRAM MODULE
PRELIMINARY
V437316S04V Rev. 1.0 December 2001
Features
■168 Pin Unbuffered 16,777,216 x 72 bit
Oganization SDRAM ECC DIMMs
■Utilizes High Performance 128 Mbit, 16M x 8
SDRAM in TSOPII-54 Packages
■Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■Single +3.3V (± 0.3V) Power Supply
■Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■Auto Refresh (CBR) and Self Refresh
■All Inputs, Outputs are LVTTL Compatible
■4096 Refresh Cycles every 64 ms
■Serial Present Detect (SPD)
■SDRAM Performance
Description
The V437316S04V memory module is organized
16,777,216 x 72 bits in a 168 pin dual in line
memory module (DIMM). The 16M x 72 memory
module uses 9 Mosel-Vitelic 16M x 8 SDRAM. The
x72 modules are ideal for use in high performance
computer systems where increased memory
density and fast access times are required.
Part Number Speed
Grade Configuration
V437316S04VXTG-75PC -75PC, CL=2,3
(133 MHz) 16M x 72
V437316S04VXTG-75 -75, CL=3
(133 MHz) 16M x 72
V437316S04VXTG-10PC -10PC, CL=2,3
(100 MHz) 16M x 72
V437316S04VTG-75-01
2
V437316S04V Rev. 1.0 December 2001
MO SEL VITELIC
V437316S04V
Pin Configurations (Front Side/Back Side)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CB0
CB1
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2
CB3
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4
CB5
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
NC
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6
CB7
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Pin Names
A0–A11 Address Inputs
I/O1–I/O64 Data Inputs/Outputs
RAS Row Address Strobe
CAS Column Address Strobe
WE Read/Write Input
BA0, BA1 Bank Selects
CKE0, CKE1 Clock Enable
CS0–CS3Chip Select
CLK0–CLK3 Clock Input
DQM0–DQM7 Data Mask
VCC Power (+3.3 Volts)
VSS Ground
SCL Clock for Presence Detect
SDA Serial Data OUT for Presence
Detect
SA0–A2 Serial Data IN for Presence
Detect
CB0–CB7 Check Bits (x72 Organization)
NC No Connection
DU Don’tUse
MO SEL VITELIC
V437316S04V
3
V437316S04V Rev. 1.0 December 2001
Part Number Information
Block Diagram
V 4 3 73 16 S 0 4 V X T G -XX
SDRAM
3.3V WIDTH
DEPTH
168 PIN Unbuffered
DIMM X8 COMPONENT
REFRESH
RATE 4K 4 BANKS
LVTTL
COMPONENT A=0.17u B=0.14u
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G=GOLD
SPEED
75PC = PC133 CL3,2
MOSEL VITELIC
MANUFACTURED 75 = PC133 CL3
10PC = PC133 CL3,2
DQM0
I/O1–I/O8
CS0
10
10
10
10
WE
WE DQM4
I/O40–I/O33
DQM1
I/O9–I/O16 DQM5
I/O48–I/O41
DQM2
I/O17–I/O24
CS2
10
10
10
10
DQM6
I/O49–I/O56
DQM3
I/O25–I/O32 DQM7
I/O57–I/O64
V437316S04VTG-75-03
WE: SDRAM D0-D8
CKE: SDRAM D0-D8
RAS: SDRAM D0-D8
A(11:0): SDRAM D0-D8
BA0, BA1: SDRAM D0-D8
CKE0
RAS
CAS
WE
A(11:0)
BA0, BA1
CAS: SDRAM D0-D8
C0-C15 D0-D8
D0-D8
V
CC
V
SS
SCL0
SA2
SA1
SA0
SDA
WP
E
2
PROM SPD (256 WORD X 8 BITS)
47K
CLOCK WIRING
CLOCK INPUT LOAD
CLK0 5 SDRAMS
CLK1 Termination
CLK2 4 SDRAMS +3.3pF Cap
CLK3 Termination
D4
DQM
I/O1–I/O8 CS
D5
DQM
I/O1–I/O8 CS
D6
DQM
I/O1–I/O8 CS
D7
DQM
I/O1–I/O8 CS
DQM
I/O1–I/O8 CS
D0
DQM
I/O1–I/O8 CS
D1
DQM
I/O1–I/O8 CS
D2
DQM
I/O1–I/O8 CS
D3
WE
WE
WE
10
CB0–7DQM
I/O1–I/O8 CS
WE
WE
WE
WE
WE
D8
4
V437316S04V Rev. 1.0 December 2001
MO SEL VITELIC
V437316S04V
Serial Presence Detect Information
A serial presence detect storage device -
E2PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintotheE
2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD-Table
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
0 Number of SPD bytes 128 80 80 80
1 Total bytes in Serial PD 256 08 08 08
2 Memory Type SDRAM 04 04 04
3 Number of Row Addresses (without BS bits) 12 0C 0C 0C
4 Number of Column Addresses (for x8
SDRAM) 10 0A 0A 0A
5 Number of DIMM Banks 1 01 01 01
6 Module Data Width 72 48 48 48
7 Module Data Width (continued) 0 00 00 00
8 Module Interface Levels LVTTL 01 01 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75 75 A0
10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 54 60
11 Dimm Config (Error Det/Corr.) ECC 02 02 02
12 Refresh Rate/Type Self-Refresh, 15.6µs80 80 80
13 SDRAM width, Primary x8 08 08 08
14 Error Checking SDRAM Data Width n/a / x8 08 08 08
15 Minimum Clock Delay from Back to Back
Random
Column Address
tccd =1CLK 01 01 01
16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F
17 Number of SDRAM Banks 4 04 04 04
18 Supported CAS Latencies CL = 3 06 06 06
19 CS Latencies CS Latency = 0 01 01 01
20 WE Latencies WL = 0 01 01 01
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E
23 Minimum Clock Cycle Time at CAS Latency
=2 Not Supported 75 A0 A0
24 Maximum Data Access Time from Clock for
CL = 2 Not Supported 54 60 60
25 MinimumClockCycleTimeatCL=1 NotSupported 00 00 00
26 Maximum Data Access Time from Clock at
CL = 1 Not Supported 00 00 00
27 Minimum Row Precharge Time 20 ns 0F 14 14
MO SEL VITELIC
V437316S04V
5
V437316S04V Rev. 1.0 December 2001
DC Characteristics
TA=0°Cto70°C; VSS =0V;V
DD,V
DDQ =3.3V±0.3V
28 Minimum Row Active to Row Active Delay
tRRD
15 ns 0E 0F 10
29 Minimum RAS to CAS Delay tRCD 20 ns 0F 14 14
30 Minimum RAS Pulse Width tRAS 45 ns 2A 2D 2D
31 Module Bank Density (Per Bank) 128 MByte 20 20 20
32 SDRAM Input Setup Time 1.5 ns 15 15 20
33 SDRAM Input Hold Time 0.8 ns 08 08 10
34 SDRAM Data Input Setup Time 1.5 ns 15 15 20
35 SDRAM Data Input Hold Time 0.8 ns 08 08 10
36-61 Superset Information (May be used in Fu-
ture) 00 00 00
62 SPD Revision Revision 2 02 02 02
63 Checksum for Bytes 0 - 62 EC 31 8F
64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 40 40
65-71 Manufacturer’s JEDEC ID Code (cont.) 00 00 00
72 Manufacturing Location
73-90 Module Part Number (ASCII) V437316S04V
91-92 PCB Identification Code
93 Assembly Manufacturing Date (Year)
94 Assembly Manufacturing Date (Week)
95-98 Assembly Serial Number
99-125 Reserved 00 00 00
126 Intel Specification for Frequency 64 64 64
127 Reserved 00 00 00
128+ Unused Storage Location 00 00 00
Symbol Parameter
Limit Values
UnitMin. Max.
VIH Input High Voltage 2.0 VCC+0.3 V
VIL Input Low Voltage –0.5 0.8 V
VOH Output High Voltage (IOUT =–2.0 mA) 2.4 —V
VOL Output Low Voltage (IOUT =2.0mA) —0.4 V
SPD-Table
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
6
V437316S04V Rev. 1.0 December 2001
MO SEL VITELIC
V437316S04V
Capacitance
TA=0°Cto70°C; VDD =3.3V± 0.3V, f = 1 MHz
Absolute Maximum Ratings
II(L) Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA
IO(L) Output leakage current
(DQ is disabled, 0V < VOUT <V
CC)–40 40 µA
Symbol Parameter
Limit Values
UnitMax. 16M x 72
CI1 Input Capacitance (A0 to A11, RAS,CAS,WE)65pF
CI2 Input Capacitance (CS0-CS3)40pF
CICL Input Capacitance (CLK0-CLK3) 40 pF
CI3 Input Capacitance (CKE0, CKE1) 55 pF
CI4 Input Capacitance (DQM0-DQM7) 20 pF
CIO Input/Output Capacitance (I/O1-I/064) 20 pF
CSC Input Capacitance (SCL, SA0-2) 8 pF
CSD Input/Output Capacitance (SA0-SA2) 10 pF
Parameter Max. Units
VoltageonVDDSupplyRelativetoV
SS -1 to 4.6 V
VoltageonInputRelativetoV
SS -1 to 4.6 V
Operating Temperature 0to+70 °C
Storage Temperature -55to125 °C
Power Dissipation 7.5 W
Operating Currents
TA=0°Cto70°C, VCC =3.3V±0.3V (Recommended operating conditions otherwise noted)
Symbol Parameter & Test Condition
Max.
Unit Note
-75PC/-
75 -10PC
ICC1 Operating Current
tRC =t
RCMIN.,t
RC =t
CKMIN.
Active-precharge command cycling,
without Burst Operation
1 bank operation 1800 1350 mA 7
Symbol Parameter
Limit Values
UnitMin. Max.
MO SEL VITELIC
V437316S04V
7
V437316S04V Rev. 1.0 December 2001
Notes:
1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
2. These parameter depend on output loading. Specified values are obtained with output open.
ICC2P Precharge Standby Current in Power Down Mode
CS =VIH,CKE≤VIL(max)
tCK =min. 14 14 mA 7
ICC2PS tCK = Infinity 9 9 mA 7
ICC2N Precharge Standby Current in Non-PowerDown Mode
CS =VIH,CKE≥VIL(max)
tCK = min. 400 315 mA
ICC2NS tCK = Infinity 45 45 mA
ICC3 No Operating Current
tCK =min,CS=V
IH(min)
bank ; active state ( 4 banks)
CKE ≥VIH(MIN.) 495 405 mA
ICC3P CKE ≥VIL(MAX.)
(Power down mode) 90 90 mA
ICC4 Burst Operating Current
tCK =min
Read/Write command cycling
990 810 mA 7,8
ICC5 Auto Refresh Current
tCK =min
Auto Refresh command cycling
2250 1890 mA 7
ICC6 Self Refresh Current
Self Refresh Mode, CKE=0.2V 14 14 mA
L-version 7.2 7.2 mA
AC Characteristics
TA=0°to 70°C; VSS =0V;V
CC =3.3V±0.3V, tT=1ns
# Symbol Parameter
Limit Values
Unit Note
-75PC -75 -10PC
Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
1t
CK Clock Cycle Time
CAS Latency = 3
CAS Latency = 2 7.5
7.5 –
–7.5
10 –
–10
10 –
–
s
ns
ns
2t
CK Clock Frequency
CAS Latency = 3
CAS Latency = 2 –
–133
133 –
–133
100 –
–100
100 MHz
MHz
3t
AC Access Time from Clock
CAS Latency = 3
CAS Latency = 2 –
_5.4
6–
_5.4
6–
_6
6ns
ns
2, 4
4t
CH Clock High Pulse Width 2.5 –2.5 –2.5 –ns
Operating Currents
TA=0°Cto70°C, VCC =3.3V±0.3V (Recommended operating conditions otherwise noted) (Continued)
Symbol Parameter & Test Condition
Max.
Unit Note
-75PC/-
75 -10PC
8
V437316S04V Rev. 1.0 December 2001
MO SEL VITELIC
V437316S04V
5t
CL Clock Low Pulse Width 2.5 –2.5 –2.5 –ns
6t
TTransition Tim 1 –1–1–ns
Setup and Hold Times
7t
IS Input Setup Time 1.5 –1.5 –1.5 –ns 5
8t
IH Input Hold Time 0.8 –0.8 –0.8 –ns 5
9t
CKS Input Setup Time 1.5 –1.5 –1.5 –ns 5
10 tCKH CKE Hold Time 0.8 –0.8 –0.8 –ns 5
11 tRSC Mode Register Set-up Time 15 –15 –15 –ns
12 tSB Power Down Mode Entry Time 0 7.5 0 7.5 0 7.5 ns
Common Parameters
13 tRCD Row to Column Delay Time 15 –20 –20 –ns 6
14 tRP Row Precharge Time 20 –20 –20 –ns 6
15 tRAS Row Active Time 42 100K 45 100K 45 100K ns 6
16 tRC Row Cycle Time 60 –70 –70 –ns 6
17 tRRD Activate(a) to Activate(b) Command
Period 14 –15 –20 –ns 6
18 tCCD CAS(a) to CAS(b) Command Period 1 –1–1–CLK
Refresh Cycle
19 tREF Refresh Period (4096 cycles) —64 —64 —64 ms
20 tSREX Self Refresh Exit Time 10 —10 —10 —ns
Read Cycle
21 tOH Data Out Hold Time 3 –3–3–ns 2
22 tLZ Data Out to Low Impedance Time 0 –0–0–ns
23 tHZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 7
24 tDQZ DQM Data Out Disable Latency 2 –2–2–CLK
Write Cycle
25 tWR Write Recovery Time 2 –2–1–CLK
26 tDQW DQM Write Mask Latency 0 –0–0–CLK
AC Characteristics
TA=0°to 70°C; VSS =0V;V
CC =3.3V±0.3V, tT= 1 ns (Continued)
# Symbol Parameter
Limit Values
Unit Note
-75PC -75 -10PC
Min. Max. Min. Max. Min. Max.
MO SEL VITELIC
V437316S04V
9
V437316S04V Rev. 1.0 December 2001
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. AC timing tests have VIL =0.4VandVIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tTis longer than 1 ns, a time (tT-1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up”the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11. tDAL is equivalent to tDPL +t
RP.
1.4V
1.4V
tSETUP tHOLD
tAC tAC
tLZ tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+1.4V
50 Ohm
2.4V
0.4V
tT
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
10
V437316S04V Rev. 1.0 December 2001
MO SEL VITELIC
V437316S04V
Package Diagram
SDRAM DIMM Module Package
V437316S04VTG-75-04
127.35
133.35
42.18
D
66.68
3.0
35.00
17.78
11011 4041 84
85 94 95 124 125 168
BA
6.35
2.26
RADIUS
1.27 + 0.10
Detail A
3.125
8.25 4.45
2.0
C
6.35
Detail B
3.125
2.0
1.0 + 0.5
1.27
Detail C
2.4 min.
0.2 ± 0.15
Tolerances: ± (0.13) unless otherwise specified.
(2.54 max)
All measurements in mm
1.27 ± 0.100
MO SEL VITELIC
V437316S04V
11
V437316S04V Rev. 1.0 December 2001
Label Information
CL= 3 or 2 (CLK)
tRCD= 3 or 2 (CLK)
tRP= 3 or 2 (CLK)
-XXXU
UNBUFFERED DIMM
PC133 54
JEDEC SPD Revision 2
2
V437316S04VXXX-XX 128MB CLX
PC133U-XXX-542-A
XXXX-XXXXXXX
Assembly in Taiwan
A
Gerber file Intel PC100 x8Based
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC100 or PC133
(refer to MVI datasheet)
tAC = 5.4 ns
CAS Latency
2=CL2
3=CL3
MO SEL VITELIC
WORLDWIDE OFFICES V437316S04V
© Copyright , MOSEL VITELIC Inc. Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC doesnot do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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