Page 1 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │www.psemi.com
RF1 RF2
RFC
CMOS
Control
Driver
ESD ESD
ESD
CTRL CTRL or V
DD
The PE42421 UltraCMOS® RF switch is designed to
cover a broad range of applications from 10 MHz
through 3000 MHz. This reflective switch integrates
on-board CMOS control logic with a low voltage
CMOS-compatible control interface, and can be
controlled using either single-pin or complementary
control inputs. Using a nominal +3-volt power supply
voltage, a typical input 1 dB compression point of
+33.5 dBm can be achieved.
The PE42421 SPDT RF switch is manufactured on
Peregrine’s UltraCMOS® process, a patented
variation of silicon-on-insulator (SOI) technology on
a sapphire substrate, offering the performance of
GaAs with the economy and integration of
conventional CMOS.
Product Specification
SPDT UltraCMOS®
10 MHz – 3.0 GHz RF Switch
Product Description
Figure 1. Functional Diagram
PE42421
Features
Single-pin or complementary CMOS
logic control inputs
Low insertion loss: 0.35 dB at
1000 MHz, 0.5 dB at 2000 MHz
Isolation of 30 dB at 1000 MHz, 20 dB
at 2000 MHz
Typical input 1 dB compression point
of +33.5 dBm
1.8V minimum power supply voltage
SC-70 package
Figure 2. Package
6-lead SC-70
71-0015-01
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 2 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │ UltraCMOS® RFIC Solutions
Notes: 1. Device linearity will begin to degrade below 10 MHz
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50Ω test set-up, measured with
1ns risetime pulses and 500 MHz bandwidth
3. A tuning capacitor must be added to the application board to optimize the insertion loss and return loss performance. See Figur e 6 for details
Table 1. Electrical Specifications @ +25°C, VDD = 3V (ZS = ZL = 50Ω )
Parameter Condition Minimum Typical Maximum Unit
Operation Frequency1 10 MHz 3000 MHz
Insertion Loss3 1000 MHz
2000 MHz 0.35
0.50 0.45
0.60 dB
dB
Isolation 1000 MHz
2000 MHz 29
19 30
20 dB
dB
Return Loss3 1000 MHz
2000 MHz 21
24 22
27 dB
dB
‘ON’ Switching Time 50% CTRL to 0.1 dB of final value, 1 GHz 1.50 us
‘OFF’ Switching Time 50% CTRL to 25 dB isolation, 1 GHz 1.50 us
Video Feedthrough2 15 mVpp
Input 1 dB Compression
1000 MHz @ 2.3 - 3.3V
1000 MHz @ 1.8 - 2.3V
2500 MHz @ 2.3 - 3.3V
2500 MHz @ 1.8 - 2.3V
31.5
29.5
28.5
28
33.5
30.5
30.5
29
dBm
Input IP3 1000 MHz, 20dBm input power 55 dBm
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 3 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │www.psemi.com
Table 2. Pin Descriptions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® de vice, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be take n to avoid exceeding the
specified rating.
Latch-Up Avoidance
Unlike conventional CMO S devices, UltraCMOS®
devices are immune to latch-up.
Figure 3. Pin Configuration (Top View)
Pin No. Pin Name Description
1 RF14 RF Port1
2 GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
3 RF24 RF Port2
4 CTRL Switch control input, CMOS logic level.
5 RFC4 RF Common
6 CTRL or VDD
This pin supports two interface options:
Single-pin control mode. A nominal 3-volt
supply connection is required.
Complementary-pin control mode. A com-
plementary CMOS control signal to CTRL
is supplied to this pin. Bypassing on this
pin is not required in this mode.
Table 4. Absolute Maximum Ratings
Notes: 5. To maintain optimum device performance, do not exceed Max PIN at
desired operating frequency (see Figure 4)
Symbol Parameter/Condition Min Max Unit
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any DC input -0.3 VDD+
0.3 V
TST Storage temperature range -65 150 °C
TOP Operating temperature
range -40 85 °C
PIN Input power (50 Ω) +345 dBm
VESD
ESD Voltage (HBM,
ML_STD 883 Method
3015.7) 2000 V
ESD Voltage (MM, JEDEC,
JESD22-A114-B) 100 V
Table 3. Operating Ranges
Parameter Min Typ Max Unit
VDD Power Supply Voltage 1.8 3.0 3.3 V
IDD Power Supply Current
(VDD = 3V, VCNTL = 3V) 9 20 µA
Control Voltage High 0.7x VDD V
Control Voltage Low 0.3x VDD V
Figure 4. Maximum Input Power
Exceeding ab solute maximum ratings may cau se
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range m aximum and absolute
maximum for extended p eriods may reduce reliability.
Moisture Sensitivity Level
The Moisture Sensitivity Le vel rating for the PE42421 in
the SC70 package is MSL1.
Note: 4. All RF pins must be DC blocked with an external series capacitor or
held at 0 VDC
Switching Frequency
The PE42421 has a maxim um 25 kHz switching rate.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 4 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │ UltraCMOS® RFIC Solutions
Control Voltages Signal Path
Pin 6 (VDD) = VDD
Pin 4 (CTRL) = High RFC to RF2
Pin 6 (VDD) = VDD
Pin 4 (CTRL) = Low RFC to RF1
Table 5. Single-pin Control Logic Truth Table
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages Signal Path
Pin 6 (CTRL or VDD) = Low
Pin 4 (CTRL) = High RFC to RF2
Pin 6 (CTRL or VDD) = High
Pin 4 (CTRL) = Low RFC to RF1
Control Logic Input
The PE42421 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection on pin
6 (VDD). This mode of operation reduces the
number of control lines required and simplifies the
switch control interface typically derived from a
CMOS Processor I/O port.
Complementary-pin control mode allows the
switch to operate using complementary control
pins CTRL and CTRL (pins 4 & 6), that can be
directly driven by +3-volt CMOS logic or a suitable
Processor I/O port. This enables the PE42421 to
be used as a potential alternate source for SPDT
RF switch products used in positive control
voltage mode and operating within the PE42421
operating limits.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 5 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │www.psemi.com
T-line Description
--
Model = CPWG
H=28mils
T=2.1mils
W=47mils
G=30mils
Er=4.4
SEEASSYNOTE2
SEEASSYNOTE2
1
2
J7
CNTL
1
J3
RF2
R1
1KOhm
R2
1KOhm
1
J5
N/
A
1
J4
N/A
1
J2
RF1
1
2
J6
CNTLX/VDD
2
GND 1
RF_1
3
RF_2
4CTRL
5RFC
6VDD
U1
PE42421/SC70-6
1
J1
RFC
12
C1
0.5pF
12
C2
0.5pF
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42421. The
RF common port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RF1 and RF2 are connected through 50Ω
transmission lines via SMA connectors J2 and J3,
respectively. A through 50Ω transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and εr of 4.4.
J6 and J7 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device VDD or CTRL input. J7-1 is connected
to the device CTRL input.
Figure 5. Evaluation Board Layouts
Figure 6. Evaluation Board Schematic
Peregrine Specification 102-0756-01
Peregrine Specification 101-0162-02
Notes: Add two 0.5 pF caps in series to be shunted on the J1 SMA input
Solder C1 side 1 to the RF tra ce close to the J1 pin
Solder C1 side 2 to C2 side 1
Solder C2 side 2 to ground
General Comments
Transmission lines connected to J1, J2, and J3 should have exactly the
same electrical length
The path from J2 to J3 including the distance through the part should
have the same length as J4 and J5 and be in parallel to J4 to J5
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 6 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │ UltraCMOS® RFIC Solutions
Typical Performance Data @ -40°C to 85°C (Unless Otherwise Noted)
Figure 7. Insertion Loss Figure 8. Isolation – Input to Output
Figure 9. Isolation – Output to Output Figure 10. Return Loss (Input)
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 7 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │www.psemi.com
Typical Performance Data @ VDD = 2.3V, T = 25°C
Figure 11. Insertion Loss Figure 12. Isolation – Input to Output
Figure 13. Isolation – Output to Output Figure 14. Return Loss (Input & Output)
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 8 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │ UltraCMOS® RFIC Solutions
Figure 15. Package Drawing
6-lead SC-70
2.10±0.05
1.25±0.10
1.30
0.65 0.225±0.075
2.10±0.10 0.90±0.10
0.05±0.05
Top View Side View
End View
A0.10 C
(2X)
C
0.10 C
0.05 C
SEATING PLANE
B
0.10 C
(2X)
Pin #1 Corner
Recommended Land Pattern
1.90
0.65
0.50 MIN
1.30 0.40 MIN
13
64
0.36±0.10
0.165±0.085
0.10 A B
ALL FEATURES
181-0013
Figure 16. Top Marking Specification
PPP
YWW
= Pin 1 Indicator
PPP = Part Number
YWW = Date Code
17-0021
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Specification
PE42421
Page 9 of 9
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0396-03 │www.psemi.com
Table 7. Ordering Information
Order Code Part Marking Description Package Shipping Method
EK42421-01 PE42421-EK PE42421 Evaluation Kit Evaluation Kit 1 / Box
PE42421SCAA-Z 421 PE42421 SPDT RF Switch Green 6-lead SC-70 3000 units / T&R
Figure 17. Tape and Reel Specifications
Pin 1
Tape Feed Direction
1
2
3 4
5
6
1
2
3 4
5
6
Device Orientation in Tape
Pin 1
Top of
Device
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The informatio n in this datasheet i s believed to b e reliable. Ho wever, Peregrin e assume s no liability for the us e
of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp.
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
