MM74HC244 - Fairchild Semiconductor

September 1983

Revised May 2005

MM74HC244 Octal 3-STATE Buffer

MM74HC244

Octal 3-STATE Buffer

General Descript ion

The MM74HC244 is a non-inverting buffer and has two

active low enables (1G and 2G); each enable indepen-

dently controls 4 buffers. This device does not have

Schmitt trigger inputs.

These 3-STATE buffers utilize advanced silicon-gate

CMOS technology and are general purpose high speed

non-inv erting b uffers. The y possess h igh dri ve cur rent ou t-

puts which ena bl e h igh sp ee d op eration even w he n dr ivi ng

large bus capacitances. These circuits achieve speeds

comparable to low power Schottky devices, while retaining

the advantage of CMOS cir cuitry, i.e., high noi se immu nity,

and low power consumption. All three devices have a

fanout of 15 LS-TTL equivalent inputs.

All inputs are protected from damage due to static dis-

charge by diodes to VCC and ground.

Features

■Typical propagation delay: 14 ns

■3-STATE outputs for connection to system buses

■Wide power supply range: 2–6V

■Low quiescen t supply cur ren t: 80

■Output current: 6 mA

Ordering Code:

Devices also available in Tape and R eel. Specif y by append ing the suffix let t er “X” to th e ordering co de.

Connection Diagram

Top View

Truth Table

HIGH Level

LOW Le vel

High Impedance

Order Number Package Number Package Description

MM74HC244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

1G 1A 1Y 2G 2A 2Y

LLLLLL

LHHLHH

HLZHLZ

HHZHHZ

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MM74HC244

Logic Diagram

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MM74HC244

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unl es s ot herwise s pecified all v olt ages are ref erenced t o ground.

Note 3: Power Dis sipation tem perature d erating — plastic “N” package:



12 mW/

C from 65

C to 85

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V

10% t he w ors t ca se outp ut v oltag es (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when

designing with this supply. Worst case VIH and VIL occur at VCC

5.5V an d 4. 5V res pectively. (The VIH value at 5. 5V is 3.85 V.) The worst cas e leak age cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the h i gher voltag e and so the 6 .0 V v alues sho uld be used.

Supply Voltage (VCC)



0.5 to



7.0V

DC Input Voltage (VIN)



1.5 to VCC



1.5V

DC Output Voltage (VOUT)



0.5 to VCC



0.5V

Clamp Diode Current (IIK, IOK)

20 mA

DC Output Current, per pin (IOUT)

35 mA

DC VCC or GND Current, per pin (ICC)

70 mA

Storage Temperature Range (TSTG)



C to



150

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 second s) 260

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operating Tempera ture R ange (TA)





Input Rise or Fall Times

(tr, tf) VCC

2.0V 1000 ns

VCC

4.5V 500 ns

VCC

6.0V 400 ns

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

VIH Minimum HI GH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HI GH Level VIN

VIH or VIL

Output Voltage |IOUT|

A 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN

VIH or VIL V

|IOUT|

6.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT|

7.8 mA 6.0V 5.7 5.4 5.34 5.2 V

VOL Maximum LOW Level VIN

VIH or VIL

Output Voltage |IOUT|

A 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN

VIH or VIL

|IOUT|

6.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT|

7.8 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maximum Input VIN

VCC or GND 6.0V

0.1

1.0

Current

IOZ Maximum 3-STATE VIN

VIH, or VIL 6.0V

0.5

Output Leakage VOUT

VCC or GND

Current G

VIH

ICC Maximum Quiescent VIN

VCC or GND 6.0V 8.0 80 160

Supply Current IOUT

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MM74HC244

AC Electrical Characteristi cs

VCC

5V, TA

C, tr

6 ns

AC Electrical Characteristi cs

VCC

2.0V-6.0V, CL

50 pF, tr

6 ns (unless otherwise specified)

Note 5: CPD determines the no load dynam ic pow er cons um ption, PD

CPD VCC2f



ICC VCC, and the no load dynam ic c urrent con sumpti on,

CPD VCCf



ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limit

tPHL, tPLH Maximum Propagation CL

45 pF 14 20 ns

Delay

tPZH, tPZL Maximum Enable Delay RL

1 k

17 28 ns

to Active Output CL

45 pF

tPHZ, tPLZ Maximum Disable Delay RL

1 k

15 25 ns

from Active Output CL

5 pF

Symbol Parameter Conditions VCC TA



40 to 85

C TA



55 to 125

CUnits

Typ Guar ant eed Lim i ts

tPHL, tPLH Maximum Propagation CL

50 pF 2.0V 58 115 145 171 ns

Delay CL

150 pF 2.0V 83 165 208 246 ns

50 pF 4.5V 14 23 29 34 ns

150 pF 4.5V 17 33 42 49 ns

50 pF 6.0V 10 20 25 29 ns

150 pF 6.0V 14 28 35 42 ns

tPZH, tPZL Maximum Output Enable RL

1 k

Time CL

50 pF 2.0V 75 150 189 224 ns

150 pF 2.0V 100 200 252 298 ns

50 pF 4.5V 15 30 38 45 ns

150 pF 4.5V 30 40 50 60 ns

50 pF 6.0V 13 26 32 38 ns

150 pF 6.0V 17 34 43 51 ns

tPHZ, tPLZ Maximum Output Disable RL

1 k

2.0V 75 150 189 224 ns

Time CL

50 pF 4.5V 15 30 38 45 ns

6.0V 13 26 32 38 ns

tTLH, tTHL Maximum Output 2.0V 60 75 90 ns

Rise and Fall Time 4.5V 12 15 18 ns

6.0V 10 13 15 ns

CPD Power Dissipation (per buffer)

Capacitance (Note 5) G

VIH 12 pF

VIL 50 pF

CIN Maximum Input 5 10 10 10 pF

Capacitance

COUT Maximum Output 10 20 20 20 pF

Capacitance

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MM74HC244

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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MM74HC244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide

Package Number M20D

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MM74HC244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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MM74HC244 Octal 3-STATE Buffer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.