PSB4860 (V4.1) - Infineon Technologies

ICs for Communications

Sophisticated Answering Machine with Echo Cancellation

SAM-EC

PSB 4860 Version 4.1

Data Sheet 2000-01-14

DS 1

For questions on technology, delivery and prices please contact the Infineon Technologies Offices

in Germany or the Infineon Technologies Companies and Representatives worldwide:

see our webpage at http://www.infineon.com

PSB 4860

Revision History: Current Version: 2000-01-14

Previous Version:

Page

(in previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56,

FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE,

ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,

SLICOFI® are registered trademarks of Infineon Technologies AG.

ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG.

Edition 2000-01-14

Published by Infineon Technologies AG,

TR,

Balanstraße 73,

81541 München

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for

applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales

office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice

you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with

the express written approval of the Infineon Technologies AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that

device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-

dangered.

PSB 4860

Data Sheet 3 2000-01-14

1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.4 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

1.5 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.6 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

1.6.1 Analog Featurephone with Digital Answering Machine . . . . . . . . . . . . . . .20

1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal . . . . . .22

1.6.3 DECT Basestation with Integrated Digital Answering Machine . . . . . . . . .23

1.7 Backward Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.1.1 Full Duplex Speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.1.2 Echo Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

2.1.3 Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.1.4 Line Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

2.1.5 DTMF Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

2.1.6 CNG Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.1.7 Alert Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.1.8 Universal Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.1.9 CPT Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.1.10 Caller ID Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.1.11 Caller ID Sender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.1.12 DTMF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.1.13 Speech Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.1.14 Speech Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

2.1.15 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

2.1.16 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

2.1.17 Universal Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

2.1.18 Automatic Gain Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

2.1.19 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

2.1.20 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

2.2 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.2.1 File Definition and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

2.2.2 User Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

2.2.3 High Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . .83

2.2.4 Low Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . . .95

2.2.5 Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

2.2.6 Special Notes on File Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

2.3 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

2.3.1 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

PSB 4860

Data Sheet 4 2000-01-14

2.3.2 SPS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

2.3.3 Reset and Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

2.3.4 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

2.3.5 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

2.3.6 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

2.3.7 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2.3.8 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

2.3.9 Clock Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

2.3.10 AFE Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

2.3.11 Restrictions and Mutual Dependencies of Modules . . . . . . . . . . . . . . . .106

2.3.12 Emergency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

2.4 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

2.4.1 IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

2.4.2 SSDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

2.4.3 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

2.4.4 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

2.4.5 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

2.4.6 Auxiliary Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

3 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

3.1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

3.2 Hardware Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

3.3 Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

3.3.1 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

3.3.2 Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

4.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

PSB 4860

Data Sheet 5 2000-01-14

Figure 1: Pin Configuration of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2: Logic Symbol of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3: Block Diagram of PSB 4860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4: Analog Full Duplex Speakerphone with Digital Answering Machine . . . . 20

Figure 5: Stand-Alone Answering Machine with Data Access via SCI . . . . . . . . . . 21

Figure 6: Featurephone with Answering Machine for ISDN Terminal . . . . . . . . . . . 22

Figure 7: DECT Basestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8: Functional Units - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9: Functional Units - Recording a Phone Conversation . . . . . . . . . . . . . . . . 27

Figure 10: Functional Units - Simultaneous Internal and External Call . . . . . . . . . . . 28

Figure 11: Speakerphone - Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12: Speakerphone - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13: Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14: Echo Cancellation Unit - Typical Room Impulse Response . . . . . . . . . . . 31

Figure 15: Echo Suppression Unit - States of Operation. . . . . . . . . . . . . . . . . . . . . . 32

Figure 16: Echo Suppression Unit - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17: Speech Detector - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18: Speech Comparator - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 19: Speech Comparator - Acoustic Echoes . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 20: Speech Comparator - Interdependence of Parameters . . . . . . . . . . . . . . 39

Figure 21: Echo Suppression Unit - Automatic Gain Control. . . . . . . . . . . . . . . . . . . 42

Figure 22: Line Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . 45

Figure 23: Line Echo Cancellation Unit - Superior Mode with Shadow FIR . . . . . . . 46

Figure 24: DTMF Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 25: CNG Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 26: Alert Tone Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 27: Universal Tone Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 28: CPT Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 29: CPT Detector - Cooked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 30: Caller ID Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 31: Caller ID Sender - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 32: DTMF Generator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 33: Speech Coder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 34: VOX Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 35: Speech Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 36: Analog Front End Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . 69

Figure 37: Digital Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 38: Universal Attenuator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 39: Automatic Gain Control Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . 73

Figure 40: Equalizer - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 41: Peak Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 42: Memory Management - Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 43: Memory Management - Structure of Message Directory . . . . . . . . . . . . . 79

PSB 4860

Data Sheet 6 2000-01-14

Figure 44: Memory Management - Structure of Voice Prompt Directory. . . . . . . . . . 80

Figure 45: Audio File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 46: Binary File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 47: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 48: Operation Modes - State Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 49: IOM®-2 Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 50: IOM®-2 Interface - Frame Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 51: IOM®-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 52: IOM®-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 53: IOM®-2 Interface - Channel Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 54: SSDI Interface - Transmitter Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 55: SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 56: SSDI Interface - Receiver Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 57: Analog Front End Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . 117

Figure 58: Analog Front End Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 59: Analog Front End Interface - Data Transfer . . . . . . . . . . . . . . . . . . . . . . 118

Figure 60: Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 61: Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 62: Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 63: Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 64: Configuration Register Write Access or Register Read Command . . . . 122

Figure 65: ARAM/DRAM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . 127

Figure 66: ARAM/DRAM Interface - Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . 128

Figure 67: ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . 129

Figure 68: ARAM/DRAM Interface - Refresh Cycle Timing. . . . . . . . . . . . . . . . . . . 129

Figure 69: EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 70: EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 71: Parallel Flash Memory Interface - Connection Diagram. . . . . . . . . . . . . 131

Figure 72: Parallel Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . 132

Figure 73: Parallel Flash Memory Interface - Command Write . . . . . . . . . . . . . . . . 133

Figure 74: Parallel Flash Memory Interface - Address Write. . . . . . . . . . . . . . . . . . 133

Figure 75: Parallel Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . 134

Figure 76: Parallel Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . 134

Figure 77: Serial Flash - Connection to Single TC 58 A 040 F . . . . . . . . . . . . . . . . 135

Figure 78: Serial Flash - Connection to Single AT 45 DB 041 . . . . . . . . . . . . . . . . 135

Figure 79: Serial Flash - Connection to Multiple TC 58 A 040 F . . . . . . . . . . . . . . . 136

Figure 80: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 81: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 82: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 83: SSDI/IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . 306

Figure 84: SSDI/IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . 306

Figure 85: SSDI Interface - Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 86: Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

PSB 4860

Data Sheet 7 2000-01-14

Figure 87: Analog Front End Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 88: Memory Interface - DRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . 311

Figure 89: Memory Interface - DRAM Write Access . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 90: Memory Interface - DRAM Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 91: Memory Interface - EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 92: Memory Interface - Samsung Command Write . . . . . . . . . . . . . . . . . . . 315

Figure 93: Memory Interface - Samsung Address Write . . . . . . . . . . . . . . . . . . . . . 316

Figure 94: Memory Interface - Samsung Data Write . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 95: Memory Interface - Samsung Data Read . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 96: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 97: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

PSB 4860

Data Sheet 8 2000-01-14

Table 1: Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 2: Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 3: Echo Cancellation Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 4: Speech Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 5: Speech Comparator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 6: Attenuation Control Unit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 7: SPS Output Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 8: Automatic Gain Control Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 9: Fixed Gain Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 10: Speakerphone Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 11: Selection of the Mode of the Line Echo Canceller . . . . . . . . . . . . . . . . . . .47

Table 12: Line Echo Cancellation Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 13: DTMF Detector Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 14: DTMF Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 15: DTMF Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 16: CNG Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 17: CNG Detector Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 18: Alert Tone Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 19: Alert Tone Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 20: Universal Tone Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 21: Universal Tone Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 22: CPT Detector Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 23: CPT Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 24: Caller ID Decoder Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 25: Caller ID Decoder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 26: Caller ID Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 27: Caller ID Sender Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 28: Caller ID Sender Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 29: Caller ID Sender Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 30: DTMF Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 31: Speech Coder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 32: Speech Coder Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 33: Speech Coder - Gap Detector Control Registers . . . . . . . . . . . . . . . . . . . .62

Table 34: VOX Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 35: Speech Coder - Data Transfer via SCI. . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 36: Speech Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 37: Speech Decoder - Data Transfer via SCI . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 38: Analog Front End Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 39: Digital Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 40: Universal Attenuator Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 41: Automatic Gain Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 42: Equalizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 43: Peak Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

PSB 4860

Data Sheet 9 2000-01-14

Table 44: Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 45: Memory Management Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 46: Memory Management Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 47: Initialize Memory Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 48: Initialize Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 49: Initialize Memory Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 50: Activate Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 51: Activate Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 52: Activate Memory Result Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 53: Read Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 54: Read Data Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 55: Open File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 56: Open Next Free File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 57: Open Next Free File Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 58: Seek Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 59: Cut File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 60: Delete Multiple Files Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 61: Compress File Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table 62: Memory Status Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 63: Memory Status Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 64: Garbage Collection Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 65: Write File Descriptor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 66: Read File Descriptor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 67: Access File Descriptor Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 68: Read Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Table 69: Read Data Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Table 70: Write Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 71: Set Address Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 72: DMA Read Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Table 73: DMA Write Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 74: Block Erase Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Table 75: Execution Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 76: Real Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Table 77: SPS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Table 78: Power Down Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Table 79: Interrupt Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table 80: Hardware Configuration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 81: Frame Synchronization Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 82: Dependencies of Modules - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 83: Dependencies of Modules - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 84: File Command Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 85: Module Weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 86: Command Words for Emergency Mode Data Transfer . . . . . . . . . . . . . .110

PSB 4860

Data Sheet 10 2000-01-14

Table 87: SSDI vs. IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 88: IOM®-2 Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Table 89: SSDI Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Table 90: Control of ALS Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 91: Analog Front End Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 92: Analog Front End Interface Clock Cycles. . . . . . . . . . . . . . . . . . . . . . . . .118

Table 93: Command Words for Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 94: Address Field W for Configuration Register Write . . . . . . . . . . . . . . . . . .122

Table 95: Address Field R for Configuration Register Read . . . . . . . . . . . . . . . . . .123

Table 96: Supported Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Table 97: Address Line Usage (ARAM/DRAM Mode) . . . . . . . . . . . . . . . . . . . . . . .127

Table 98: Refresh Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Table 99: Address Line Usage (Samsung Mode). . . . . . . . . . . . . . . . . . . . . . . . . . .131

Table 100: Flash Memory Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 101: Pin Functions for Serial Flash Interface. . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 102: Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 103: Auxiliary Parallel Port Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 104: Static Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 105: Multiplex Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 106: Interrupt Mask Definition for Parallel Port . . . . . . . . . . . . . . . . . . . . . . . .139

Table 107: Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 108: Status Register Update Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

Semiconductor Group 11 11.99

PSB 4860

1Overview

General

Combined with an analog front end the provides a solution for embedded or stand alone

answering machine applications. Together with a standard microcontroller for analog

telephones these two chips form the core of a featurephone with full duplex

speakerphone and answering machine capabilities.

The chip features recording by DigiTape™, a family of high performance algorithms.

Messages recorded with DigiTape™ can be played back with variable speed without

pitch alteration. Messages recorded with a higher bitrate can be converted into

messages with a lower bitrate arbitrarily. The PSB 4860 Version 4.1 supports three

members of DigiTape™: 10.3 kbit/s, 5.6 kbit/s and 3.3 kbit/s.

Furthermore the , Version 4.1 features a full duplex speakerphone, a caller ID decoder,

DTMF recognition and generation and call progress tone detection. A programmable

band-pass can be used to detect special tones besides the standard call progress tones.

The frequency response of cheap microphones or loudspeakers can be corrected by a

programmable equalizer.

Messages and user data can be stored in ARAM/DRAM or flash memory which can be

directly connected to the . The also supports a voice prompt EPROM for fixed

announcements.

The provides an IOM®-2 compatible interface with up to three channels for speech data.

Alternatively to the IOM®-2 compatible interface the supports a simple serial data

interface (SSDI) with separate strobe signals for each direction (linear PCM data, one

channel).

A separate interface is used for a glueless connection to the dual channel codec SAM-

AFE (PSB 4851).

The chip is programmed by a simple four wire serial control interface and can inform the

microcontroller of new events by an interrupt signal. For data retention the supports a

power down mode where only the real time clock and the memory refresh (in case of

ARAM/DRAM) are operational.

The supports interface pins to +5 V input levels.

P-MQFP-80-1

Data Sheet 12 2000-01-14

Sophisticated Answering Machine with Echo

Cancellation

SAM

PSB 4860

Version 4.1 CMOS

Type Package

PSB 4860 P-MQFP-80-1

1.1 Features

Digital Functions

•High performance recording by DigiTape™

•Selectable compression rate (3.3, 5.6 or 10.3 kbit/s)

•Variable playback speed

•Support for DRAM/ARAM or Flash Memory (5V,

3.3V)

•x1, x4 and x8 ARAM/DRAM supported

•Optional voice prompt EPROM

•Up to four serial or parallel flash devices supported (Atmel, Toshiba, Samsung)

•Audio data transfer via serial control interface (SCI) possible

•Full duplex speakerphone by acoustic echo cancellation

•DTMF generation and detection

•Call progress tone detection

•Caller ID decoder

•Caller ID sender

•Direct memory access

•Real time clock

•Equalizer for transducer/microphone frequency response correction

•Automatic gain control

•Automatic timestamp

•Universal tone detector

•Three data channels (IOM®-2 compatible interface)

•Auxiliary parallel port with optional interrupt generation

•Ultra low power refresh mode

•Emergency shut-down (fast parameter saving into flash device)

•Backward compatible with PSB 4860 V2.1 (hardware and software)

PSB 4860

Data Sheet 13 2000-01-14

1.2 Pin Configuration

(top view)

Figure 1 Pin Configuration of

110 20

4160 50

DDA

XTAL

OSC

SSA

SCLK

SDR

AFEDD

AFEDU

VDD

VSS

AFEFS

AFECLK

FSC

DU/DX

DD/DR

DXST

DRST

VDD

VSS

DCL

W/FWE

FRDY

VPRD/FCLE

RAS/FOE

CAS1/FCS

SPS0

SPS1

VDD

VSS

/SDI

/SDO

/CS

VDD

MA4

MA5

MA6

VDD

MA8

VSS

MA15

VSS

MA7

MA9

MA10

VDD

MA12

MA13

MA14

VSS

MA11

VDDP

RST

CLK

/SCLK

DDP

INT

SDX

CAS0/ALE

SAM-EC

PSB 4860

Data Sheet 14 2000-01-14

1.3 Pin Definitions and Functions

Table 1 Pin Definitions and Functions

Pin No.

P-MQFP-80

Symbol Dir.1) Reset Function

7, 15, 21,

29, 39, 49,

58, 61, 67,

VDD -- Power supply (3.0 V - 3.6 V)

Power supply for logic.

1VDDA -- Power supply (3.0 V - 3.6 V)

Power supply for clock generator.

4VSSA -- Power supply (0 V)

Ground for clock generator.

9, 16, 22,

30, 40, 48,

57, 59, 60,

78, 66, 72

VSS -- Power supply (0 V)

Ground for logic and interface.

17 AFEFS O L Analog Frontend Frame Sync:

8 kHz frame synchronization signal for the

communication with the analog front end

(PSB 4851).

18 AFECLK O L Analog Frontend Clock:

Clock signal for the analog front end

(6.912 MHz).

19 AFEDD O L Analog Frontend Data Downstream:

Data output to the analog frontend.

20 AFEDU I - Analog Frontend Data Upstream:

Data input from the analog frontend.

79 RST I - Reset:

Active high reset signal.

23 FSC I - Data Frame Synchronization:

8 kHz frame synchronization signal (IOM®-2

and SSDI mode).

24 DCL I - Data Clock:

Data Clock of the serial data of the IOM®-2

compatible and SSDI interface.

PSB 4860

Data Sheet 15 2000-01-14

26 DD/DR I/OD

-IOM®-2 Compatible Mode:

Receive data from IOM®-2 controlling device.

SSDI Mode:

Receive data of the strobed serial data

interface.

25 DU/DX I/OD

-IOM®-2 Compatible Mode:

Transmit data to IOM®-2 controlling device.

SSDI Mode:

Transmit data of the strobed serial data

interface.

27 DXST O L DX Strobe:

Strobe for DX in SSDI interface mode.

28 DRST I - DR Strobe:

Strobe for DR in SSDI interface mode.

14 CS I- Chip Select:

Select signal of the serial control interface

(SCI).

11 SCLK I - Serial Clock:

Clock signal of the serial control interface

(SCI).

13 SDR I - Serial Data Receive:

Data input of the serial control interface (SCI).

12 SDX O/

HSerial Data Transmit:

Data Output of the serial control interface

(SCI).

10 INT O/

HInterrupt

New status available.

Table 1 Pin Definitions and Functions

PSB 4860
Data Sheet  16 2000-01-14
 
52
53
54
55
62
63
64
65
68
69
70
71
74
75
76
77
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
L2)
Memory Address 0-15:
Multiplexed address outputs for ARAM, DRAM 
access.
Non-multiplexed address outputs for voice 
prompt EPROM.
Auxiliary Parallel Port:
General purpose I/O.
42
43
44
45
46
47
50
51
MD0/
SCLK
MD1/SDI
MD2/SDO
MD3
MD4/CS0
MD5/CS1
MD6/CS2
MD7/CS3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
ARAM/DRAM or Samsung Flash:
Memory data bus.
Serial Flash Memory (Toshiba, Atmel):
Serial interface signals and predecoded chip 
select lines.
35
36
CAS0/ALE
CAS1/
FCS
O
O
H3) ARAM, DRAM:
Column address strobe for memory bank 0 
or 1.
Flash Memory:
Address Latch Enable for address lines A16-
A23.
Chip select signal for Flash Memory
34 RAS/FOE OH
3) ARAM, DRAM:
Row address strobe for both memory banks.
Flash Memory:
Output enable signal for Flash Memory.
Table 1 Pin Definitions and Functions

PSB 4860

Data Sheet 17 2000-01-14

33 VPRD/

FCLE

3) ARAM, DRAM:

Read signal for voice prompt EPROM.

Flash Memory:

Command latch enable for Flash Memory.

32 W/FWE OH

3) ARAM, DRAM:

Write signal for all memory banks.

Flash Memory:

Write signal for Flash Memory.

31 FRDY I - Flash Memory Ready

Input for Ready/Busy signal of Flash Memory

OSC1

OSC2

Auxiliary Oscillator:

Oscillator loop for 32.768 kHz crystal.

8CLKI-Alternative AFECLK Source

13,824 MHz

XTAL1

XTAL2

Oscillator:

XTAL1: External clock or input of oscillator

loop.

XTAL2: output of oscillator loop for crystal.

SPS0

SPS1

Multipurpose Outputs:

General purpose, speakerphone, address

lines or status

56 RO O - Reserved Output

Must be left open.

41, 80 NC - - Not Connected

1) I = Input

O = Output

OD = Open Drain

2) These lines are driven low with 102 µA (typical) until the mode (address lines or auxiliary port) is defined.

3) These lines are driven high with 100 µA (typical) during reset.

Table 1 Pin Definitions and Functions

PSB 4860

Data Sheet 18 2000-01-14

1.4 Logic Symbol

Figure 2 Logic Symbol of

DU/DX

DD/DR

DCL

FSC

SDX

SDR

SCLK

IOM®-2

SCI

AFECLK

AFEFS

AFEDU

AFEDD

PSB

MA0-MA15 MD0-MD7

CAS0/

ALE

CAS1/

FCS FOE

RAS/ VPRD/

FCLE

FWE

Memory

VDDA

VDD

VSS

OSC2

OSC1XTAL1XTAL2

RST

SSDI4851

INT

FRDY

DXST

DRST

CLK

PSB 4860

Data Sheet 19 2000-01-14

1.5 Functional Block Diagram

Figure 3 Block Diagram of

DU/DX

DD/DR

DCL

FSC

SDX

SDR

SCLK

AFECLK

AFEFS

AFEDU

AFEDD

MA0-MA15 MD0-MD7CAS0/

ALE

CAS1/

FCS FOE

RAS/ VPRD/

FCLE

FWE

OSC2

OSC1XTAL1XTAL2

RST

DSP

Memory Interface

Reset and Timing Unit

Data

Interface

Control

Interface

Analog

Front End

Interface

INT

FRDY

DXST

DRST

PSB 4860

Data Sheet 20 2000-01-14

1.6 System Integration

The combined with an analog front end (PSB 4851) can be used in a variety of

applications. This combination offers outstanding features like full duplex speakerphone

and emergency operation. Some applications are given in the following sections.

1.6.1 Analog Featurephone with Digital Answering Machine

Figure 4 shows an example of an analog telephone system. The telephone can operate

during power failure by line powering. In this case only the handset and ringer circuit are

active. All other parts of the chipset are shut down leaving enough power for the external

microcontroller to perform basic tasks like keyboard monitoring.

For answering machine operation the voice data can be stored in a Flash memory

devices. In addition, voice prompts can be stored in the Flash as well. Alternatively, An

ARAM or DRAM can be used to store the voice data. Then, the voice prompts can be

stored EPROM which can be connected to the /PSB 4851 additionally. The

microcontroller can use the memory attached to the /PSB 4851 to store and retrieve

binary data.

Figure 4 Analog Full Duplex Speakerphone with Digital Answering Machine

Flash Memory

Microcontroller

077-3445

line

tip/

ring

PSB 4851

SCI

PSB 4860

Data Sheet 21 2000-01-14

The PSB 4860 does not need to be directly connected to a Flash or DRAM but can use

the SCI interface to store and get its data. An example is shown in Figure 5.

Figure 5 Stand-Alone Answering Machine with Data Access via SCI

Flash Memory

Microcontroller

077-3445

line

tip/

ring

PSB 4851

SCI

PSB 4860

Data Sheet 22 2000-01-14

1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal

Figure 6 shows an ISDN featurephone. All voice data is transferred by the IOM®-2

compatible interface. The is programmed by the SCI interface. The microcontroller can

access the memory attached to the . This is useful for storing system parameters or

phonebook entries.

Figure 6 Featurephone with Answering Machine for ISDN Terminal

Flash PSB 4860

Microcontroller

077-3445

IOM®-2

S0-BUS

Power Controller

PEB 2023

PSB 21381/2

SAM-EC Scout-S

PSB 4860

Data Sheet 23 2000-01-14

1.6.3 DECT Basestation with Integrated Digital Answering Machine

Figure 7 shows a DECT basestation based on the /PSB 4851 chipset. In this application

it is possible to service both an external call and an internal call at the same time. For

programming the serial control interface (SCI) is used while voice data is transferred via

the IOM®-2 compatible interface (SSDI/IOM®-2).

Figure 7 DECT Basestation

Flash Memory

Microcontroller

077-3445

Antenna

SSDI/IOM®-2

SCI

Burstmode

Controller

DECT

line

tip/

ring

PSB 4851

PSB 4860

Data Sheet 24 2000-01-14

1.7 Backward Compatibility

The PSB 4860 Version 4.1 is backwards compatible with the PSB 4860 V2.1 and V3.1

with respect to:

•Pin Configuration

•Supply Voltage

•Signal Levels

•Start-up Sequence after Reset

•Register Definition1)

All of the additional features of the PSB 4860 Version 4.1 are enabled by previously

unused bits of the Hardware Configuration Registers, the Read/Write Registers or

reserved command opcodes. Therefore the PSB 4860 Version 4.1 can be used as a

drop-in replacement for the PSB 4860 V3.1 if the following checklist is observed:

1. Update version register inquiry (if present) for new version

2. Ensure no invalid (for V2.1 or V3.1) commands, registers or programming values are

used

The PSB 4860 Version 4.1 can be used as a drop-in replacement for the PSB 4860 V2.1

if the following is taken care of additionally:

1. Ensure no low level MMU command is used in application

2. Use voice prompt tool (formatter) for Version 4.1 (e.g. SPROMPT, APROMPT,

TPROMPT)

3. Read/Write Data accesses are not used to clear an interrupt

4. DTMF receiver has different handling of DTC bit and expects slightly differnt timing of

the tones

5. An improved oscillator makes new start-up tests necessary

Furthermore, there are a few changes which should have no impact on backwards

compatibility:

1. The status bits are updated faster

2. The DRAM refresh starts as soon as register CCTL is written (ARAM/DRAM specified)

3. The bit EIE in the file command register FCMD does not exist any more. The value at

this bit position is ignored. This bit is not needed any more as the PSB 4860 V3.1 and

V4.1 executes file commands as soon as possible anyway.

Note: If application of V2.1 uses low level MMU commands (e.g. for in-system reloading

of voice prompts) then this code must be changed to work properly for V4.1.

1) Exceptions are: SATT2:DS, SAGX2:SPEEDH and SAGR2:SPEEDH

PSB 4860

Data Sheet 25 2000-01-14

2 Functional Description

Functional Units

The contains several functional units that can be combined with almost no restrictions

to perform a given task. Figure 8 gives an overview of the important functional units.

Figure 8 Functional Units - Overview

Each unit has one or more signal inputs (denoted by I). Most units have at least one

signal output (denoted by S). Any input I can be connected to any signal output S. In

addition to the signals shown in figure 8 there is also the signal S0 (silence), which is

DTMF

Generator

DTMF

Detector

Speech

Coder

Speaker-

phone

CID

Decoder

Speech

Decoder

CPT/UTD

Detector

line

micro-

loud-

SSDI/IOM®-2 IOM®-2

S5S23

S11

S12

S10

S13

S24

signal summation: signal sources:

S1,...,S24

out

speaker

phone

line side

acoustic side

Memory

SCI

I1I1

Channel 3Channel 1

I3I4

I1I2

I1I2I3I1I2I3

I1I2

Alert Tone

Detector

CNG

Detector

I1I1

Universal

Attenuator

S14

Line Echo

Canceller

I1I2

S15

AGC

I1I2

S17

Equalizer

S18

S16

IOM®-2

Channel 2

I1I2I3

CID Sender

S22

Peak

Detector

PSB 4860

Data Sheet 26 2000-01-14

useful at signal summation points. Table 2 lists the available signals within the according

to their reference points.

Table 2 Signal Summary

Signal Description

S0Silence

S1Analog line input (channel 1 of PSB 4851 interface)

S2Analog line output (channel 1 of PSB 4851 interface)

S3Microphone input (channel 2 of PSB 4851 interface)

S4Loudspeaker/Handset output (channel 2 of PSB 4851 interface)

S5Serial interface input, channel 1

S6Serial interface output, channel 1

S7Serial interface input, channel 2

S8Serial interface output, channel 2

S9DTMF generator output

S10 DTMF generator auxiliary output

S11 Speakerphone output (acoustic side)

S12 Speakerphone output (line side)

S13 Speech decoder output

S14 Universal attenuator output

S15 Line echo canceller output

S16 Automatic gain control output (after gain stage)

S17 Automatic gain control output (before gain stage)

S18 Equalizer output

S22 Caller ID sender output

S23 Serial interface input, channel 3

S24 Serial interface output, channel 3

PSB 4860

Data Sheet 27 2000-01-14

The following figures show the connections for two typical states during operation. Units

that are not needed are not shown. Inputs that are not needed are connected to S0 which

provides silence (denoted by 0). In figure 9 a hands-free phone conversation is currently

in progress. The speech coder is used to record the signals of both parties. The alert tone

detector is used to detect an alerting tone of an off-hook caller id request while the CID

decoder decodes the actual data transmitted in this case.

Figure 9 Functional Units - Recording a Phone Conversation

Alert Tone

Detector

Speech

coder

Speaker-

phone

CID

decoder

Line Echo

Canceller

line

micro-

loud-

out

speaker

phone

line side

acoustic side

Memory

SCI

AGC

PSB 4860

Data Sheet 28 2000-01-14

In figure 10 a phone conversation using the speakerphone is in progress. One party is

using the base station of a DECT system while the other party is using a mobile handset.

At the same time an external call is serviced by the answering machine. In the current

state a message (recorded or outgoing) is being played back. In this case the DTMF

detector is used to detect signals for remote access while the CPT detector is used to

determine the end of the external call.

Figure 10 Functional Units - Simultaneous Internal and External Call

Speaker-

phone

Speech

decoder

line

micro-

loud-

SSDI/IOM®-2

out

speaker

phone

line side

acoustic side

Memory

SCI

Channel 1

DTMF

Detector

CPT

decoder

Line Echo

Canceller

Equalizer

PSB 4860

Data Sheet 29 2000-01-14

2.1 Functional Units

In this section the functional units of the are described in detail. The functional units can

be individually enabled or disabled.

2.1.1 Full Duplex Speakerphone

The speakerphone unit (figure 11) is attached to four signals (microphone, loudspeaker,

line out and line in). The two input signals (microphone, line in) are preceded by signal

summation points.

Figure 11 Speakerphone - Signal Connections

Internally, this unit can be divided into an echo cancellation unit and an echo suppression

unit (figure 12). The echo cancellation unit provides the attenuation Gc while the echo

suppression unit provides the attenuation Gs. The total attenuation ATT of the

speakerphone is therefore ATT=GC+Gs.

Figure 12 Speakerphone - Block Diagram

The echo cancellation unit estimates that part of the signal at the microphone that

originates from the loudspeaker. This part is then subtracted from the signal at the

microphone. This technique allows a full-duplex speakerphone.

Speakerphone

S11

S12

microphone

loudspeaker

line out

line in

Echo

Cancellation

line outmicrophone

loudspeaker line in

Echo

Suppression

GcGS

PSB 4860

Data Sheet 30 2000-01-14

The echo suppression unit attenuates the receive or transmit path dependent on what

path is active. Without the echo cancellation unit and by using a high attenuation of the

echo suppression unit, the echo suppression unit provides a half-duplex speakerphone.

If the echo cancellation unit is active but cannot provide all of the required attenuation

itself, the echo suppression unit can be used to provide additional attenuation.

The echo cancellation must be disabled during recording or playback of speech data but

the echo suppression unit can run simultenously. This allows half-duplex speakerphone

operation even when recording or playback is on-going.

2.1.2 Echo Cancellation

A simplified block diagram of the echo cancellation unit is shown in figure 13.

Figure 13 Echo Cancellation Unit - Block Diagram

The echo cancellation unit consists of a finite impulse response filter (FIR) that models

the expected acoustic echo, an NLMS based adaptation unit and a control unit. The

expected echo is subtracted from the actual input signal of the microphone. If the model

is exact and the echo does not exceed the length of the filter then the echo can be

cancelled completely. However, even if this ideal state can be achieved for one moment

the acoustic echo usually changes over time. Therefore the NLMS unit continuously

adapts the coefficients of the FIR filter. This adaptation process is steered by the control

unit. As an example, the adaptation is disabled as long as double talk is detected by the

control unit. Furthermore the control unit informs the echo suppression unit about the

achieved echo return loss.

Table 3 shows the registers associated with the echo cancellation unit.

microphone

loudspeaker

FIR

Filter

NLMSControl

line out

line in

PSB 4860

Data Sheet 31 2000-01-14

The length of the FIR filter can be varied from 127 to 511 taps (15.875ms to 63.875ms).

The taps are grouped into blocks. Each block contains 64 taps.

The performance of the FIR filter can be enhanced by prescaling some or all coefficients

of the FIR filter. Prescaling a coefficient means the coefficient gets multiplied by a

constant. The advantage of prescaling is an enhanced precision and consequently an

enhanced echo cancellation. The disadvantage is a reduced echo cancellation

performance if the signal exceeds the maximal coefficient value. More precisely, if a

coefficient at tap Ti is scaled by a factor Ci then the level of the echo (room impulse

response) must not exceed Max/Ci (Max: Maximum PCM value). Figure 14 shows an

example of a typical room impulse response.

Figure 14 Echo Cancellation Unit - Typical Room Impulse Response

In this example, the echo never exceeds 0.5 of the maximum value. Furthermore after

time t0.25 the echo never exceeds 0.25 of the maximum value. Therefore all coefficients

can be scaled by a factor of 2 and all coefficients for taps corresponding to times after

t0.25 can be scaled by a factor of 4.

The echo cancellation unit provides three parameters for scaling coefficients. The first

parameter GS determines a factor Ci=2GS for all coefficients. The second parameter FB

determines the first block, for which an additional parameter PS contributes to the factor

Ci=2GS+PS.

This feature can be used for different default settings like large or small rooms.

Table 3 Echo Cancellation Unit Registers

SAELEN 9 LEN Length of FIR filter

SAEATT 15 ATT Attenuation reduction during double-talk

SAEGS 3 GS Global scale (all blocks)

SAEPS1 3 PS Partial scale (for blocks >= SAEPS2:FB)

SAEPS2 3 FB First block affected by partial scale

0.5

0.25

t0.25

PSB 4860

Data Sheet 32 2000-01-14

2.1.3 Echo Suppression

The echo suppression unit can be in one of three states:

•transmit state

•receive state

•idle state

In transmit state the microphone signal drives the line output while the line input is

attenuated. In receive state the loudspeaker signal is driven by the line input while the

microphone signal is attenuated. In idle state both signal paths are active with evenly

distributed attenuation. It can be prevendted that the echo suppression unit goes into the

idle state

Figure 15 Echo Suppression Unit - States of Operation

line out

line in

microphone

loudspeaker

idle state

line out

line in

microphone

loudspeaker

receive state

line out

line in

microphone

loudspeaker

transmit state

PSB 4860

Data Sheet 33 2000-01-14

Figure 16 shows the signal flow graph of the echo suppression unit in more detail.

Figure 16 Echo Suppression Unit - Signal Flow Graph

The Attenuation Control performs the switching between the three possible states by

using the attenuation stages GHX and GHR. Actually, state switching is controlled by the

speech comparators SCAS and SCLS and by the speech detectors SDX and SDR. The

gain control units AGCX, AGCR, LGAX, and LGAR are used to achieve proper signal

levels for each state.

All blocks are programmable. Thus, the telephone set can be optimized and adjusted to

the particular geometrical and acoustical environment. The following sections discuss

the blocks of the echo suppression unit in detail.

SCLSSCAS

SDX

SDR

AGCR

AGCX

Attenuation

Control

line outmicrophone

loudspeaker

LGAX

LGAR line in

GHX

GHR

PSB 4860

Data Sheet 34 2000-01-14

2.1.3.1 Speech Detector

For each signal source a speech detector (SDX, SDR) is available. The speech

detectors are identical but can be programmed individually. Figure 17 shows the signal

flow graph of a speech detector.

Figure 17 Speech Detector - Signal Flow Graph

The first three units (LIM, LP1, PD) are used for preprocessing the signal while the actual

speech detection is performed by the background noise monitor.

Background Noise Monitor

The tasks of the noise monitor are to differentiate voice signals from background noise,

even if it exceeds the voice level, and to recognize voice signals without any delay.

Therefore the Background Noise Monitor consists of the Low-Pass Filter 2 (LP2) and the

offset in two separate branches. Basically it works on the burst-characteristic of the

speech: voice signals consist of short peaks with high power (bursts). In contrast,

background noise can be regarded approximately stationary from its average power.

Low-Pass Filter 2 provides different time constants for noise (non-detected speech) and

speech. It determines the average of the noise reference level. In case of background

noise the level at the output of LP2 is approximately the level of the input. As in the other

branch an additional offset OFF is added to the signal, the comparator signals noise. At

speech bursts the digital signals arriving at the comparator via the offset branch change

faster than those via the LP2-branch. If the difference exceeds the offset OFF, the

LIM LP1 PD

LP2

OFF

LP1 PDS

PDN

LP2S

LP2N

LP2L

Background Noise Monitor

Signal Preprocessing

LIM

PSB 4860

Data Sheet 35 2000-01-14

comparator signals speech. Therefore the output of the background noise monitor is a

digital signal indicating speech (1) or noise (0).

A small fade constant (LP2N) enables fast settling of LP2 to the average noise level after

the end of speech recognition. However, a too small time constant for LP2N can cause

rapid charging to such a high level that after recognizing speech the danger of an

unwanted switching back to noise exists. It is recommended to choose a large rising

constant (LP2S) so that speech itself charges the LP2 very slowly. Generally, it is not

recommended to choose an infinite LP2S because then approaching the noise level is

disabled. During continuous speech or tones the LP2 will be charged until the limitation

LP2L is reached. Then the value of LP2 is frozen until a break discharges the LP2. This

limitation permits transmission of continuous tones and “music on hold”.

The offset stage represents the estimated difference between the speech signal and

averaged noise.

Signal Preprocessing

As described in the preceding chapter, the background noise monitor is able to

discriminate between speech and noise. In very short speech pauses e.g. between two

words, however, it changes immediately to non-speech, which is equal to noise.

Therefore a peak detection is required in front of the Noise Monitor.

The main task of the Peak Detector (PD) is to bridge the very short speech pauses during

a monolog so that this time constant has to be long. Furthermore, the speech bursts are

stored so that a sure speech detection is guaranteed. But if no speech is recognized the

noise low-pass LP2 must be charged faster to the average noise level. In addition, the

noise edges are to be smoothed. Therefore two time constants are necessary. As the

peak detector is very sensitive to spikes, the low-pass LP1 filters the incoming signal

containing noise in a way that main spikes are eliminated. Due to the programmable time

constant it is possible to refuse high-energy sibilants and noise edges.

To compress the speech signals in their amplitudes and to ease the detection of speech,

the signals have to be companded logarithmically. Hereby, the speech detector should

not be influenced by the system noise which is always present but should discriminate

between speech and background noise. The limitation of the logarithmic amplifier can be

programmed via the parameter LIM. LIM is related to the maximum PCM level. A signal

exceeding the limitation defined by LIM is getting amplified logarithmically, while very

smooth system noise below is neglected. It should be the level of the minimum system

noise which is always existing; in the transmit path the noise generated by the telephone

circuitry itself and in receive direction the level of the first bit which is stable without any

speech signal at the receive path. Table 4 shows the parameters for the speech detector.

PSB 4860

Data Sheet 36 2000-01-14

The input signal of the speech detector can be connected to either the input signal of the

echo suppression unit (as shown for SDX) or the output of the associated AGC (as

shown for SDR). This can be selected with bits SDX and SDR of table 10.

Table 4 Speech Detector Parameters

Parameter # of bytes Range Comment

LIM 1 0 to -95 dB Limitation of log. amplifier

OFF 1 0 to 95 dB Level offset up to detected noise

PDS 1 1 to 2000 ms Peak decrement PD1 (speech)

PDN 1 1 to 2000 ms Peak decrement PD1 (noise)

LP1 1 1 to 2000 ms Time constant LP1

LP2S 1 2 to 250 s Time constant LP2 (speech)

LP2N 1 1 to 2000 ms Time constant LP2 (noise)

LP2L 1 0 to 95 dB Maximum value of LP2

PSB 4860

Data Sheet 37 2000-01-14

2.1.3.2 Speech Comparators (SC)

The echo suppression unit has two identical speech comparators (SCAS, SCLS). Each

comparator can be programmed individually to accommodate the different system

characteristics of the acoustic interface and the line interface. As SCAS and SCLS are

identical, the following description holds for both SCAS and SCLS.

The SC has two input signals SX and SR, which map to microphone/loudspeaker for

SCAS and line in/line out for SCLS.

The speech comparator decides whether the signal coming in on SR is only an echo from

the signal outgoing on SX or a real speech activity. The result is then interpreted by the

Attenuation Control of figure 16. In general, the SC works according to the following

equation:

Therefore, SCAS controls the switching to transmit state and SCLS controls the

switching to receive state. Switching is done only if SX exceeds SR by at least the

expected acoustic level enhancement V. This level enhancement is divided into two

parts: G and GD. A block diagram of the SC is shown in figure 18.

Figure 18 Speech Comparator - Block Diagram

At both inputs, logarithmic amplifiers compress the signal range. Hence, only logarithmic

levels are on both paths and after the signals have been processed, logarithmic levels

on both paths are compared.

if SX > SR + V then switch state

GGDS

GDN

PDS

PDN

Log. Amp. Base Gain Gain Reserve Peak Decrement

Log. Amp.

PDS

PDN

Peak Decrement

PSB 4860

Data Sheet 38 2000-01-14

The main task of the comparator is to control the echo. The internal coupling due to the

direct sound and mechanical resonances is covered by G. The external coupling, mainly

caused by the acoustic feedback, is controlled by GD/PD. An example for direct sound

(1) and acoustic feedback (2) is illustrated in figure 19.

Figure 19 Speech Comparator - Acoustic Echoes

The base gain G corresponds to the terminal couplings of the complete telephone. Thus,

G is the measured or calculated level enhancement between the receive and the

transmit input of the SC.

To control the acoustic feedback two parameters are necessary: GD represents the

actual reserve on the measured G. Together with the Peak Decrement (PD), the echo

behavior at the acoustic side is modeled: After speech has ended there is a short time

during which hard couplings through the mechanics and resonances and the direct echo

are present. Till the end of that time (∆t), the level enhancement V must be at least equal

to G to prevent clipping caused by these internal couplings. After that time (∆t), only the

acoustic feedback is present. This coupling, however, is reduced by air attenuation. For

this in general the longer the delay, the smaller the echo being valid. This echo behavior

is taken care of by the decrement rate PD.

PSB 4860

Data Sheet 39 2000-01-14

Figure 20 Speech Comparator - Interdependence of Parameters

According to figure 19, a compromise between the reserve GD and the decrement rate

PD has to be made: a smaller reserve (GD) above the level enhancement G requires a

longer time to decrease (PD). It is easy to overshout the other side but the

intercommunication is harder because after the end of the speech, the level of the

estimated echo has to be exceeded. In contrast, with a higher reserve (GD*) it is harder

to overshout continuous speech or tones, but a faster intercommunication is supported

because of a stronger decrement (PD*).

Two pairs of coefficients, GDS/PDS when speech is detected, and GDN/PDN in case of

noise, offer a different echo handling for speech and non-speech. With speech, even if

very strong resonances are present, the performance will not be worsened by the high

GDS needed. Only when speech is detected, a high reserve prevents clipping.

The time ∆t (determined by parameter ET) after speech ends, the parameters of the

comparator are switched to the “noise” values. If both sets of the parameters are equal,

ET has no effect.

Table 5 Speech Comparator Parameters

Parameter # of bytes Range Comment

G1–48 to + 48 dB Base Gain

GDS 1 0 to 48 dB Gain Reserve (Speech)

∆t

GD*

PD*

RX-Speech

RX-noise

PSB 4860

Data Sheet 40 2000-01-14

2.1.3.3 Attenuation Control

The attenuation control unit performs state switching by controlling the attenuation

stages GHX and GHR. In receive state, the attenuation G is completely switched to

GHX. In transmit state, the attenuation G is completely switched to GHR. In idle state,

both GHX and GHR attenuate by G/2. State switching depends on the signals of one

speech comparator and the corresponding speech detector.

The attenuation G actually provided by the attenuation stages GHR and GHX is the

attenuation determined by the parameter ATT minus the attenuation reported by the

echo cancellation unit (G = ATT - GC).

Additional (fixed) attenuation on the transmit and receive path is also influenced by the

automatic gain control stages AGCX and AGCR, respectively.

While each state is associated with the programmed attenuation, the time TSW it takes

to reach the steady-state attenuation after a state switch can be programmed. The time

TSW depends on a programmable decay rate SW and the current attenuation G by the

formula .

If the current state is either transmit or receive and no speech on either side has been

detected for time TTW then the idle state is entered. To smoothen the transition, the

attenuation is incremented (decremented) by DS until the evenly distribution G/2 for both

GHX and GHR is reached.

Table 6 summarizes the parameters for the attenuation unit.

PDS 1 0.025 to 6 dB/ms Peak Decrement (Speech)

GDN 1 0 to 48 dB Gain Reserve (Noise)

PDN 1 0.025 to 6 dB/ms Peak Decrement (Noise)

ET 1 0 to 992 ms Time to Switch from speech to noise

parameters

Table 6 Attenuation Control Unit Parameters

Parameter # of bytes Range Comment

TW 1 0 ms to 4096 ms TTW to return to idle state

ATT 1 0 to 95 dB Attenuation of both echo cancellation

and echo suppression

DS 1 0.6 to 680 ms/dB Decay Speed (to idle state)

SW 1 0.0052 to 10 ms/dB Decay Rate (used for TSW)

Table 5 Speech Comparator Parameters

Parameter # of bytes Range Comment

Tsw SW G×=

PSB 4860

Data Sheet 41 2000-01-14

Note: In addition, attenuation is also influenced by the Automatic Gain Control stages

(AGCX, AGCR) in order to keep the total loop attenuation constant.

Note: By programming parameter DS to 0xFF idle mode is disabled and the

speakerphone will remain in the last state. This parameter must be set before

enabling the speakerphone.

2.1.3.4 Echo Suppression Status Output

The PSB 4860 can report the current state of the echo suppression unit to ease

optimization of the parameter set of the echo suppression unit. In this case the SPS0 and

SPS1 pins are set according to table 7.

Furthermore the controller can read the current value of the SPS pins by reading register

SPSCTL.

2.1.3.5 Loudhearing

The speakerphone unit can also be used for controlled loudhearing. This is enabled by

setting bit MD in register SCTL. If loudhearing mode is enabled, the loudspeaker

amplifier of the PSB 4851 (ALS) is used instead of GHR (figure 16) when appropriate to

avoid oscillation. To use this feature, the PSB 4851 must be programmed to allow ALS

override. The ALS field within the AFE control register AFECTL defines the value sent to

the PSB 4851 if attenuation is necessary (see specification of the PSB 4851).

2.1.3.6 Amplifiers with Automatic Gain Control

The echo suppression unit has two identical automatic gain control units AGCX and

AGCR both referred to as AGC in this section.

Whether the automatic gain control AGC amplifies or attenuates depends on whether the

signal level is above or below the threshold level defined by parameter COM. The

threshold is relative to the maximum PCM-value and thus negative. The parameters

AG_GAIN and AG_ATT determine the maximal amplification and attenuation,

respectively. The bold line in Figure 21 gives an example for the steady-state output level

of the AGC as a function of the input level.

Table 7 SPS Output Encoding

SPS0SPS1Echo Suppression Unit State

0 0 no echo suppression operation

01receive

1 0 transmit

1 1 idle

PSB 4860

Data Sheet 42 2000-01-14

Figure 21 Echo Suppression Unit - Automatic Gain Control

For reasons of physiological acceptance, the AGC gain is automatically reduced in case

of continuous background noise (e.g. by ventilators). The reduction is programmed via

the NOlS parameter. When the noise level exceeds the threshold determined by NOIS,

the amplification will be reduced by the same amount the noise level is above the

threshold.

The regulation speed is controlled by SPEEDH for signal amplitudes above the threshold

and SPEEDL for amplitudes below. Usually SPEEDH will be chosen to be at least 10

times faster than SPEEDL. An additional low pass with time constant LP is provided to

avoid an immediate response of the AGC to very short signal bursts. The time constant

of the low pass should not be selected longer than 4 ms in order to avoid unstable

behavior.

If the speech detector SDX detects noise or the receive path is active, AGCX freezes its

current attenuation and the last gain setting is used. Regulation starts with this value as

soon as SDX detects speech and the receive path is inactive. Likewise, if SDR detects

noise or the transmit path is active, AGCR freezes its current attenuation and the last

gain setting is used. Regulation starts with this value as soon as SDR detects speech

and the transmit path is inactive.

The current gain/attenuation of the AGC can be read at any time (AG_CUR). When the

AGC has been disabled, the initial gain used immediately after enabling the AGC can be

programmed. Table 8 shows the parameters of the AGC.

COM

AG_ATT

AG_GAIN

AGC input level

AGC

output

level

max. PCM

-10 dB

-20 dB

-10 dB-20 dB

Example:

COM

AG_GAIN

AG_ATT

-30 dB

15 dB

20 dB

PSB 4860

Data Sheet 43 2000-01-14

Note: There are two sets of parameters, one for AGCX and one for AGCR.

Note: By setting AG_GAIN to 0 dB a limitation function can be realized with the AGC.

2.1.3.7 Amplifiers with Fixed Gain

Each signal path features an additional amplifier (LGAX, LGAR) that can be set to a fixed

gain. These amplifiers should be used for the basic amplification in order to avoid

saturation in the preceding stages. Table 9 describes the only parameter of this stage.

2.1.3.8 Mode Control

Table 10 shows the registers used to determine the signal sources and the

speakerphone mode.

Table 8 Automatic Gain Control Parameters

Parameter # of Bytes Range Comment

AG_INIT 1 -95 dB to 95dB Initial AGC gain/attenuation

COM 1 0 to –95 dB Compare level rel. to max. PCM-value

AG_ATT 1 0 to -95 dB Attenuation range

AG_GAIN 1 0 to 48 dB Gain range

AG_CUR 1 -95 dB to 95 dB Current gain/attenuation

SPEEDL 1 0.25 to 62.5 dB/s Change rate for lower levels

SPEEDH 1 2 to 500 dB/s Change rate for higher levels

NOIS 1 0 to – 95 dB Threshold for AGC-reduction

by background noise

LP 1 0.025 to 16 ms AGC low pass time constant

Table 9 Fixed Gain Parameters

Parameter # of Bytes Range Comment

LGA 1 -30 dB to 12 dB always active

Table 10 Speakerphone Control Registers

SCTL 1 ENS Echo suppression unit enable

SCTL 1 ENC Echo cancellation unit enable

SCTL 1 MD Speakerphone or loudhearing mode

PSB 4860

Data Sheet 44 2000-01-14

SCTL 1 AGX AGCX enable

SCTL 1 AGR AGCR enable

SCTL 1 SDX SDX input tap

SCTL 1 SDR SDR input tap

AFECTL 4 ALS ALS value for loudhearing

SSRC1 5 I1 Input signal 1 (microphone)

SSRC1 5 I2 Input signal 2 (microphone)

SSRC2 5 I3 Input signal 3 (line in)

SSRC2 5 I4 Input signal 4 (line in)

Table 10 Speakerphone Control Registers

PSB 4860

Data Sheet 45 2000-01-14

2.1.4 Line Echo Canceller

The contains an adaptive line echo cancellation unit for the cancellation of near end

echoes. The unit has three modes.

Normal mode: The maximum echo length considered is 4 ms. This mode is always avail-

able.

Extended mode: The maximum echo length considered is 24 ms. This mode cannot be

used while the speech encoder, the acoustic echo cancellation unit or slow

playback is active.

Superior mode: The maximum echo length considered is 4 ms. This mode is always

available. By using an additional shadow filter, the echo cancellation quality is

improved.

The line echo cancellation unit is especially useful in front of the various detectors

(DTMF, CPT, etc.). A block diagram is shown in figure 22.

Figure 22 Line Echo Cancellation Unit - Block Diagram

Input I2 is usually connected to the line input while input I1 is connected to the outgoing

signal.

In normal mode the adaptation process is controlled by the three parameters MIN, ATT

and MGN. Adaptation takes place only if both of the following conditions hold:

With the first condition, adaptation to small signals can be avoided. The second condition

avoids adaptation during double talk. The parameter ATT represents the echo loss

provided by external circuitry. The adaptation stops if the power of the received signal

(I2) exceeds the power of the expected signal (I1-ATT) by more than the margin MGN.

In extended mode, adaptation is enabled all the time.

Adaptive

Filter

I2S15

I1 MIN>

I1 I2–ATTMGN+–0>

PSB 4860

Data Sheet 46 2000-01-14

Figure 23 Line Echo Cancellation Unit - Superior Mode with Shadow FIR

The basic idea of the superior mode is shown in figure 23. The shadow FIR filter on the

left hand side gets its coefficients adapted similar to the adaptive filter of the Line Echo

Canceller in normal mode. For cancelling the line echo, however, the FIR filter on the

right hand side is used. When the quality of this FIR filter is excelled by the quality of the

shadow FIR filter, the coefficients of the shadow FIR filter are copied to the FIR on the

right hand side. More formally, the coefficients of the shadow FIR filter are adapted (see

unit “adapt coeff” in figure 23) if similar to normal mode, the following two conditions hold:

In this case, ATT is already the difference between external echo loss and margin

(ATTsuperior = ATTnormal - MGNnormal) so that the condition is actually the same as for

normal mode. The parameter ATT should be adjusted accordingly. Note that ATT can

now be negative.

The coefficients are copied from the shadow FIR filter to the actually used FIR filter (see

unit “copy coeff.” in figure 23) if

1. currently the adaptation of the shadow FIR filter is in progress

and at least one of the following two conditions holds:

The attenuation of the shadow FIR filter ATTS is better than the attenuation of the

actually used FIR filter ATTA by a margin MGN. Note that parameter MGN has now a

different meaning than in normal mode

The current attenuation ATTS of the shadow FIR is better than at any time since last

update according to condition 2.

Filter

FIR

I2S15

FIR

Shadow

Filter

adapt

copy

coeff.

I1 MIN>

I1 I2–ATT–0>

ATTS ATTA–MGN>

ATTS t() max ATTS t 1–()…ATTS last time condition 2 has been valid(),,()>

PSB 4860

Data Sheet 47 2000-01-14

Table 11 shows the registers associated with the line echo canceller.

The adaptation of the coefficients can be stopped by setting bit AS in register LECCTL.

This holds for all three modes of the Line Echo Canceller. Furthermore for superior

mode, also the copying of the coefficients from the shadow FIR is disabled.

The different modes can be selected by setting the bits MD and CM as indicated by

table 12.

Table 12 Selection of the Mode of the Line Echo Canceller

Table 11 Line Echo Cancellation Unit Registers

LECCTL 1 EN Line echo canceller enable all

LECCTL 1 MD Line echo canceller mode

LECCTL 1 CM Compatibility mode

LECCTL 1 AS Adaptation stop all

LECCTL 5 I2 Input signal selection for I2all

LECCTL 5 I1 Input signal selection for I1all

LECLEV 15 MIN Minimal power for signal I1 normal and sup.

LECATT 15 ATT Externally provided attenuation (I1 to I2) normal and sup.

LECMGN 15 MGN Margin normal and sup.

MD CM Mode

00Normal mode

0 1 Superior mode

1 - Extended mode

PSB 4860

Data Sheet 48 2000-01-14

2.1.5 DTMF Detector

The contains an DTMF detector that recognizes the sixteen standard DTMF tones.

Figure 24 shows a block diagram of the DTMF detector. The results of the detector are

available in the status and a dedicated result register. These registers can be read by

the external controller via the serial control interface (SCI).

Figure 24 DTMF Detector - Block Diagram

Table 13 to 15 show the associated registers.

As soon as a valid DTMF tone is recognized, the status word and the DTMF tone code

are updated (table 14).

DTV is set when a DTMF tone is currently recognized and cleared when no DTMF tone

is recognized or the detector is disabled. The code for the DTMF tone is provided in

The registers DDTW and DDLEV contain the parameters for detection (table 15).

Table 13 DTMF Detector Control Register

DDCTL 1 EN DTMF detector enable

DDCTL 5 I1 Input signal selection

Table 14 DTMF Detector Results

STATUS 1 DTV DTMF code valid

DDCTL 5 DTC DTMF tone code

Table 15 DTMF Detector Parameters

DDTW 15 TWIST Twist for DTMF recognition

DDLEV 6 MIN Minimum signal level to detect DTMF tones

DTMF

SCI

I1Detector

PSB 4860

Data Sheet 49 2000-01-14

2.1.6 CNG Detector

The calling tone (CNG) detector can detect the standard calling tones of fax machines

or modems. This helps to distinguish voice messages from data transfers. The result of

the detector is available in the status register that can be read by the external controller

via the serial control interface (SCI). The CNG detector consists of two band-pass filters

with fixed center frequency of 1100 Hz and 1300 Hz.

Figure 25 CNG Detector - Block Diagram

Table 16 shows the available parameters.

For a calling tone being detected, both the programmed minimum time and the minimum

signal level must be exceeded. Furthermore the input signal resolution can be reduced

by the RES parameter. Then the signal noise below the threshold RES is not regarded.

This can be useful in a noisy environment at low signal levels although the accuracy of

the detection decreases. As soon as a valid tone is detected, the status word of the is

updated. The status bits are defined as follows:

Note: STATUS:CNG is cleared only by disabling the module.

Table 16 CNG Detector Registers

CNGCTL 1 EN CNG detector enable

CNGCTL 5 I1 Input signal selection

CNGLEV 16 MIN Minimum signal level

CNGBT 16 TIME Minimum time of signal burst

CNGRES 16 RES Input signal resolution

Table 17 CNG Detector Result

STATUS 1 CNG Fax/Modem calling tone detected

CNG Detector

SCI

1100 Hz 1300 Hz

PSB 4860

Data Sheet 50 2000-01-14

2.1.7 Alert Tone Detector

The alert tone detector can detect the standard alert tones (2130 Hz and 2750 Hz) for

caller id protocols. The results of the detector are provided in the status register and

control interface (SCI).

Figure 26 Alert Tone Detector - Block Diagram

As soon as a valid alert tone is recognized, the status word of the and the code for the

detected combination of alert tones are updated (table 19). With On Hook mode

selected, the end of the alert tone can be detected faster. On Hook mode assumes that

there is no speech signal present.

Table 18 Alert Tone Detector Registers

ATDCTL0 1 EN Alert Tone Detector Enable

ATDCTL0 5 I1 Input signal selection

ATDCTL1 1 MD Detection of dual tones or single tones

ATDCTL1 1 DEV Maximum deviation (0.5% or 1.1%)

ATDCTL1 1 ONH On hook mode

ATDCTL1 8 MIN Minimum signal level to detect alert tones

Table 19 Alert Tone Detector Results

STATUS 1 ATV Alert tone detected

ATDCTL0 2 ATC Alert tone code

Alert Tone

SCI

I1 Detector

PSB 4860

Data Sheet 51 2000-01-14

2.1.8 Universal Tone Detector

The universal tone detector can be used instead of the CPT detector to detect special

tones which are not covered by the standard CPT band-pass. Figure 27 shows the

functional block diagram.

Figure 27 Universal Tone Detector - Block Diagram

Initially, the input signal is filtered by a programmable band-pass (center frequency CF

and band width BW). Both the in-band signal (upper path) and the out-of-band signal are

determined (lower path) and the absolute value is calculated. Both signals are

furthermore filtered by a limiter and a low-pass. All signal samples (absolute values)

below a programmable limit LIM are set to zero and all other signal samples are

diminished by LIM. The purpose of the limiter is to increase noise robustness. After the

limiter stages both signals are filtered by a fixed low pass.

The evaluation logic block determines when to set and when to reset the status bit

STATUS:UTD.

The status bit will be set if both of the following conditions hold for at least time TTONE

without breaks exceeding time TB1:

1. the in-band signal exceeds a programmable level LEV

2. the difference of the in-band and the out-of-band signal exceeds DELTA

The status bit will be reset if at least one of these conditions is violated by at least time

TGAP without breaks exceeding TB2.

The times TB1 and TB2 help to reduce the effects of sporadic dropouts.

Example:

TTONE is set to 100 ms and TB1 is set to 4 ms.

Evaluation

Logic SCI

Programmable

Band-pass

Limit

|x|

PSB 4860

Data Sheet 52 2000-01-14

The conditions are met for 30ms, then violated for 3ms and then met again for 80 ms. In

this case the break of 3ms is ignored, because it does not exceed the allowed break time

TB1. Therefore the status bit will be set after 100 ms.

Table 20 summarizes the associated registers.

The result is available in the status register (table 21).

Note: The UTD bit is at the same position as the CPT bit. Therefore the CPT detector

and the UTD must not run at the same time.

Table 20 Universal Tone Detector Registers

UTDCTL 1 EN Band-pass Enable

UTDCTL 5 I1 Input signal selection

UTDBW 15 BW Bandwidth of band-pass

UTDCF 16 CF Center frequency of band-pass

UTDLIM 15 LIM Limiter limit

UTDLEV 15 LEV Minimum signal level (in-band)

UTDLEV 15 DELTA Minimum difference (in-band, out-of-band)

UTDTMT 8 TTONE Minimum time to set status bit

UTDTMT 8 TB1 Maximum break time for TTONE

UTDTMG 8 TGAP Minimum time to reset status bit

UTDTMG 8 TB2 Maximum break time for TGAP

Table 21 Universal Tone Detector Results

STATUS 1 UTD Tone detected

PSB 4860

Data Sheet 53 2000-01-14

2.1.9 CPT Detector

The selected signal is monitored continuously for a call progress tone. The CPT detector

consists of a band-pass and an optional timing checker (figure 28).

Figure 28 CPT Detector - Block Diagram

The CPT detector can be used in two modes: raw and cooked. In raw mode, the

occurrence of a signal within the frequency range, time and energy limits is directly

reported. The timing checker is bypassed and therefore the does not interpret the length

or any interval of the signal.

In cooked mode, the number and duration of signal bursts are interpreted by the timing

checker. A signal burst followed by a gap is called a cycle. Cooked mode requires a

minimum of two cycles. The CPT flag is set with the first burst after the programmed

number of cycles has been detected. The CPT flag remains set until the unit is disabled

or speech is detected, even if the conditions are not met anymore. In this mode the CPT

is modeled as a sequence of identical bursts separated by gaps with identical length.

The can be programmed to accept a range for both the burst and the gap. It is also

possible to specify a maximum aberration of two consecutive bursts and gaps. Figure 29

shows the parameters for a single cycle (burst and gap).

Figure 29 CPT Detector - Cooked Mode

The status bit is defined as follows:

Timing

Band-pass

SCI (Status)I1

300-640 Hz

Checker

tBmax

tBmin

tGmin

tGmax

PSB 4860

Data Sheet 54 2000-01-14

CPT is not affected by reading the status word. It is automatically reset when the unit is

disabled. Table 23 shows the control register for the CPT detector.

If any condition is violated during a sequence of cycles the timing checker is reset and

restarts with the next valid burst.

Note: In cooked mode CPT is set with the first burst after the programmed number of

cycles has been detected. If CPTTR:NUM = 2, then CPT is set with the third signal

burst.

Note: The number of cycles must be set to zero in raw mode.

Note: The UTD bit is at the same position as the CPT bit. Therefore the CPT detector

and the UTD must not run at the same time.

Table 22 CPT Detector Result

STATUS 1 CPT CP tone currently detected [300 Hz; 640 Hz]

Table 23 CPT Detector Registers

CPTCTL 1 EN Unit enable

CPTCTL 1 MD Mode (cooked, raw)

CPTCTL 5 I1 Input signal selection

CPTMN 8 MINB Minimum time of a signal burst (tBmin)

CPTMN 8 MING Minimum time of a signal gap (tGmin)

CPTMX 8 MAXB Maximum time of a signal burst (tBmax)

CPTMX 8 MAXG Maximum time of a signal gap (tGmax)

CPTDT 8 DIFB Maximum difference between consecutive bursts

CPTDT 8 DIFG Maximum difference between consecutive gaps

CPTTR 3 NUM Number of cycles (cooked mode), 0 (raw mode)

CPTTR 8 MIN Minimum signal level to detect tones

CPTTR 4 SN Minimal signal-to-noise ratio

PSB 4860

Data Sheet 55 2000-01-14

2.1.10 Caller ID Decoder

The caller ID decoder is basically a 1200 baud modem (FSK, demodulation only). The

bit stream is formatted by a subsequent UART and the data is available in a data register

along with status information (figure 30).

Figure 30 Caller ID Decoder - Block Diagram

The FSK demodulator supports two modes according to table 24. The appropriate mode

is detected automatically.

The CID decoder does not interpret the data received. Each byte received is placed into

the CIDCTL register (table 26). The status byte of the is updated (table 25).

CIA and CD are cleared when the unit is disabled. In addition, CIA is cleared when

CIDCTL0 is read.

Table 24 Caller ID Decoder Modes

Mode Mark

(Hz)

Space

(Hz)

Comment

1 1200 2200 Bellcore

2 1300 2100 V.23

Table 25 Caller ID Decoder Status

STATUS 1 CIA CID byte received

STATUS 1 CD Carrier Detected

Table 26 Caller ID Decoder Registers

CIDCTL0 1 EN Unit enable

CIDCTL0 1 DOT Drop out tolerance during mark or seizure sequence

CIDCTL0 1 CM Compatibility mode

CIDCTL0 5 I1 Input signal selection

UART

FSK demod. SCI (Status, Data)

(Bellcore, V.23)

PSB 4860

Data Sheet 56 2000-01-14

When the CID unit is enabled, it waits for a programmable number of continuous mark

bits (CIDCTL1:NMB). These mark bits may optionally be preceded by a channel seizure

signal consisting of a series of alternating space and mark signals. If such a channel

seizure sequence is present it must consist of at least CIDCTL1:NMSS alternating mark

and space bits. Once the programmed number of continuous mark bits has been

received the sets the carrier detect bit STATUS:CD.

The interpretation of the data, including message type, length and checksum is

completely left to the controller. The CID unit should be disabled as soon as the complete

information has been received as it cannot detect the end of the transmission by itself.

There are two alternative Caller ID Decoders. With bit CM cleared, the standard Caller

ID Decoder is selected, which is compatible to PSB 4860 versions 2.1 and 3.1. The

standard Called ID Decoder requires a seizure sequence. With CM set to 1, the

improved Caller ID Decoder is selected, which provides a higher twist tolerance and

improved noise immunity, does not require a seizure sequence, and allows to select the

drop out tolerance. The drop out tolerance is selected by bit DOT of register CIDCTL0.

Then, drop outs during a mark sequence do not necessarily cause that the CID detection

looses its carrier sequence, but the received mark sequence can be recognized although

there are drop outs. The same holds for a seizure sequence. This behavior meets the

Bellcore test specification.

If drop out tolerance is enabled, the six registers CIDMF1 to CIDMF6 have to be

programmed prior to use of this feature. Note that these registers are undefined after

recompression. The registers CIDMF1 to CIDMF6 must contain all possible message

formats, which can be transmitted after the mark sequence, and these registers must not

contain any other value. For Bellcore for example, the valid message formats are 04h,

06h, 80h and 82h so that registers CIDMF1 to CIDMF6 may contain 04h, 06h, 80h, 82h,

82h and 82h.

Note: Some caller ID mechanism may require additional external components for DC

decoupling. These tasks must be handled by the controller.

Note: The controller is responsible for selecting and storing parts of the CID as needed.

Note: The caller ID decoder cannot be enabled at the same time as the caller ID sender.

CIDCTL0 8 DATA Last CID data byte received

CIDCTL1 5 NMSS Number of mark/space sequences necessary for

successful detection of carrier.

CIDCTL1 5 NMB Number of mark bits necessary before space of first

byte after carrier detected.

CIDCTL1 6 MIN Minimum signal level for CID detection.

Table 26 Caller ID Decoder Registers

PSB 4860

Data Sheet 57 2000-01-14

2.1.11 Caller ID Sender

The caller ID sender is a 1200 baud modem (FSK, modulation only). The byte data

stream is formatted by a UART and then modulated (figure 31).

Figure 31 Caller ID Sender - Block Diagram

The FSK modulator supports two modes according to table 27.

The CID sender can send a programmable number of seizure bits, followed by an also

programmable number of mark bits prior to the first data byte. The sender starts

transmission once it is enabled. The status byte of the is updated (table 28).

Bit CIR is set, when a new byte for transmission can be written to CISDATA:DATA. If no

new data byte has been written in time (i.e. at the beginning of the next start bit) then the

caller ID sender automatically sends stop bits and sets the status bit CIS. CIS and CIR

are cleared when the unit is disabled or the data register CISDATA is written.

Table 27 Caller ID Sender Modes

Mode Mark

(Hz)

Space

(Hz)

Comment

1 1200 2200 Bellcore

2 1300 2100 V.23

Table 28 Caller ID Sender Status

STATUS 1 CIR CID byte request

STATUS 1 CIS Stop bits are sent

Table 29 Caller ID Sender Registers

CISCTL 1 EN Unit enable

CISCTL 1 MD Modulation mode

UART FSK mod. S22

SCI

(Bellcore, V.23)

PSB 4860

Data Sheet 58 2000-01-14

Note: The caller ID sender cannot be activated at the same time as the caller ID decoder.

CISDATA 8 DATA Next data byte to be transmitted

CISLEV 15 LEV Transmit signal level

CISSZR 15 SEIZ Number of seizure bits

CISMRK 15 MARK Number of mark bits

Table 29 Caller ID Sender Registers

PSB 4860

Data Sheet 59 2000-01-14

2.1.12 DTMF Generator

The DTMF generator can generate single or dual tones with programmable frequency

and level. This unit is primarily used to generate the common DTMF tones but can also

be used for signalling or other user defined tones. A block diagram is shown in figure 32.

Figure 32 DTMF Generator - Block Diagram

The two frequency generators and level adjustment stages are identical. There are two

modes for programming the generators, cooked mode and raw mode. In cooked mode,

the standard DTMF frequencies are generated by programming a single 4 bit code. In

raw mode, the frequency of each generator can be programmed individually by a

separate register. The unit has two outputs which provide the same signal but with

individually programmable attenuation. Table 30 shows the parameters of this unit.

Note: DGF1 and DGF2 are undefined when cooked mode is used and must not be

written.

Table 30 DTMF Generator Registers

DGCTL 1 EN Enable for generators

DGCTL 1 MD Mode (cooked/raw)

DGCTL 4 DTC DTMF code (cooked mode)

DGF1 15 FRQ1 Frequency of generator 1

DGF2 15 FRQ2 Frequency of generator 2

DGL 7 LEV1 Signal level of generator 1

DGL 7 LEV2 Signal level of generator 2

DGATT 8 ATT1 Attenuation of S9

DGATT 8 ATT2 Attenuation of S10

generator

lev1

lev2 att2

S10

att1

PSB 4860

Data Sheet 60 2000-01-14

2.1.13 Speech Coder

The speech coder (figure 33) has two input signals I1 and I2. The first signal (I1) is fed to

the coder while the second signal (I2) is used as a reference signal for voice controlled

recording. The signal I1 can be coded by either a 3.3 kbit/s, 5.6 kbit/s or 10.3 kbit/s coder.

Figure 33 Speech Coder - Block Diagram

The data rates 10.3 kbit/s and 5.6 kbit/s are fixed rates. The data rate 3.3 kbit/s is an

average rate that can actually vary between 740 bit/s and 4.8 kbit/s. The rate currently

achieved heavily depends on the energy of the incoming signal. While silence is

encoded with 740 bit/s, high energy bursts require 4.8 kbit/s. This implies that for a voice

prompt consisting of only one word, the compression rate tends to be approximately

4.8 kbit/s. Furthermore if an Automatic Gain Control AGC is used, the AGC may increase

the signal power in such a way that silence is not recognized as silence. Then, the

compression rate also tends to approximate 4.8 kbit/s.

Data is written initially at the beginning of a file and the file pointer is advanced as

needed. In case of any memory error (e.g. memory full) a file error is indicated and the

coder is disabled. The controller must subsequently close the file. The file can be played

back, though.

The coder’s compression rate can be switched on the fly. However, it may take up to

60 ms until the switch is executed. No audio data is lost during switching.

The signal I2 is first filtered by a low pass LP with programmable time constant and then

compared to a reference level MIN. If the filtered signal exceeds MIN, then the status bit

SD (table 31) is set immediately. If the filtered signal has been smaller than MIN for a

programmable time TIME then the status bit SD is reset.

The coder can be enabled in permanent mode or in voice recognition mode. In

permanent mode (bit VC is set to 0), the coder starts immediately and compresses all

input data continuously. The current state of the status bit SD does not affect the coder.

In voice recognition mode (bit VC is set to 1), the coder is automatically started on the

first transition of the status bit from 0 to 1. Once the coder has started it remains active

until disabled.

10300 bit/s

I1Memory

MIN

3300 bit/s

5600 bit/s

VOXGAP SCI

SCI

PSB 4860

Data Sheet 61 2000-01-14

The coder can optionally use silence gap coding. This feature can reduce the bit rate

dramatically if there are long periods of silence in the incoming data stream. The GAP

bit in the STATUS register is set when a gap is detected and the speech coder performs

gap coding. This feature is only available for compression rates 5.6 and 10.3 kBit/s, and

thus cannot be used to influence compression rate in 3.3 kBit/s mode.

Furthermore the speech coder contains a VOX detector that can distinguish voice from

signals with constant energy (noise, silence, sine signals). The result of this detector is

available by the bit VOX of the STATUS register.

The operation of the speech coder is defined according to table 32.

Table 31 Speech Coder Status

STATUS 1 SD Speech detected

STATUS 1 GAP A gap is detected during recording

STATUS 1 VOX Noise, silence, constant or periodic signal detected

Table 32 Speech Coder Control Registers

SCCTL 1 EN Enable speech coder

SCCTL 1 GAP Enable gap coding

SCCTL 2 Q0, Q1 Recording quality

SCCTL 1 VC Voice controlled recording

SCCTL 1 VOX VOX detection enable

SCCTL 5 I1 Input signal 1 selection

SCCTL 5 I2 Input signal 2 selection

SCCT2 8 MIN Minimal signal level for speech detection

SCCT2 8 TIME Minimum time for reset of SD

SCCT3 7 LP Time constant for low-pass

SCCT3 8 GAPT Minimum time for gap

PSB 4860

Data Sheet 62 2000-01-14

The gap detector consists of a speech detector and a subsequent timer. A gap is

detected whenever the speech detector detects no speech for at least time GAPT. The

speech detector has the same signal flow graph and parameters as the speech detectors

SDX or SDR of the speakerphone.

Table 33 shows the registers that hold these parameters.

Table 33 Speech Coder - Gap Detector Control Registers

SCGAP1 7 LP2L Maximum value of LP2

SCGAP1 7 LIM Limitation of log. amplifier

SCGAP2 8 LP1 Time constant LP1

SCGAP2 7 OFF Level offset up to detected noise

SCGAP3 8 PDN Peak decrement PD1 (noise)

SCGAP3 8 LP2N Time constant LP2 (noise)

SCGAP4 8 PDS Peak decrement PD1 (speech)

SCGAP4 7 LP2S Time constant LP2 (speech)

PSB 4860

Data Sheet 63 2000-01-14

The task of the VOX detector is to distinguish between a signal containing voice and high

energy signals called VOX containing just noise or periodic signals (e.g. sine waves).

The general idea how to do this is to distinguish between signals with different CREST

factors. The CREST factor is the difference between the signal’s peak and root-mean-

square power. Furthermore, also signals with low power are classified as VOX. The VOX

detector is illustrated in Figure 34.

Figure 34 VOX Detector

The VOX detector uses a hierarchical approach with three levels of hierarchy:

1. Slice Level

A slice is a 9ms sample of the signal (bars in figure 34). For each slice the power of

the signal is calculated.

2. Segment Level

A segment consists of a programmable number (FLEN) of slices. Each segment is

classified as either a low power, a high power non-voice or a voice segment

depending on the power and distribution of the slices.

3. Frame Level

A frame consists of a programmable number (NFRAMES) of segments. For each

frame the status of the VOX bit is reconsidered based on the information from the

segments.

For each segment the difference between the largest and the smallest power is

calculated. This can be considered as a pseudo-CREST factor. For the first segment, the

pseudo-CREST factor would be the difference between slice 5 and slice 3. Furthermore

for each segment the number N of slices that exceed the programmable limit (POWER)

is determined. For the first segment slices 2, 4 and 5 exceed the limit. Therefore N is 3.

Now for each segment the following result is generated:

If N is smaller than the programmable parameter RPOWB, then this segment contains a

low power signal and the segment is classified as low power. If N is at least RPOWB but

POWER

Frame 1 Frame 2

Slice

Segment

PSB 4860

Data Sheet 64 2000-01-14

the pseudo-CREST factor is smaller than the parameter CREST then the segment is

also classified as low power. Otherwise the segment is classified as voice.

Now the segments are combined into frames and for each frame the following calculation

is performed:

•If at least CVF adjacent segments contain voice then the VOX bit is reset. The internal

timer is reset. If the VOX bit was cleared before, nothing happens. A new frame will

be started immediately.

•If at most RLPF segments are classified as low power segments and at least RVF

segments are classified as voice segments, then the VOX bit is reset because the

frame contains voice. The timer is also reset and the next frame is processed.

•Otherwise, the internal timer is incremented. If the timer has reached the value TIME

then the VOX bit is set and the next frame is processed.

Table 34 shows the registers for the VOX detector.

Table 34 VOX Detector Registers

SCVOX1 7 NFRAMES Number of segments within one frame

SCVOX1 7 CVF Minimum number of adjacent voice segments

SCVOX2 7 RLPF Minimum number of low power segments for VOX

SCVOX2 7 RVF Minimum number of voice segments for voice

SCVOX3 15 POWER Power reference level for slices (noise vs. signal)

SCVOX4 15 CREST Pseudo-CREST factor for slices (VOX/Voice)

SCVOX5 7 RPOWB Minimum number of voice slices within segment

SCVOX5 7 TIME Minimum time to set VOX bit

SCVOX6 11 FLEN Number of slices within a segment

PSB 4860

Data Sheet 65 2000-01-14

The PSB 4860 offers the possibility to transfer the speech data via SCI. Then, no ARAM/

DRAM or Flash needs to be connected to the PSB 4860. To use this feature, the SCI bit

in register SDCTL must be set. The speech coder writes the speech data into register

SCDATA. Bit DA in register STATUS indicates when new data has been written to

SCDATA and the microcontroller must then read this data. When the microcontroller

reads the data, the DA bit is cleared. Table 35 shows the registers involved.

Table 35 Speech Coder - Data Transfer via SCI

Note: Even when the coder is currently being disabled, some last data of the current

block might still have to be transferred via SCI. The microcontroller must go on

with the transfers as long as the DA bit indicates new data.

Note: The data format is different to when ARAM or Flash memory is used. The

compression rate increases by 0.4 kbit/s in case the date rate 10.3 kbit/s or

5.6 kbit/s is used and by 0.2 kbit/s in case the date rates 3.3 kbit/s is used.

SDCTL 1 SCI Speach data transfer via SCI

STATUS 1 DA New data available

SCDATA 16 DATA Speech data

PSB 4860

Data Sheet 66 2000-01-14

2.1.14 Speech Decoder

The speech decoder (figure 35) decompresses the data previously coded by the speech

coder unit and delivers a standard 128 kbit/s data stream.

Figure 35 Speech Decoder - Block Diagram

The decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent

of the selected quality. The data rate, with which the decoder requests input data,

changes accordingly. For messages that have been recorded with gap coding the

decoder offers two additional options. Firstly, the gaps can be skipped during decoding.

With this option, gaps are reduced to a single audio block (30 ms) independently of their

original length.

Secondly, gaps can be replayed as silence or with a noise with programmable level. The

noise level is relative to the level when the message had been recorded. The spectrum

of the replayed noise is similar to the recoded noise.

Table 36 shows the registers for the speech decoder.

Data reading starts at the location of the current file pointer. The file pointer is updated

during speech decoding. If the end of the file is reached, the decoder is automatically

disabled. The automatically resets SDCTL:EN at this point.

If the speed shall be changed on the fly (i.e. while the decoder is enabled) the CS bit

must be set at the same time.

Table 36 Speech Decoder Registers

SDCTL 1 EN Enable speech decoder

SDCTL 1 CS Change Speed

SDCTL 1 CP Gap Compression

SDCTL 1 CN Gap Comfort Noise

SDCTL 2 SPEED Selection of playback speed

SDCT2 15 CN Gap Comfort Noise Level

S13

Memory

10300 bit/s

3300 bit/s

5600 bit/s

PSB 4860

Data Sheet 67 2000-01-14

Note: The last 90 ms of the file are not played back. Therefore an additional 90 ms of

speech should be recorded. If tail-cut is used then it is recommended to cut 3

blocks (each block represents 30 ms of audio data) less than calculated.

PSB 4860

Data Sheet 68 2000-01-14

The PSB 4860 offers the possibility to transfer the speech data via SCI. To use this

feature, the SCI bit in register SDCTL must be set. The speech decoder reads the

speech data from register SDDATA. Bit DRQ in register STATUS indicates when new

data is requested from SDDATA and the microcontroller must then write this data. When

the microcontroller writes the data, the DRQ bit is cleared. Table 37 shows the registers

involved.

Table 37 Speech Decoder - Data Transfer via SCI

SDCTL 1 SCI Speech data transfer via SCI

STATUS 1 DRQ New data request

SDDATA 16 DATA Speech data

PSB 4860

Data Sheet 69 2000-01-14

2.1.15 Analog Front End Interface

There are two identical interface channels to the analog frontend as shown in figure 36.

The interface is described in chapter 2.4.3 and must be connected to the double codec

PSB 4851.

Figure 36 Analog Front End Interface - Block Diagram

For each signal an amplifier is provided for level adjustment. The incoming signals can

be passed through an optional high-pass (HP). This high-pass (fg=20 Hz) is useful for

blocking DC offsets and should be enabled by default. Furthermore, up to three signals

can be mixed in order to generate the outgoing signals (S2,S4). Table 38 shows the

associated registers.

Table 38 Analog Front End Interface Registers

IFG1 16 IG1 Gain for IG1

IFG2 16 IG2 Gain for IG2

IFS1 1 HP High-pass for S1

IFS1 5 I1 Input signal 1 for IG2

IFS1 5 I2 Input signal 2 for IG2

IFS1 5 I3 Input signal 3 for IG2

IFG3 16 IG3 Gain for IG3

IFG4 16 IG4 Gain for IG4

IFS2 1 HP High-pass for S3

IFS2 5 I1 Input signal 1 for IG4

IFS2 5 I2 Input signal 2 for IG4

IFS2 5 I3 Input signal 3 for IG4

Channel 2

Channel 1

S2I1

line out

line in IG1

IG2

S4I1

loudspeaker

microphone

IG4

HP IG3 HP

PSB 4860

Data Sheet 70 2000-01-14

2.1.16 Digital Interface

There are two almost identical interfaces at the digital side (i.e., the SSDI/IOM®-2

interface described in chapters 2.4.1 and 2.4.2). As shown in figure 37, there are three

channels available if the IOM®-2 interface is used while only channel 1 supports the

SSDI mode

Figure 37 Digital Interface - Block Diagram

Each outgoing signal can be the sum of two signals with no attenuation and one signal

with programmable attenuation (ATT). The attenuator can be used to generate an

artificial side tone if the input (S5, S7, S23) is connected to I3. Each input can be passed

through an optional high-pass (HP) to get rid of any DC part.

Channel 2 of the IOM®-2 can be split into two consecutive 8 bit channels with

independent data streams (A-law or µ-law). It is therefore possible to use either two 16

bit linear channels, a 16 bit channel and an 8 bit channel, a 16 bit channel and two 8 bit

channels or three 8 bit channels.

The associated registers are shown in table 39.

Table 39 Digital Interface Registers

IFS3 5 I1 Input signal 1 for S6

IFS3 5 I2 Input signal 2 for S6

IFS3 5 I3 Input signal 3 for S6

IFS3 1 HP High-pass for S5

Channel 2/3 (IOM®-2 Interface)Channel 1 (SSDI/IOM®-2 Interface)

S7/S23

S8/S24

ATT2/3

ATT1

PSB 4860

Data Sheet 71 2000-01-14

IFS4 5 I1 Input signal 1 for S8

IFS4 5 I2 Input signal 2 for S8

IFS4 5 I3 Input signal 3 for S8

IFS4 1 HP High-pass for S7

IFS5 5 I1 Input signal 1 for S24

IFS5 5 I2 Input signal 2 for S24

IFS5 5 I3 Input signal 3 for S24

IFS4 1 HP High-pass for S23

IFG5 8 ATT1 Attenuation for input signal I3 (Channel 1)

IFG5 8 ATT2 Attenuation for input signal I3 (Channel 2)

IFG6 8 ATT3 Attenuation for input signal I3 (Channel 3)

Table 39 Digital Interface Registers

PSB 4860

Data Sheet 72 2000-01-14

2.1.17 Universal Attenuator

The contains an universal attenuator that can be connected to any signal (e.g. for side-

tone gain in ISDN applications).

Figure 38 Universal Attenuator - Block Diagram

Table 40 shows the associated register.

Table 40 Universal Attenuator Registers

UA 8 ATT Attenuation for UA

UA 5 I1 Input signal for UA

S14

PSB 4860

Data Sheet 73 2000-01-14

2.1.18 Automatic Gain Control Unit

In addition to the universal attenuator with programmable but fixed gain the contains an

amplifier with automatic gain control (AGC). The AGC is preceded by a signal

summation point for two input signals. One of the input signals can be attenuated.

Figure 39 Automatic Gain Control Unit - Block Diagram

Furthermore the signal after the summation point is available. Besides providing a

general signal summation (S16 not used) this signal is especially useful if the AGC unit

provides the input signal for the speech coder. In this case S17 can be used as a

reference signal for voice controlled recording as well as VOX detection and gap coding.

The operation of the AGC is similar to AGCX (AGCR) of the speakerphone. The

differences are as follows:

•No NOIS parameter

•Enable/disable by bit EN

•Slightly different coefficient format

The operation of the AGC is similar to AGCX (ACCR) of the speakerphone. The

differences are as follows:

•No NOIS parameter

•Separate enable/disable control

•Slightly different coefficient format

Furthermore the AGC contains a comparator that starts and stops the gain regulation.

The signal after the summation point (S17) is used as input of a peak detector. For each

maximum value, the peak detector catches the maximum and decays it with the time

constant DEC for decay until the next maximum is detected. The output signal of this

peak detector is compared to a programmable limit LIM. Regulation takes only place

when the filtered signal exceeds the limit.

S16

AGC

ATT

I2S17

PSB 4860

Data Sheet 74 2000-01-14

Table 41 shows the associated registers.

Table 41 Automatic Gain Control Registers

AGCCTL 1 EN Enable

AGCCTL 5 I1 Input signal 1 for AGC

AGCCTL 5 I2 Input signal 2 for AGC

AGCATT 15 ATT Attenuation for I2

AGC1 8 AG_INIT Initial AGC gain/attenuation

AGC1 8 COM Compare level rel. to max. PCM-value

AGC2 8 SPEEDL Change rate for lower levels

AGC2 8 SPEEDH Change rate for higher level

AGC3 7 AG_ATT Attenuation range

AGC3 8 AG_GAIN Gain range

AGC4 7 DEC Peak detector time constant

AGC4 8 LIM Comparator minimal signal level

AGC5 7 LP AGC low pass time constant

PSB 4860

Data Sheet 75 2000-01-14

2.1.19 Equalizer

The PSB 4860 also provides an equalizer that can be inserted into any signal path. The

main application for the equalizer is the correction to the frequency characteristics of the

microphone, transducer or loudspeaker.

The equalizer consists of an IIR filter followed by an FIR filter as shown in figure 40.

Figure 40 Equalizer - Block Diagram

The coefficients A1-A9, B2-B9 and C1 belong to the IIR filter, the coefficients D1-D17 and

C2 belong to the FIR filter. Table 42 shows the registers associated with the equalizer.

Table 42 Equalizer Registers

FCFCTL 1 EN Enable

FCFCTL 5 I Input signal for equalizer

FCFCTL 6 ADR Filter coefficient address

FCFCOF 16 Filter coefficient data

z-1 z-1 z-1

A1 A2 A9

z-1

B2B9

z-1 z-1 z-1

D1 D2 D17

S18

FIR

IIR

PSB 4860

Data Sheet 76 2000-01-14

Due to the multitude of coefficients the PSB 4860 uses an indirect addressing scheme

for reading or writing an individual coefficient. The address of the coefficient is given by

ADR and the actual value is read or written to register FCFCOF.

In order to ease programming the PSB 4860 automatically increments the address ADR

after each access to FCFCOF.

Note: Any access to an out-of-range address automatically resets FCFCTL:ADR.

PSB 4860

Data Sheet 77 2000-01-14

2.1.20 Peak Detector

The peak detector (figure 41) is usually not used in normal operation. It provides,

however, an easy means to verify the minimum or maximum signal level of any signal Si

within the . The peak detector stores either the maximum or the minimum signal value of

the observed signal I1 in the register PDDATA since the last read access to this register.

Therefore it is not only possible to determine the absolute level of the signal but it can

also be checked whether a DC offset is present. This can be done by first scanning for

the maximum and then for the minimum value. If the minimum value is not

(approximately) the negated positive value then a DC offset is present. The peak

detector should be disabled if not needed.

Figure 41 Peak Detector - Block Diagram

The register PDDATA gives the maximum or minimum integer depending on the mode

selected by bit MM. As an example it may be assumed that the detection of the maximum

is selected. Then with enabling the detector and with each read access to register

PDDATA, PDDATA is set to the smallest possible value, which is the negative maximum

integer. With each new maximum detected on signal I1, this maximum is provided by

PDDATA.

Table 43 Peak Detector Registers

PDCTL 1 EN Peak Detector Enable

PDCTL 1 MM Minimum/Maximum selection

PDCTL 5 I1 Input signal selection

PDDATA 16 Min/Max signal value since last read access

Peak

SCI

I1 Detector

PSB 4860

Data Sheet 78 2000-01-14

PSB 4860

Data Sheet 79 2000-01-14

2.2 Memory Management

Memory Managemen t

Memory Managemen t - Gen eral

This section describes the memory management provided by the . As figure 42 shows,

three units can access the external memory. During recording, the speech coder can

write compressed speech data into the external memory. For playback, the speech

decoder reads compressed speech data from external memory. In addition, the

microcontroller can directly access the memory by the SCI interface.

Figure 42 Memory Management - Data Flow

The memory is organized as a file system. The offers one directory for messages and

one for voice prompts. These two directory have a similar structure. Figure 43 illustrates

the basic structure of the message directory.

Figure 43 Memory Management - Structure of Message Directory

The message directory contains 255 file descriptors, each describing one file. See the

next section for details on files.

Speech Decoder

Speech Coder

MemorySCI

length (0-65535)

user data (16 bits)

file descriptor 1

file descriptor 255

file descriptor n

file descriptor (R/W)directory

RTC1 (16 bits)

RTC2 (16 bits)

PSB 4860

Data Sheet 80 2000-01-14

Figure 44 illustrates the basic structure of the voice prompt directory.

Figure 44 Memory Management - Structure of Voice Prompt Directory

The voice prompt directory contains 254 file descriptors. To each file descriptor a voice

prompt file can be attached. The file with number 255 is a special file. If this file is

selected, up to 2048 phrases can be used.

The directories must be created after each power failure for volatile R/W-memory. All file

descriptors are cleared (all words zero). For non-volatile memory, the directories have to

be created only once. If the directories already exist, the memory just has to be activated

after a reset. The file descriptors are not changed in this case.

For detailed information on the structure of the directories, please refer to the appropriate

application note.

2.2.1 File Definition and Access

A file is a linear sequence of units and can be accessed in two modes: binary and audio.

In binary mode, a unit is a word (16 bits). In audio mode, a unit is a variable number of

words representing 30 ms of uncompressed speech. A file can contain at most 65535

units. Figure 45 shows an audio file containing 100 audio units. The length of the

message is therefore 3 s.

Figure 45 Audio File Organization - Example

file descriptor 1

file descriptor 254

file descriptor n

directory

phrase selected

phrase 0

phrase 2048

...

Hi Jack, this is Tom. Please call me back tomorrow.

099

3 s

PSB 4860

Data Sheet 81 2000-01-14

Figure 46 shows a binary file of 11 words containing a phonebook (with only two entries).

Figure 46 Binary File Organization - Example

The file 255 in the voice prompt area offers a convenient handling of phrases. The large

number of up to 2048 different phrases can be handled. Each phrase can be of arbitrary

length. In contrast to voice prompt files, phrases can be combined by the controller in

any sequence without intermediate noise or gaps.

Figure 47 shows a phrase file containing a total of five phrases.

Figure 47 Phrase File Organization - Example

To access a file, the file must first be opened with the following information:

1. memory space (i.e., message or voice prompt directory)

2. file number

3. access mode

These parameters remain effective until the next file open command is given. All other

files are closed and cannot be accessed. The file with file number 0 does actually not

exist. Opening this file closes all existing files.

The provides four registers for file access and three bits within the STATUS register.

Table 44 shows these registers.

Table 44 Memory Management Registers

FCMD 16 Command to be executed

FCTL 16 Access mode and file number

FDATA 16 Data transfer and additional parameters

FPTR 16 (11) File pointer (phrase selector)

STATUS 16 Busy, Error and Phrase Queuing indication

544F 4D20 3535 3534 3330 004A 4143 4B20 5555 5538 3131

0101

M 555430 JACK 555811

one two you have messages left friday

01 4

PSB 4860

Data Sheet 82 2000-01-14

File commands are written to the FCMD register. The busy bit in the STATUS register is

set within 150 µs1) (simultaneously with RDY). Some commands require additional

parameters which have to be written into the specified registers prior to the command.

Data transfer is done via the register FDATA (both reading and writing).

The status register contains two flags (table 45) to indicate if a file command is currently

being executed (STATUS:BSY) and if the last file command has terminated without error

(STATUS:ERR). A new command must not be written to FCMD while the last one is still

running (STATUS:BSY=1). The only commands that can be aborted are Compress File

and Garbage Collection.

Writing a valid command to FCMD also resets the error bit in the status register.

Table 46 shows the parameters defining the access mode and the access location. All

parameters can only be written when no file command is currently active. New

parameters become effective after the completion of a file open command. If another unit

(e.g. speech coder) accesses the file, the file pointer is updated automatically. Then, the

controller can monitor the progress of recording or playing by reading the file pointer.

2.2.2 User Data Word

The user data word is part of a file descriptor as illustrated in figures 43 and 44. It offers

an easy way to store some information on the file.

1) When the speakerphone is enabled it may take up to 250 µs to set the BSY and the RDY bit.

Table 45 Memory Management Status

STATUS 1 BSY File command or decoder/encoder still running

STATUS 1 ERR File command completed/aborted with error

STATUS 1 PQE Phrase Queue Empty

Table 46 Memory Management Parameters

FCTL 1 MS Memory space (R/W or voice prompt)

FCTL 1 MD Access mode (audio or binary)

FCTL 1 TS Write timestamp (file open only)

FCTL 1 UD Write User Data word

FCTL 8 FNO File number (active file)

FPTR 16 File pointer or phrase selector

PSB 4860

Data Sheet 83 2000-01-14

A user data word consists of 12 bits that can be read or written by the user, one bit (R)

that is reserved for future use and three read-only bits (D,M,E) which indicate the status

of a file.

If D is set, the file is marked for deletion and should not be used any more. This bit is

maintained by the for housekeeping. The M bit indicates the file type (audio/binary) while

the E bit indicates an existing file. The E bit may be used after an activation to decide

which files are actually valid and contain data.

2.2.3 High Level Memory Management Commands

This section describes each of the high level memory management commands in detail.

These commands are sufficient for normal operation of an answering machine. In

addition, there are low level commands (section 2.2.4). These commands are only

required for special tasks like in-system reprogramming of the voice prompt area.

Memory Managemen t - Command s

2.2.3.1 Initialize

This command configures the memory. In case of Flash, the message and the voice

prompt directory are created. It is possible to reserve 4 kB of memory which is

subsequently excluded from the standard file management. This reserved area can then

be used for fast data backup (see emergency mode). The reserved 4kB memory block

is called emergency block.

In case of ARAM/DRAM, only the message directory is created since voice prompts are

assumed to be kept in an additional ROM. The can either create an empty directory from

scratch or leave the first n files of an existing directory untouched while deleting the

remaining files. This option is useful if due to an unexpected event (e.g. power loss

during recording) some data are corrupted. In this case vital system information can still

be recovered if it has been stored in the first files. Furthermore, if bit MV indicates a voice

prompt directory, the voice prompt memory is scanned for a valid directory.

In any case, with the command Initialize the checks the external memory configuration

and delivers the size of usable memory in 1 kByte blocks.

15 0

D M E R User Definable

Table 47 Initialize Memory Parameters

FCMD 5 CMD Initialize command code

FCMD 1 IN Confirmation for Initialization, must be set

FCMD 1 REB Reservation of 4 kB of memory

PSB 4860

Data Sheet 84 2000-01-14

Possible Errors:

•no R/W memory found

•more than 55 bad blocks (flash and ARAM)

•voice prompt directory requested, but not detected

•wrong hardware connection

Note: This command should be given only once for flash devices. Only for ATMEL flash

devices w/o voice prompts, this command may be issued multiple times.

2.2.3.2 Initialize Message Memory

This command is only allowed if Flash is used and assumes that Initialize has been

executed successfully. This command deletes all messages and generates a new

message memory by using vital data of the voice prompt directory. The voice prompt

area and therefore the prompt files and phrases are left untouched. For a successful

execution, the voice prompts must have been prepared for this. If for example the

download tools SPROMPT, APROMPT, or TPROMPT are used they must have been

started with the option -saverw.

The command Initialize Message Memory may help for recovery from a fatal system

crash, which has damaged data in the flash memory. The emergency block (4 kB of

memory that may have been reserved with the command Initialize) keep untouched.

FCTL 8 FNO 0: delete no file

1: delete all files

n: delete starting with file n

CCTL 2 MT Type of R/W memory (DRAM, Flash)

CCTL 1 MQ Quality of R/W memory (Audio, Normal)

CCTL 1 MV Scan for voice prompt directory

CCTL 2 SFT Serial Flash Type

CCTL 2 CDIV Serial Flash Clock Speed

Table 48 Initialize Memory Results

FDATA 16 Number of usable 1kByte blocks in R/W memory

Table 47 Initialize Memory Parameters

PSB 4860

Data Sheet 85 2000-01-14

Possible Errors:

•file open

Note: This file command must be followed by the file command Activate.

2.2.3.3 Activate

This command activates an existing directory, sets the external memory configuration

and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt

memory space is scanned for a valid directory.

In case of ARAM/DRAM, the checks the consistency of the directory in the message

memory space. It returns the first file that contains corrupted data (if any). If corrupted

data is detected an initialization should be performed with the same file number as an

input parameter.

Table 49 Initialize Memory Parameters

FCMD 5 CMD Initialize command code

FCMD 1 IN Confirmation for Initialization, must be set

CCTL 2 MT Type of R/W memory (DRAM, Flash)

CCTL 1 MQ Quality of R/W memory (Audio, Normal)

CCTL 2 SFT Serial Flash Type

CCTL 2 CDIV Serial Flash Clock Speed

Table 50 Activate Memory Parameters

FCMD 5 CMD Activate command code

CCTL 2 MT Type of R/W memory (DRAM, Flash)

CCTL 1 MQ Quality of R/W memory (Audio, Normal)

CCTL 1 MV Voice prompt directory available

CCTL 2 SFT Serial Flash Type

CCTL 2 CDIV Serial Flash Clock Speed

CCTL 1 RD Remap Directory (see Garbage Collection)

PSB 4860

Data Sheet 86 2000-01-14

Possible error conditions:

•no memory connected

•no directory found

•device ID wrong (flash only)

•corrupted files found (see FCTL:FNO)

•directory corrupted

This command can have three types of results as shown in table 52.

Note: If the Flash is configured, the file command Activate must be used for setting up

the memory after power-up.

2.2.3.4 Check Voice Prompt Data Integrity

With this command, the PSB 4860 calculates a CRC value of voice prompt data and

phrases contained in the voice prompt directory. The result can be read by the

microcontroller in register FDATA. This command can be used for verification of the

downloaded phrases during production.

Table 51 Activate Memory Results

FDATA 16 Number of usable 1 kByte blocks in R/W memory

FCTL 8 FNO n: number of first corrupted file (DRAM/ARAM only)

Table 52 Activate Memory Result Interpretation

Result STATUS:

ERR

FCTL:

FNO

Comment

no error 0 0 Command successful, memory activated.

soft error 1 n The first n-1 files are O.K. The memory is activated.

hard error 1 1 The memory is not activated due to a hard error.

Table 53 Read Data Parameters

FCMD 5 CMD Check Voice Prompt Data Integrity Command Code

PSB 4860

Data Sheet 87 2000-01-14

Possible error conditions:

•file open

•no activate performed

•no prompt directory existing

2.2.3.5 Open File

A specific file is opened for subsequent accesses with the specified access mode.

Opening a new file automatically closes the currently open file and clears the file pointer.

Opening file number 0 can be used to close all physical files. If the TS flag is set, the

current contents of RTC1 and RTC2 is written to the appropriate fields of the file

descriptor in order to provide a time stamp. If the UD flag is set, the contents of FDATA

is written to the user data word. Note that for Samsung and Toshiba Flash memory, bits

within the user data word can only be changed from 0 to 1.

Possible error conditions:

•selected file marked for deletion, but not yet deleted by garbage collection

•new file selected, but memory full

•<fno> exceeds number of prompts (in voice prompt space only)

•wrong access mode selected for existing file

•<fno> has been recompressed partially

Table 54 Read Data Results

FDATA 16 16 bit CRC value

Table 55 Open File Parameters

FCMD 5 CMD Open command code

FCTL 1 MS Memory space (R/W, voice prompt)

FCTL 1 MD Access mode (audio or binary)

FCTL 1 TS Write time stamp

FCTL 1 UD Write user data word

FCTL 8 FNO File number <fno>

FDATA 12 User data word (if FCTL:UD set)

PSB 4860

Data Sheet 88 2000-01-14

Note: In case of Samsung and Toshiba Flash memory, existing ones in the entries

RTC1/RTC2 of the file descriptor cannot be altered. Therefore TS should be set

only once during the lifetime of a file.

2.2.3.6 Open Next Free File

The next free file is opened for subsequent write accesses with the specified access

mode. The search starts at the specified file number. If the TS flag is set, the current

content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in

order to provide a timestamp. If a free file has been found, the file is opened and the file

number is returned in FCTL:FNO. Otherwise an error is reported. The user data word

can be written optionally. Note that for flash memory, bits within the user data word can

be only changed from 0 to 1.

Possible error conditions:

•no unused file found

•memory full

Note: In case of Samsung and Toshiba Flash memory existing ones cannot be altered.

Therefore TS should be set only once during the lifetime of a file.

Note: R/W-memory must be selected. Otherwise the result is unpredictable.

Table 56 Open Next Free File Parameters

FCMD 5 CMD Open Next Free File command code

FCTL 1 MD Access mode (audio or binary)

FCTL 1 TS Write timestamp

FCTL 8 FNO Starting point (>0)

FCTL 1 UD Write user data word

FDATA 12 User data word (if FCTL:UD set)

Table 57 Open Next Free File Results

FCTL 8 FNO File number

PSB 4860

Data Sheet 89 2000-01-14

2.2.3.7 Seek

The file pointer of the currently opened file is set to the position specified by FPTR. If the

current file is the phrase file the starts the speech decoder immediately after the seek is

finished (the bit SDCTL:EN is set automatically). All other settings of the decoder remain

unaffected.

When the PSB 4860 starts playing a phrase it automatically clears the FDATA register

and sets the PQE status bit. Three audio blocks (90 ms) before the current phrase ends,

the PSB 4860 starts to check bit 15 of the FDATA register. Then, this bit must not be

altered until the phrase ends. If this bit is set, the PSB 4860 automatically appends the

phrase denoted by the lower eleven bits of FDATA to the current phrase without delay.

Once the new phrase has started the PSB 4860 clears FDATA and sets PQE again and

the next phrase can be written by the controller. Writing FDATA automatically resets the

PQE bit. The BSY bit of the STATUS register is set immediately and reset when the last

phrase has been finished.

When the last phrase of a sentence is played, a phrase containing 120 ms silence should

be appended. Otherwise, the last 120ms of the last phrase are not played.

Possible error conditions:

•file pointer out of range

•phrase number out of range

•wrong CCTL register content (e.g.: voice prompt directory specified but not present)

2.2.3.8 Cut File

All units starting with the unit addressed by the file pointer are removed from the file. If

all units are deleted the file is marked for deletion (see user data word). However, the

associated file descriptor and memory space are released only after a subsequent

garbage collection.

Table 58 Seek Parameters

FCMD 5 CMD Seek command code

FPTR 16 (11) File pointer (phrase selector)

FDATA 16 Next phrase (if bit 15 is set)

PSB 4860

Data Sheet 90 2000-01-14

Possible error conditions:

•file pointer out of range

•voice prompt memory selected

2.2.3.9 Delete Multiple Files

All files starting with the file number greater than or equal to the specified file number are

marked for deletion. This command is intended to erase all messages with the exception

of one or more outgoing messages. Note that the associated file descriptors and memory

space are released only after a subsequent garbage collection.

Possible error conditions:

•file open

•<fno> equal to 0

2.2.3.10 Compress File

An audio file can be recompressed using a lower bit rate than the current bit-rate of the

file. This reduces the file size. The memory space is released after a subsequent

garbage collection. This command can be aborted at any time and resumed later without

loss of information. The target bit rate is selected by the speech encoder control register.

The starting point of the recompression can be programmed as well. Prior to this

command all files must be closed. Table 61 shows the parameters for this command.

Table 59 Cut File Parameters

FCMD 5 CMD Cut command code

FPTR 16 Position of first unit to be deleted (the first unit of a

message has number 0)

Table 60 Delete Multiple Files Parameters

FCMD 5 CMD Cut command code

FCTL 8 FNO First file number to be deleted

Table 61 Compress File Parameters

FCMD 5 CMD Compress command code

SCCTL 2 Q0, Q1 Target bit rate

PSB 4860

Data Sheet 91 2000-01-14

Possible error conditions:

•<fno> invalid

•another file currently open

•binary file selected

Note: After power fail during execution of this command, the file cannot be guaranteed

to be a valid file.

2.2.3.11 Memory Status

This command returns the number of available 1 kByte blocks in R/W memory space.

Possible error conditions:

•file open

2.2.3.12 Garbage Collection

This command initiates a garbage collection. Until a garbage collection, files that are

marked for deletion still occupy the associated file descriptor and memory space. After

the garbage collection these file descriptors and the associated memory space are

available again. This command can optionally remap the directory. In this mode the

remaining file descriptors are remapped to form a contiguous block starting with file

number 1. The original order is preserved. This command requires that all files are

closed, i.e., file 0 is opened. Independently of the selected directory only the read/write

directory is used. The command can be aborted any time and resumed later on by

FCTL 8 FNO File number <fno>

FPTR 16 Start of recompression within file

Table 62 Memory Status Parameters

FCMD 5 CMD Memory status code

Table 63 Memory Status Results

FDATA 16 FREE Number of free blocks

Table 61 Compress File Parameters

PSB 4860

Data Sheet 92 2000-01-14

issuing the command again. Note, that an aborted recompression command must be

completed before a garbage collection can be performed.

Possible error conditions:

•file open

•recompression to be resumed

2.2.3.13 Access File Descriptor

The file descriptors of the message memory can be accessed by two write and four read

commands. The file descriptors of the voice prompt memory can be read but must not

be written. The file is not affected by any of these commands.

The two write commands are: Write File Descriptor - RTC1 / RTC2, and Write File

Descriptor - User. With the command Write File Descriptor - RTC1 / RTC2, two values

(RTC1 and RTC2) are written. This command can only be executed when no file is

opened. With the command Write File Descriptor - User, only one value (User DATA) is

written. This command can only be executed for a currently opened file.

There are four read commands, one for each of the file descriptor entries: User Data,

RTC1, RTC2, Length. These commands can be executed for opened files or, when all

files are closed, for the file with file number <fno>.

Table 64 Garbage Collection Parameters

FCMD 5 CMD Garbage Collection Command Code

FCMD 1 RD Remap Directory

Table 65 Write File Descriptor Parameters

FCMD 5 CMD Write Access command code

FDATA 16 User data or RTC1

FPTR 16 RTC2

FCTL 16 FNO File number

Table 66 Read File Descriptor Parameters

FCMD 5 CMD Read Access command code

FCTL 16 FNO File number

PSB 4860

Data Sheet 93 2000-01-14

Possible error conditions:

•file open for command Write File Descriptor - RTC1 / RTC2

•file not open for command Write File Descriptor - User

Note: In case of Samsung and Toshiba Flash memory, bits already set to 1 cannot be

altered.

Note: Do not write with these commands to the voice prompt directory.

2.2.3.14 Read Data

This command can be used in binary access mode only. A single word is read at the

position given by the file pointer. The file pointer can be set by the Seek command. The

file pointer is advanced by one word automatically.

Possible error conditions:

•file pointer out of range

•audio file selected

2.2.3.15 Write Data

This command can be used in binary access mode only. A single word is written at the

position of the file pointer. The file pointer is advanced by one word automatically. Note

that for Samsung and Toshiba Flash memories, only zeroes can be overwritten by ones.

This restriction occurs only if an already used value within an existing file is to be

overwritten.

Table 67 Access File Descriptor Results

FDATA 16 Content of selected entry

Table 68 Read Data Parameters

FCMD 5 CMD Read Data Command Code

Table 69 Read Data Results

FDATA 16 Data word

PSB 4860

Data Sheet 94 2000-01-14

Possible error conditions:

•file pointer out of range (for existing files only)

•voice prompt memory selected

•memory full

•audio file selected

Table 70 Write Data Parameters

FCMD 5 CMD Access Mode Command Code (including mode)

FDATA 16 Data word

PSB 4860

Data Sheet 95 2000-01-14

2.2.4 Low Level Memory Management Commands

These commands allow the direct access of any location (single word) of the external

memory. Additionally it is possible to erase any block in case of a Samsung or Toshiba

Flash device. These commands must not be used during normal operation as they may

interfere with the file system. No file must be open when one of these commands is

given.

The primary use of these commands is the in-system programming of a flash device with

voice prompts. Please refer to the appropriate Application Note for usage of the following

commands.

2.2.4.1 Set Address

This command sets the 24 bit address pointer APTR. Only the address bits A8-A23 are

set, the address bits A0-A7 are automatically cleared.

Possible error conditions:

•file open

2.2.4.2 DMA Read

This command initializes the read procedure. This command must be given before the

read command can be issued. Table 72 shows the parameter for this command.

The overall procedure to read data is as follows. All accesses must be perfomed in

handshake mode, i.e., the RDY must go active before the next step can be taken:

1. Write address to register FDATA.

2. Write command Set Address to the command register FCMD.

3. Initialize read with handshake by writing command DMA Read to FCMD.

4. Start read of a word by transmitting 5A00H via SCI.

5. Read data via SCI similar to the Data Read Access as described in chapter 2.4.4.

Table 71 Set Address Parameters

FCMD 5 CMD Set Address command code

FDATA 16 ADR Address bits A8-A23 of address pointer APTR

Table 72 DMA Read Parameters

FCMD 5 CMD DMA Read command code (initialization)

PSB 4860

Data Sheet 96 2000-01-14

6. Repeat 3) and 4) as often as necessary. The address is incremented automatically.

Neglect BSY bit for these transfers but consider the RDY bit (no interrupt is issued).

7. Finish read access by transmitting 5F00H via the SCI

Possible error conditions:

•file open

2.2.4.3 DMA Write

This command initializes the write procedure. This command must be given before the

write command can be issued. Table 73 shows the parameter for this command.

The overall procedure to write data is as follows. All accesses must be perfomed in

handshake mode, i.e., the RDY must go active before the next step can be taken::

1. Write address to register FDATA.

2. Write command Set Address to the command register FCMD.

3. Initialize write with handshake by writing command DMA Write to FCMD.

4. Write data via SCI similar to the Register Write Access as described in chapter 2.4.4

but use 4500H as command word.

5. Repeat 3) as often as necessary. The address is incremented automatically. Neglect

BSY bit for these transfers but consider the RDY bit (no interrupt is issued).

6. Finish write access with a last Register Write Access (after the last word has been

written) with 4F00H as command word.

Possible error conditions:

•file open

Note: If flash memory is connected the actual write is only performed when the last word

within a page is written. Until then the data is merely buffered in the flash device.

Please check the flash memory data sheets on page size.

2.2.4.4 Block Erase

This command erases the physical block of a Samsung of Toshiba Flash memory, which

includes the address given by APTR. The actual amount of memory erased by this

command depends on the block size of the Flash device. Table 74 shows the

parameters for this command.

Table 73 DMA Write Parameters

FCMD 5 CMD DMA Write command code (initialization)

PSB 4860

Data Sheet 97 2000-01-14

Possible error conditions:

•file open

•ARAM/DRAM configured

Table 74 Block Erase Parameters

FCMD 5 CMD Block Erase command code

PSB 4860

Data Sheet 98 2000-01-14

2.2.5 Execution Time

The execution time of the file commands is determined by three factors:

1. Memory configuration

2. Memory state

3. Individual characteristics of the memory devices

Therefore there is no general formula for an exact calculation of the execution time for

file commands. For ARAM/DRAM the last item is not significant as the memory access

timing is always fixed and no additional delay is incurred for erasing memory blocks.

However, the amount of memory has significant impact on the initialization in case of

ARAM and flash.

For flash devices the particular location of a write access in combination with the internal

organization of the memory device may result in a block erase and subsequent write

accesses in order to copy data. In this case the individual erase and write timing of the

attached devices also prolongs the execution time.

Table 75 gives an indication of the execution time for a typical memory configurations.

The times for the Samsung Flash KM29W040AT are listed.

Table 75 Execution Times

Command max typical

Initialize < 3 s 0.5 s

Activate < 3 s 1 s

Open File /Open Next Free File

(no change to file or file descriptor)

< 26 ms 1 ms

Open File /Open Next Free File

(change to file or file descriptor)

< 160 ms -

Seek (within 4 MBit File) < 0.5 s -

Seek (within phrase file) < 1 ms -

Cut File < 5 ms 0.5 ms

Compress File #units * 30 ms #units * 30 ms

Access File Descriptor < 10 ms 1 ms

Memory Status < 10 ms 0.6 ms

Read/Write Data < 10 ms 125 us

Garbage Collection < 3 s 1 s

PSB 4860

Data Sheet 99 2000-01-14

2.2.6 Special Notes on File Commands

1. No MMU commands must be inserted between opening a file and writing data to it,

either by writing data to a binary file or by enabling the coder for audio files.

Therefore reading or writing the file descriptor is only allowed after all data writing has

happened.

2. If an audio file has been opened for replay, a Write File Descriptor Command must be

followed by a Seek command before the decoder can be enabled.

PSB 4860

Data Sheet 100 2000-01-14

PSB 4860

Data Sheet 101 2000-01-14

2.3 Miscellaneous

Miscellaneous

2.3.1 Real Time Clock

The supplies a real time clock which maintains time with a resolution of one second and

a range of up to one year. There are two registers which contain the current time and

date (table 76).

The real time clock maintains time during normal mode and power down mode only if the

auxiliary oscillator OSC is running and the RTC is enabled.

Note: Writing out-of-range values to RTC1 and RTC2 results in undefined operation of

the RTC

2.3.2 SPS Control Register

The two SPS outputs (SPS0, SPS1) can be used either as general purpose outputs,

speakerphone status outputs, as extended address outputs for Voice Prompt EPROM

or as status register outputs. This is programmed with the bits MODE. Table 77 shows

the associated register.

When used as status register outputs, the status register bit at position POS appears at

SPS0 and the bit at position POS+1 appears at SPS1. This mode of operation can be

used for debugging purposes or direct polling of status register bits. The RDY bit cannot

be observed via SP0 or SP1.

Table 76 Real Time Clock Registers

RTC1 6 SEC Seconds elapsed

RTC1 6 MIN Minutes elapsed

RTC2 5 HR Hours elapsed

RTC2 11 DAY Days elapsed

Table 77 SPS Register

SPSCTL 1 SP0 Output Value of SPS0

SPSCTL 1 SP1 Output Value of SPS1

SPSCTL 3 MODE Mode of Operation

SPSCTL 4 POS Position for status register window

PSB 4860

Data Sheet 102 2000-01-14

2.3.3 Reset and Power Down Mode

The can be in either reset mode, power down mode or active mode. During reset the

clears the hardware configuration registers and stops both internal and external activity.

The address lines MA0-MA15 provide a weak low until they are actually used as address

lines (strong outputs) or auxiliary port pins (I/O). In reset mode the hardware

configuration registers can be read and written. With the first access to a read/write

operation takes place. By setting the power down bit (PD) the can be brought to power

down mode.

In power down mode the main oscillator is stopped and, depending on

HWCONFIG2:PPM), the memory control lines are released (weak high). Given that the

auxiliary oscillator is still active and enabled (bit OSC in register HWCONFIG0), then

depending on the configuration (ARAM/DRAM, APP), the may still generate external

activity (e.g. refresh cycles). The enters active mode again upon an access to a read/

write register. Figure 48 shows a state chart of the modes of the .

Figure 48 Operation Modes - State Chart

2.3.4 Interrupt

The can generate an interrupt to inform the host of an update of the STATUS register

according to table 79. An interrupt mask register (INTM) can be used to disable or enable

the interrupting capability of each bit of the STATUS register except ABT individually.

Table 78 Power Down Bit

CCTL 1 PD power down mode

Reset

Active

Mode

Power Down

Mode

CCTL.PD=1

R/W reg. access

RST=1RST=1

R/W reg. access

PSB 4860

Data Sheet 103 2000-01-14

An interrupt is internally generated if any combination of these events occurs and the

interrupt is not masked. This internal interrupt is cleared only when the host executes the

Data Read Access with Interrupt Acknowledge command. The internal interrupt is

cleared when the first bit of the STATUS register is output. If a new event occurs while

the host reads the status register, the status register is updated after the current access

Table 79 Interrupt Source Summary

STATUS

(old)

STATUS

(new)

Set by Reset by

RDY=0 RDY=1 Command completed Command issued

CIR=0 CIR=1 New Caller ID byte requested CISDATA written

CIS=0 CIS=1 Stop bits are sent CISDATA written

CIA=0 CIA=1 New Caller ID byte available CIDCTL0 read

CD=0 CD=1 Carrier detected Carrier lost

CD=1 CD=0 Carrier lost Carrier detected

CPT/UTD=0 CPT/UTD=1 CPT or UT detected CPT or UT lost

CPT/UTD=1 CPT/UTD=0 CPT or UT lost CPT or UT detected

CNG=0 CNG=1 Fax calling tone detected Module disabled

DTV=0 DTV=1 DTMF tone detected DTMF tone lost

DTV=1 DTV=0 DTMF tone lost DTMF tone detected

ATV=0 ATV=1 Alert tone detected Alert tone lost

ATV=1 ATV=0 Alert tone lost Alert tone detected

DA=0 DA=1 Speech coder data in SCDATA Data read by uC

DRQ=0 DRQ=1 Speech decoder requests data Data written by uC

BSY=1 BSY=0 File command completed New command issued

SD=0 SD=1 Speech activity detected Speech activity lost

SD=1 SD=0 Speech activity lost Speech activity detected

GAP=0 GAP=1 Gap start Gap end

GAP=1 GAP=0 Gap end Gap start

VOX=0 VOX=1 VOX detected Voice detected

VOX=1 VOX=0 Voice detected VOX detected

PQE=0 PQE=1 Phrase Queue Empty FDATA written

IPP=0 IPP=1 Event at APP input pin detected Register DHOLD read

PSB 4860

Data Sheet 104 2000-01-14

is terminated and a new interrupt is internally generated immediately after the access

has ended.

2.3.5 Abort

If the cannot continue the current operations in progress (e.g. due to a transient loss of

power) it stops operation and initializes all read/write registers to their reset state. After

that it sets the ABT bit of the STATUS register and generates an interrupt. The discards

all commands with the exception of a write command to the revision register while ABT

is set. Only after the write command to the revision register (with any value) the ABT bit

is reset and a reinitialization can take place.

2.3.6 Revision Register

The contains a revision register. This register is read only and does not influence

operation in any way. A write to the revision register clears the ABT bit of the STATUS

2.3.7 Hardware Configuration

The can be adapted to various external hardware configurations by four special

registers: HWCONFIG0 to HWCONFIG3. These registers are usually only written once

during initialization and must not be changed while the is in active mode. It is mandatory

that the programmed configuration reflects the external hardware for proper operation.

Special care must be taken to avoid I/O conflicts or excess current by enabling inputs

without an external driving source. Table 80 can be used as a checklist.

2.3.8 Frame Synchronization

The locks itself to either an externally supplied frame sync signal or generates the frame

sync signal itself. This internal reference frame sync signal is called master frame sync

(MFSC). Table 81 shows how AFECLK and MFSC are derived by the . The bits ACT and

MFS are contained in the hardware configuration registers. The bit MFS controls

whether the frame sync is taken from external or generated internally. The bit ACT

enables the clock tracking and is explained in the sequel section.

Table 80 Hardware Configuration Checklist

HWCONFIG0 PFRDY 1 FRDY must not float

HWCONFIG0 OSC 1 OSC1/2 must be connected to a crystal

HWCONFIG0 ACS 1 CLK must not float (tie low if no clock present)

HWCONFIG1 MFS 1 FSC must not float (tie low if no clock present)

HWCONFIG1 ACT 1 FSC must not float (tie low if no clock present)

PSB 4860

Data Sheet 105 2000-01-14

2.3.9 Clock Tracking

The can adjust AFECLK and AFEFSC dynamically to a slightly varying FSC. This mode

requires that both AFEFSC and FSC are nominally running at the same frequency (8

kHz). It is enabled with the bit ACT in the hardware configuration registers.

2.3.10 AFE Clock Source

The can also derive its AFECLK from an externally provided clock CLK. This can be

enabled with the bit ACS in the hardware configuration registers. The external clock CLK

is expected to run at 13.824 MHz.

Table 81 Frame Synchronization Selection

ACT MFS AFECLK MFSC Application

0 0 XTAL AFEFSC Analog featurephone

0 1 - FSC ISDN stand-alone

1 1 XTAL FSC DECT with PSB 4851

PSB 4860

Data Sheet 106 2000-01-14

2.3.11 Restrictions and Mutual Dependencies of Modules

There are some restrictions concerning the modules that can be enabled at the same

time. Table 82 and 83 summarize these restrictions. A checked cell indicates that the two

modules (defined by the row and the column of the cell) must not be enabled at the same

time.

Examples:

•The line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder

is running at slow speed.

•If the DTMF detector is running, the compress file command (C) must not be

executed.

Table 82 Dependencies of Modules - 1

Speech

Encoder

Speech

Decoder

Line EC

(24 ms)

Acoustic

DTMF

Detector

File

Command

Speech Encoder X X X A

Speech Decoder X X1)

1) if Speech Decoder is running at slow speed

X A

Line EC (24 ms) X X1) X B

Acoustic EC X X X B

DTMF Detector C

File Command A A B B C

Table 83 Dependencies of Modules - 2

Caller ID

Sender

Caller ID

Decoder

Alert

Tone Det

CPT

Detector

UTD

Detector

File

Command

CID Sender X C

CID Decoder X X1)

1) if CIDCTL0:CM is set.

C1)

AT Detector X1)

CPT Detector X

UPT Detector X

File Command C C1)

PSB 4860

Data Sheet 107 2000-01-14

There are three classes of file commands denoted by the letters A, B and C. Table 84

shows the definitions of these classes:

A further restriction occurs due to the resource costs of the simultaneously applied

modules. Each module currently in use takes up some resources. The percentage a

module needs from the totally available resources is listed in table 85. The sum of

resources all applied modules must never exceed 100. The amounts listed on table 85

are valid for 31.104 MHz operating frequency. If the PSB 4860 runs at a higher or lower

frequency, the resource costs decrease or increase accordingly.

Thus, it may be necessary to restrict the length of the FIR filter of the echo cancellation

unit if several other units are operating at the same time.

Table 84 File Command Classes

Class Description

A All commands

B Background commands (Activate, Recompress, Garbage Collection, Initialize,

Initialize Message Memory, Delete Multiple Files) and

open commands (Open, Open Next Free File)

C Recompress command

Table 85 Module Weights

Module Weight Comment Example 1 Example 2

Equalizer 2.8 X X

CPT Detector 5.6

Caller ID Decoder 4.2 CM = 0 X

Caller ID Decoder 10.9 CM = 1

CNG Detector 2.6

DTMF Generator 2.2 X

Echo Cancellation 52.7 127 taps (16 ms)

Echo Cancellation 63.1 255 taps (32 ms) X

Echo Cancellation 73.6 383 taps (48 ms)

Echo Cancellation 84.0 511 taps (64 ms) X

Line Echo Cancellation 12.8 normal mode

Line Echo Cancellation 25.5 extended mode

Line Echo Cancellation 14.3 superior mode X

Universal Attenuator 0.2

PSB 4860

Data Sheet 108 2000-01-14

Example:

•For an analog phone echo cancellation, DTMF tone generation, caller ID reception,

and line echo cancellation are necessary. The system uses the PSB 4851 and the

equalizer to linearize the loudspeaker. In this case the sum of all weights without echo

cancellation is 34.4. Therefore 255 taps can be used for a total of 97.5.

•In an ISDN phone echo cancellation, channel 1 of the digital interface, the analog

interface with clock tracking and the equalizer shall be enabled at the same time. In

this application the sum of all weights without echo cancellation is 16.0. Therefore 511

taps can be used for a total of 99.8.

Digital Interface 1.7 channel 1 or SSDI X

Digital Interface 1.7 channel 2

Digital Interface 1.7 channel 3

Analog Interface 2.5 X X

Clock Tracking 0.6 X

Miscellaneous 8.4 always active X X

Alert Tone Detector 2.8 off hook

Universal Tone Detector 3.5 on hook

DTMF Detector 5.2

Caller ID Sender 4.3

Speech Coder 62.5

+ AGC 2.6

+ VOX detection 0.8

+ GAP coding 2.6

Speech Decoder 31.8

Table 85 Module Weights

Module Weight Comment Example 1 Example 2

PSB 4860

Data Sheet 109 2000-01-14

2.3.12 Emergency Mode

This mode is intended for a fast backup of controller data into non-volatile memory (flash

memory) connected to the PSB 4860. In short, with this mode a maximum of 2048 bytes

can be transferred with less than 20 ms overhead additional to the time needed by the

flash itself for writing data.

This mode can be entered from normal mode only and returns to power-down mode

when finished. When this mode is entered the PSB 4860 disables all modules

immediately. Only ARAM/DRAM refresh, the auxiliary parallel port and the SCI interface

remain active. If a file was recorded at the time the emergency mode has been entered,

the file may get truncated or deleted completely depending on the memory configuration:

•ATMEL

Entering emergency mode immediately will loose the currently recorded file. The

associated memory will be recovered upon the next Activate Command.

•Samsung

The file can be closed immediately and emergency mode can be entered immediately.

The currently recorded file will be saved.

•Toshiba

The file can be closed immediately and emergency mode can be entered immediately.

The currently recorded file will be saved. However, the maximum block erase time of

the flash device must be taken into account (worst case).

However, all other files will remain intact. In addition, no memory space will get lost due

to the file truncation. Once the emergency mode has been entered, the PSB 4860

expects up to 2048 bytes of data. The data is transferred as a contiguous block from the

controller to the PSB 4860. With each access (48 SCLK cycles) three bytes can be

transferred. The controller does not have to wait for a confirmation from the PSB 4860

for this block transfer. Therefore, at an SCLK frequency of 2 MHz the maximal block size

of 2048 byte can be transferred in approximately 18 ms. Once the data has been

transferred to the PSB 4860 the data is written to a prepared page in the flash device.

The PSB 4860 goes into powerdown mode as soon as possible (after the last necessary

write access to the flash device).

The emergency mode can also be used for fast file close. Then the command that

indicates the end of the transmission has to be issued instead of writing the first byte. In

this case no emergency block of the memory needs to be reserved with the command

Initialize.

The PSB 4860 must be activated again before it can resume normal operation.

In order to use this mode the PSB 4860 must be told to set aside some memory during

initialization as described in section 2.2.3.1. This reserved memory is then excluded from

the normal access (messages and voice prompts) and thus provides an already erased

(ready to write) location for the backup of the block data.

PSB 4860

Data Sheet 110 2000-01-14

Procedure:

1. Preparation

If a file command is currently running (except record, playback or phrase playback)

then the file command must be aborted by setting the ICA bit of register FCMD.

The file command will be aborted within 15 ms (all memories except Toshiba) or

110 ms (worst case Toshiba).

This step is completed when the BSY bit of the STATUS register is reset.

2. Entering Emergency Mode

Emergency mode is entered by setting bit EM of the CCTL register.

This step is completed when the RDY bit of the STATUS register is set again.

3. Data transmission from controller to

The controller can transfer any amount of data in steps of three bytes each from three

bytes to 2046 bytes. This data transfer does not use any handshake mechanism. At

a SCLK frequency of 2 MHz, the controller can issue data transfer commands at full

speed.

There are two commands available (Table 86):

The Transfer Emergency Data command is a special type of a Write Register

Command (Table 95 and Figure 61). Each Transfer Emergency Data command

transfers three bytes of data to the . The first byte is already encoded in the command

word itself while the next two bytes are transmitted in the data word.

Once all data bytes have been transferred, a Write to Memory Command with a

dummy data word must be given. This has to be done even if no byte was and neither

needs to be transferred.

4. Data transmission from to memory

After receiving the Write to Memory command the automatically starts to transfer all

received data to the reserved block in external memory.

This step is completed when the PD bit of register HWCONFIG0 is set (i.e. the is in

power down mode).

5. Recovery

Data recovery from the reserved block can be done after the next activation by the

Low Level Memory Management Commands.

Table 86 Command Words for Emergency Mode Data Transfer

1514131211109876543210

Transfer Emergency Data 0 1 0 0 0 1 0 1 Byte 1

Write to Memory 0100111100000000

PSB 4860

Data Sheet 111 2000-01-14

2.4 Interfaces

Interfaces

This section describes the interfaces of the . The supports both an IOM®-2 interface with

single and double clock mode and a strobed serial data interface (SSDI). However, these

two interfaces cannot be used simultaneously as they share some pins. Both interfaces

are for data transfer only and cannot be used for programming the . The is slave and the

frame synchronization as well as the data clock are inputs. Table 87 lists the features of

the two alternative interfaces.

2.4.1 IOM®-2 Interface

The data stream is partitioned into packets called frames. Each frame is divided into a

programmable number of timeslots. Each timeslot is used to transfer 8 bits. Figure 49

shows a commonly used terminal mode (three channels ch0, ch1 and ch2 with four

timeslots each). The first timeslot (in figure 49: B1) is denoted by number 0, the second

one (B2) by 1 and so on.

Figure 49 IOM®-2 Interface - Frame Structure

The signal FSC is used to indicate the start of a frame. Figure 50 shows as an example

two valid FSC-signals (FSC, FSC*) which both indicate the same clock cycle as the first

clock cycle of a new frame (T1).

Table 87 SSDI vs. IOM®-2 Interface

IOM®-2 SSDI

Signals 4 6

Channels (bidirectional) 3 1

Code linear PCM (16 bit),

A-law, µ-law (8 bit)

linear PCM (16 bit)

Synchronization within frame by timeslot

(programmable)

by signal

(DXST, DRST)

B1 M0B2

FSC

DD/DU

ch0ch1ch2

125 µs

CI0 IC1 M1IC2 CI1

PSB 4860

Data Sheet 112 2000-01-14

Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However,

programming is not supported via the monitor channels.

Figure 50 IOM®-2 Interface - Frame Start

The supports both single clock mode and double clock mode. In single clock mode, the

bit rate is equal to the clock rate. Bits are shifted out with the rising edge of DCL and

sampled at the falling edge. In double clock mode, the clock runs at twice the bit rate.

Therefore for each bit there are two clock cycles. Bits are shifted out with the rising edge

of the first clock cycle and sampled with the falling edge of the second clock cycle. Figure

51 shows the timing for single clock mode and figure 52 shows the timing for double

clock mode.

Figure 51 IOM®-2 Interface - Single Clock Mode

DCL

FSC

FSC*

T1T2

DCL

T1T2

DD/DR

DU/DX bit 0bit 1bit 2

bit 0bit 1bit 2

PSB 4860

Data Sheet 113 2000-01-14

Figure 52 IOM®-2 Interface - Double Clock Mode

The supports up to three channels simultaneously for data transfer. If only two channels

are used, then both the coding (PCM A-law, PCM µ-law or linear) and the data direction

(DD/DU assignment for transmit/receive) can be programmed individually. The PSB

4860 supports a third channel by simply splitting the second 16 bit channel into two 8 bit

channels. Therefore the following restrictions occur for channel 2 and 3 in this case:

1. Channel two as well as three must use PCM coding (both either A-law or µ-law)

2. Channel three is on an even timeslot

3. Channel two is on the following odd timeslot

To enabled the channel splitting, bit SDCHN2:CS must be set and bit SDCHN2:PCM

cleared. The selection of bit SDCHN2:PCD holds then for both channels.

Table 88 shows the registers used for configuration of the IOM®-2 interface.

Table 88 IOM®-2 Interface Registers

SDCONF 1 EN Interface enable

SDCONF 1 DCL Selection of clock mode

SDCONF 6 NTS Number of timeslots within frame

SDCHN1 1 EN Channel 1 enable

SDCHN1 6 TS First timeslot (channel 1)

SDCHN1 1 DD Data Direction (channel 1)

SDCHN1 1 PCM 8 bit code or 16 bit linear PCM (channel 1)

SDCHN1 1 PCD 8 bit code (A-law or µ-law, channel 1)

SDCHN2 1 EN Channel 2 enable

SDCHN2 1 CS Channel 2 split (into two contiguous 8 bit channels)

SDCHN2 6 TS First timeslot (channel 2)

DCL

DD/DR

DU/DX bit 0bit 1bit 2

bit 0 bit 1

T2T3T4T5

PSB 4860

Data Sheet 114 2000-01-14

In A-law or µ-law mode, only 8 bits are transferred and therefore only one timeslot is

needed for a channel. In linear mode, 16 bits are needed for a single channel. In this

mode, two consecutive timeslots are used for data transfer. Bits 8 to 15 are transferred

within the first timeslot and bits 0 to 7 are transferred within the next timeslot. The first

timeslot must have an even number. Figure 53 shows as an example a single channel

in linear mode occupying timeslots 2 and 3. Each frame consists of six timeslots and

single clock mode is used.

Figure 53 IOM®-2 Interface - Channel Structure

At this rate the data is shifted out with the rising edge of the clock and sampled at the

falling edge. The data clock runs at 384 kHz (six timeslots with 8 bit each within 125 µs).

SDCHN2 1 DD Data Direction (channel 2)

SDCHN2 1 PCM 8 bit code or 16 bit linear PCM (channel 2)

SDCHN2 1 PCD 8 bit code (A-law or µ-law, channel 2)

Table 88 IOM®-2 Interface Registers

FSC

DD/DU

D15 D10

D11

D12

D13

D14 D9D8D7D6D5D4D2D1D0

PSB 4860

Data Sheet 115 2000-01-14

2.4.2 SSDI Interface

The SSDI interface is intended for seamless connection to low-cost burst mode

controllers (e.g. PMB 4725) and supports a single channel in each direction. The data

stream is partitioned into frames. Within each frame, one 16 bit value can be sent and

received by the . The start of a frame is indicated by the rising edge of FSC. Data is

always sampled at the falling edge of DCL and shifted out with the rising edge of DCL.

The SSDI transmitter and receiver are operating independently of each other except that

both use the same FSC and DCL signal.

2.4.2.1 SSDI Interface - Transmitter

The indicates outgoing data (on signal DX) by activating DXST for 16 clocks. The signal

DXST is activated with the same rising edge of DCL that is used to send the first bit (Bit

15) of the data. DXST is deactivated with the first rising edge of DCL after the last bit has

been transferred. The drives the signal DX only when DXST is activated. Figure 54

shows the timing for the transmitter.

Figure 54 SSDI Interface - Transmitter Timing

2.4.2.2 SSDI Interface - Receiver

Valid data is indicated by an active DRST pulse. Each DRST pulse must last for exactly

16 DCL clocks. As there may be more than one DRST pulses within a single frame the

can be programmed to listen to the n-th pulse with n ranging from 1 to 16. In order to

detect the first pulse properly, DRST must not be active at the rising edge of FSC. In

figure 55 the is listening to the third DRST pulse (n=3).

FSC

125 µs

DXST

DCL

DU/DX bit 15 bit 14 bit 1 bit 0

PSB 4860

Data Sheet 116 2000-01-14

Figure 55 SSDI Interface - Active Pulse Selection

Figure 56 shows the timing for the SSDI receiver.

Figure 56 SSDI Interface - Receiver Timing

Table 89 shows the registers used for configuration of the SSDI interface.

Table 89 SSDI Interface Register

SDCHN1 4 NAS Number of the active DRST strobe

FSC

DRST

active pulse (n=3)

FSC

125 µs

DRST

DCL

DD/DR bit 15 bit 14 bit 1 bit 0

PSB 4860

Data Sheet 117 2000-01-14

2.4.3 Analog Front End Interface

The uses a four wire interface similar to the IOM®-2 interface to exchange information

with the analog front end (PSB 4851). The main difference is that all timeslots and the

channel assignments are fixed as shown in figure 57. The is master of this interface and

provides AFEFS as well as AFECLK.

Figure 57 Analog Front End Interface - Frame Structure

Voice data is transferred in 16 bit linear coding in two bidirectional channels C1 and C2.

An auxiliary channel C3 is used to transfer the current setting of the loudspeaker

amplifier ALS to the . The remaining bits are fixed to zero. In the other direction C3

transfers an override value for ALS from the to the PSB 4851. An additional override bit

OV determines if the currently transmitted value should override the AOAR:LSC1)

setting. The AOAR:LSC setting is not affected by C3:ALS override. Table 90 shows the

source control of the gain for the ALS amplifier.

Furthermore the AFE interface can be enabled or disabled according to table 91.

1) See specification of PSB 4851, automatically set by the in loudhearing mode.

Table 90 Control of ALS Amplifier

AOPR:OVRE C3:OV Gain of ALS amplifier

0 - AOAR:LSC

1 0 AOAR:LSC

11C

3:ALS

Table 91 Analog Front End Interface Register

AFECTL 1 EN Interface enable

Channel C1Channel C3

Channel C2

AFEFS

AFEDD

125 µs

ALS

AFEDU unused

000OV

16 bit 16 bit 8 bit

PSB 4860

Data Sheet 118 2000-01-14

Figure 58 Analog Front End Interface - Frame Start

Figure 58 shows the synchronization of a frame by AFEFS. The first clock of a new frame

(T1) is indicated by AFEFS switching from low to high before the falling edge of T1.

AFEFS may remain high during subsequent cycles up to T32.

Figure 59 Analog Front End Interface - Data Transfer

The data is shifted out with the rising edge of AFECLK and sampled at the falling edge

of AFECLK (figure 59). If AOPR:OVRE is not set, the channel C3 is not used by the PSB

4851. All values (C1, C2, C3:ALS) are transferred MSB first. The data clock (AFECLK)

rate is fixed at 6.912 MHz. Table 92 shows the clock cycles used for the three channels.

Table 92 Analog Front End Interface Clock Cycles

Clock Cycles AFEDD (driven by ) AFEDU (driven by PSB 4851)

T1-T16 C1 data C1 data

T17-T32 C2 data C2 data

T33-T40 C3 data C3 data

T41-T864 0tristate

AFECLK

AFEFS

T1T2

AFECLK

T1T2

AFEDD

AFEDU bit 0bit 1bit 2

bit 0bit 1bit 2

PSB 4860

Data Sheet 119 2000-01-14

2.4.4 Serial Control Interface

The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is

transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS

indicates the beginning of an access. Data is sampled by the at the rising edge of SCLK

and shifted out at the falling edge of SCLK. Each access must be terminated by a rising

edge of CS. The accesses to the can be divided into four classes:

1. Configuration Read/Write

2. Register Read/Write

3. Status/Data Read

4. Status/Data Read with Interrupt Acknowledge

If the is in power down mode, a read access to the status register does not deliver valid

data with the exception of the RDY bit (RDY=0). After the status has been read the

access can be either terminated or extended to read data from the . A register read/write

access can only be performed when the is ready. The RDY bit in the status register

provides this information.

Any access to the starts with the transfer of 16 bits to the over line SDR. This first word

specifies the access class, access type (read or write) and, if necessary, the register

accessed. Two access types terminate after the first word: configuration register write

and register read. If the configuration register is written, the first word also includes the

data and the access is terminated. After an access register read, an access of type data

read is necessary to obtain the register data. However, the data is valid only when

STATUS:RDY=1.

With a second word, all accesses beside configuration register write and register read

deliver the status register from the via line SDX. After the second word, the access

status register read terminates while all other accesses transfer data with a third word

and terminate then.

Figures 60 to 63 show the timing diagrams for the different access classes and types to

the .

PSB 4860

Data Sheet 120 2000-01-14

Figure 60 Status Register Read Access

Figure 61 Data Read Access

SCLK

SDR c15 c14 c1c0

s15 s14 s1s0

SDX

c15,..,c0:

s15,..,s0:

command word for status register read :

status register:

INT

SCLK

SDR c15 c14 c1c0

s15 s14 s1s0

SDX

c15,..,c0:

s15,..,s0:

command word for data read:

status register:

d15 d14 d1d0

d15,..,d0: data to be read:

PSB 4860

Data Sheet 121 2000-01-14

Figure 62 Register Write Access

Figure 63 Configuration Register Read Access

Configuration registers at even adresses use bit positions d7-d0 while configuration

registers at odd adresses use bit positions d15-d8.

SCLK

SDR c15 c14 c1c0

s15 s14 s1s0

SDX

c15,..,c0:

s15,..,s0:

command word for register write:

status register:

d15 d14 d1d0

d15,..,d0: data to be written :

SCLK

SDR c15 c14 c1c0

SDX

c15,..,c0:

s15,..,s0:

command word for configuration register read:

status register :

d15,..,d0: data to be read:

s15 s14 s1s0d15 d14 d1d0

PSB 4860

Data Sheet 122 2000-01-14

Figure 64 Configuration Register Write Access or Register Read Command

For all commands the external signal INT is deactivated as long as the chip is selected

(CS is low). For a detailed discussion about the behavior of the interrupt signal please

see section 2.3.4. Table 93 shows the formats of the different command words. All other

command words are reserved. Note that interrupts are only acknowledged (cleared) if

the command read status/data with interrupt acknowledge is issued.

In case of a configuration register write, W determines what configuration register is to

be written (table 94):

Table 93 Command Words for Register Access

1514131211109876543210

Read Status Register or

Data Read Access

(interrupt acknowledge)

0011000000000000

Read Status Register or

Data Read Access1)

1) Does not acknowledge interrupt.

1001000000000000

Read Register1) 0101 REG

Write Register1) 0100 REG

Read Configuration Reg.011100R000000000

Write Configuration Reg. 0 1 1 0 0 0 W DATA

Table 94 Address Field W for Configuration Register Write

9 8 Register

0 0 HWCONFIG 0

0 1 HWCONFIG 1

1 0 HWCONFIG 2

1 1 HWCONFIG 3

SCLK

SDR c15 c14 c1c0

c15,..,c0: command word for configuration register write:

or register read:

PSB 4860

Data Sheet 123 2000-01-14

In case of a configuration register read, R determines what pair of configuration registers

is to be read (table 95):

Note: Reading any register except the status register or a hardware configuration

command (figure 64). With this access the register address is transferred to the .

After that access data read accesses (figure 61) must be executed. The first data

read access with STATUS:RDY=1 delivers the value of the register.

Table 95 Address Field R for Configuration Register Read

9 Register pair

0 HWCONFIG 0 / HWCONFIG 1

1 HWCONFIG 2 / HWCONFIG 3

PSB 4860

Data Sheet 124 2000-01-14

PSB 4860

Data Sheet 125 2000-01-14

2.4.5 Memory Interface

The supports either Flash Memory or ARAM/DRAM as external memory for storing

messages. If ARAM/DRAM is used, an EPROM can be added optionally to support read-

only messages (e.g. voice prompts).

Note: Although the memory accesses are performed by the , the specification of the

used memory (e.g. number of re-write cycles in case of Flash) has to be regarded

by the controller.

Table 96 summarizes the different configurations supported.

If ARAM/DRAM is used, the total amount of memory must be a power of two. If more

than one memory device is used, the memory devices must be of the same type.

For flash devices, voice prompts do not need to be programmed via the PSB 4860. They

can also directly be programmed by any other circuitry into the Flash. This is supported

Table 96 Supported Memory Configurations

Mbit Type Bank 0 (D0-D3) Bank 1 (D4-D7)Comment

4 ARAM/DRAM 1Mx4 -

4 ARAM/DRAM 4Mx1 - D0 only

4 ARAM/DRAM 512kx8

8 ARAM/DRAM 1Mx4 1Mx4

16 ARAM/DRAM 4Mx4 - 2k or 4k refresh

16 ARAM/DRAM 16Mx1 - D0 only

16 ARAM/DRAM 2Mx8 2k refresh

32 ARAM/DRAM 4Mx4 4Mx4 2k or 4k refresh

32 ARAM/DRAM 2x2Mx8 2k refresh

64 ARAM/DRAM 16Mx4 - 4k or 8k refresh

64 ARAM/DRAM 8Mx8 4k or 8k refresh

128 ARAM/DRAM 16Mx4 16Mx4 4k or 8k refresh

4-128 FLASH 512kx8 KM29N040

8-128 FLASH 1Mx8 KM29W8000

16-128 FLASH 2Mx8 KM29N16000

4-16 FLASH 4Mx1 TC58A040

4-16 FLASH 4Mx1 AT45DB041

8-32 FLASH 8Mx1 AT45DB081

16-64 FLASH 16Mx1 AT45DB161

PSB 4860

Data Sheet 126 2000-01-14

by the PSB 4860 insofar as the control lines are released during reset and (optionally)

power down. Instead of actively driving the lines FCS, FOE, FWE, FCLE and ALE these

lines are pulled high by a weak pullup during reset and (optionally) power down.

PSB 4860

Data Sheet 127 2000-01-14

2.4.5.1 ARAM/DRAM Interface

The supports up to two banks of memory which may be 4 bit or 8 bit wide (Figure 65).

If both banks are used, each one is connected identically with exception of the data lines

D0 - D7. These must be connected as described by table 96. The pin FRDY must be tied

high.

Figure 65 ARAM/DRAM Interface - Connection Diagram

The also supports different internal organizations of ARAM/DRAM chips. Table 97

shows the necessary connections on the address bus.

Table 97 Address Line Usage (ARAM/DRAM Mode)

ARAM/DRAM CS91) MA0-MA8MA9MA10 MA11 MA12 MA13

256k x4 1 A0-A8

512k x8 1 A0-A8A9

MA0-MA15

MD0-MD3

RAS

CAS0

A0-A12

D0-D3

RAS

CAS

A0-A12

D0-D7

RAS

CAS

single 4 bit bank single 8 bit bank

MA0-MA15

MD0-MD7

RAS

CAS0

MA0-MA15

MD0

RAS

CAS0

A0-A12

RAS

CAS

single 1 bit bank

PSB 4860 PSB 4860

PSB 4860

Data Sheet 128 2000-01-14

The timing of the ARAM/DRAM interface is shown in figures 66 to 68. The timing is

derived from the internal memory clock MCLK which runs at a quarter of the system

clock.

Figure 66 ARAM/DRAM Interface - Read Cycle Timing

1M x4 0 A0-A8A9

4M x4 (2k refresh) 0 A0-A8A9A10

4M x4 (4k refresh) 0 A0-A8A9A10 A11

2M x8 0 A0-A8A9A10

16M x4 (4k refresh) 0 A0-A8A9A10 A11

16M x4 (8k refresh) 0 A0-A8A9A10 A11 A12

8M x8 (4k refresh) 0 A0-A8A9A10 A11

8M x8 (8k refresh) 0 A0-A8A9A10 A11 A12

1) see chip control register CCTL

Table 97 Address Line Usage (ARAM/DRAM Mode)

MCLK

MA0-MA13

MD0-MD7

CAS0,CAS1

RAS

row addr. col. addr.

PSB 4860

Data Sheet 129 2000-01-14

Figure 67 ARAM/DRAM Interface - Write Cycle Timing

Figure 68 ARAM/DRAM Interface - Refresh Cycle Timing

The ensures that RAS remains inactive for at least one MCLK-cycle between

successive accesses.

The frequency at which refresh cycles are performed is shown in table 98.

Table 98 Refresh Frequency Selection

Refresh frequency Comment

64 kHz Memory access (e.g. recording) in progress

8, 16, 32 or 64 kHz1)

1) as programmed by HWCONFIG2:RSEL

No memory access in progress or power-down

MCLK

MA0-MA13

MD0-MD7

CAS0,CAS1

RAS

row addr. col. addr.

data out

MCLK

CAS0,CAS1

RAS

PSB 4860

Data Sheet 130 2000-01-14

2.4.5.2 EPROM Interface

The supports an EPROM in parallel with ARAM/DRAM. This interface is always 8 Bits

wide and supports a maximum of 256 kBytes. Figure 69 shows a connection diagram

and figure 70 shows the timing. This interface supports read cycles only.

Figure 69 EPROM Interface - Connection Diagram

Figure 70 EPROM Interface - Read Cycle Timing

Note: In order to access more than 64 kBytes the pins SPS0 and SPS1 can be

programmed to provide the address lines A16 and A17. In this mode A16 and A17

remain stable during the whole read cycle. See the register SPSCTL for

programming information.

MA0-MA15

MD0-MD7

VPRD

A0-A15

D0-D7

A16

A17

SPS1

SPS0

VPRD

MD0-MD7

MCLK*

MA0-MA15

PSB 4860

Data Sheet 131 2000-01-14

2.4.5.3 Parallel Flash Memory Interface

The has special support for KM29N040, KM29W8000 and KM29N16000 or equivalent

devices. Figure 71 shows the connection diagram for a single device.

Figure 71 Parallel Flash Memory Interface - Connection Diagram

No external components are required if up to four devices KM29N040 are used. The

select signals FCS0-FCS3 can directly be used to access up to four devices. The

determines the number of connected devices automatically. Table 99 shows the signals

on the MA-lines during a device access.

Furthermore, none of the parallel flashs needs all address liness. Therefore, the upper

address lines can additionally be used to access multiple devices. Then, they have to be

decoded by an external decoder.

Table 99 Address Line Usage (Samsung Mode)

MA11 MA10 MA9MA8MA7MA6MA5MA4MA3MA2MA1MA0

FCS3FCS2FCS1FCS0A23 A22 A21 A20 A19 A18 A17 A16

D0-D7

CLE

MD0-MD7

FCS

FOE

FWR

FCLE

ALE ALE

+5V

R/B

FRDY

PSB 4860

Data Sheet 132 2000-01-14

Figure 72 shows an application with three KM29N040 devices.

Figure 72 Parallel Flash Memory Interface - Multiple Devices

An access to the Flash Memory can consist of several partial access cycles where only

the timing of the partial access cycles is defined but not the time between two

consecutive partial access cycles. The performs three types of partial access cycles:

1. Command write

2. Address write

3. Data read/write

Table 100 shows the supported accesses and the corresponding partial access cycles.

Table 100 Flash Memory Command Summary

Access Command

write

Address

write 1

Address

write 2

Address

write 3

# of Data

read/write

Command

write

RESET FF - - - - -

STATUS READ 70 - - - 1 -

BLOCK ERASE 60 A8-A15 A16-A23 --D0

READ 00 A0-A7A8-A15 A16-A23 1-32 -

WRITE 80 A0-A7 A8-A15 A16-A23 1-32 10

D0-D7CE RE WE CLE

MD0-MD7

FOE

FWR

FRDY

ALE

+5V

R/B

FCLE

D0-D7CE RE WE CLE ALER/B

MA8

MA9

MA10

D0-D7CE RE WE CLE ALER/B

PSB 4860

Data Sheet 133 2000-01-14

The timing for the partial access cycles is shown in figures 73 to 74. Note that both FCS

and MA0-MA15 remain stable between the first and the last partial access of a device

access.

Figure 73 Parallel Flash Memory Interface - Command Write

Figure 74 Parallel Flash Memory Interface - Address Write

As there is no access that starts or stops with an address write cycle (figure 74) FCS is

already low at the start of this cycle and also remains low.

MCLK*

MA0-MA11

MD0-MD7

FWR

FCS

FCLE

data out

MCLK*

MD0-MD7

FWR

ALE

data out

address latch cycle

t0t1t2t3

PSB 4860

Data Sheet 134 2000-01-14

Figure 75 Parallel Flash Memory Interface - Data Write

As there is no access that starts or stops with a data write cycle (figure 75) FCS is

already low at the start of this cycle and also remains low.

Figure 76 Parallel Flash Memory Interface - Data Read

If the device access ends with a read cycle, the FCS-signals go inactive after t3 of the

last read cycle. The data is latched at the rising edge of FOE.

MCLK*

MD0-MD7

FWR

data out

write cycle

t0t1t2t3

MCLK*

MD0-MD7

FOE

data in

read cycle

t0t1t2t3

PSB 4860

Data Sheet 135 2000-01-14

2.4.5.4 Serial Flash Memory Interface

The PSB 4860 can be connected to up to four identical devices. It determines the

number of connected devices automatically. The controller must provide the information

on the type of the devices (Toshiba or Atmel). Table 101 lists the used pins.

The following figures show the connection diagrams for various configurations.

Figure 77 Serial Flash - Connection to Single TC 58 A 040 F

Figure 78 Serial Flash - Connection to Single AT 45 DB 041

Table 101 Pin Functions for Serial Flash Interface

Pin Nr. Name Comment

42 MD0/SCLK Clock output for serial interface

43 MD1/SDI Data in from flash device

44 MD2/SDO Data out from PSB 4860

46 MD4/CS0Chip select for first device

47 MD5/CS1Chip select for second device

50 MD6/CS2Chip select for third device

51 MD7/CS3Chip select for fourth device

MD0/SCLK

MD2/SDO

MD1/SDI

MD4/CS0

TC 58 A 040 F

PSB 4860

MD0/SCLK

MD2/SDO

MD1/SDI

MD4/CS0

SCK

AT 45 DB 041

PSB 4860

FRDY RDY/BUSY

PSB 4860

Data Sheet 136 2000-01-14

In each case multiple devices can be connected by sharing the lines MD0/SCLK, MD1/

SDI and MD2/SDO as shown in figure 79.

Figure 79 Serial Flash - Connection to Multiple TC 58 A 040 F

Table 102 shows the registers associated with the memory interface.

Table 102 Memory Interface Registers

HWCONFIG0 1 PFRDY Enable internal pull-up resistance at FRDY input

HWCONFIG2 2 RSEL Refresh cycle selection

HWCONFIG3 1 SFI Serial flash selection

CCTL 2 CDIV Serial flash clock speed selection

CCTL 2 SFT Serial flash type

CCTL 2 MT Memory type (DRAM, flash)

CCTL 1 CS9 Small DRAM (<2M)

CCTL 1 SAS 2Mx8 (or 1Mx16) ARAM/DRAM

MD0/SCLK

MD2/SDO

MD1/SDI

MD4/CS0

TC 58 A 040 F

MD5/CS1

MD6/CS2

PSB 4860

Data Sheet 137 2000-01-14

2.4.6 Auxiliary Parallel Port

The provides an auxiliary parallel port if the memory interface is in serial Flash or

Samsung Flash mode. In this case the lines MA0 to MA15 (one Flash device) or MA0 to

MA7 and MA12 to MA15 are not needed for the memory interface and can therefore be

used for an auxiliary parallel port.

The auxiliary parallel port has two modes: static mode and multiplex mode. In both

modes, the can generate an interrupt on specific input pins and specific signal edges.

Each input pin can be masked individually. The events that generated an interrupt are

collected in a hold register.

Table 103 shows the registers for mode selection.

2.4.6.1 Static Mode

In static mode all pins of the auxiliary parallel port interface have identical functionality.

Any pin can be configured as an output or an input. Pins configured as outputs provide

a static signal as programmed by the controller. Pins configured as inputs are monitoring

the signal continuously without latching. The controller always reads the current value.

Table 104 shows the registers used for static mode.

2.4.6.2 Multiplex Mode

In multiplex mode, the multiplexes either four output registers or three output register

and one input to MA0-MA11. For this, MA12-MA15 are used to distinguish four timeslots.

Each timeslot has a duration of approximately 2 ms. The timeslots are separated by a

gap of approximately 125 µs, in which none of the signals MA12-MA15 are active. The

multiplexes three output registers to MA0-MA11 in timeslots 0, 1 and 2. In timeslot 3, the

direction of the pins can be programmed. For input pins, the signal is latched with the

falling edge of MA12. Table 105 shows the registers used for multiplex mode.

This mode is useful for scanning keys or controlling seven segment LED displays.

Table 103 Auxiliary Parallel Port Mode Registers

HWCONFIG1 APP Mode selection (static/multiplex)

HWCONFIG3 MPM Enable four flash select lines instead of MA8-MA11

Table 104 Static Mode Registers

DOUT3 16 Output signals (for pins configured as outputs)

DIN 16 Input signals (for pins configured as inputs)

DDIR 16 Pin direction

PSB 4860

Data Sheet 138 2000-01-14

Figure 80 shows the timing diagram for multiplex mode.

Figure 80 Auxiliary Parallel Port - Multiplex Mode

Note: In either mode the voltage at any pin (MA0 to MA15) must not exceed VDD.

2.4.6.3 Interrupt Generation

For each pin configured as an input, the compares the current value to the previous

value. In static mode, the previous value is the value 1 ms ago (static mode). In multiplex

mode, the previous value is the value sampled during the previous input timeslot. In both

modes, the exact sampling point cannot be defined. For a reliable detection of a specific

value, it is therefore necessary that a value must be stable at least 1.5 ms (static mode)

or 8 ms (multiplex mode).

Table 105 Multiplex Mode Registers

DOUT0 12 Output signals on MA0-MA11 while MA15=1

DOUT1 12 Output signals on MA0-MA11 while MA14=1

DOUT2 12 Output signals on MA0-MA11 while MA13=1

DOUT3 12 Output signals (for pins configured as outputs) while MA12=1

DIN 12 Input signals (for pins configured as inputs) at falling edge of MA12

DDIR 12 Pin direction during MA12=1

2 ms

MA15

MA14

MA13

MA12

MA0-MA11 DOUT0 DOUT2DOUT1 DOUT0DIN/DOUT3

PSB 4860

Data Sheet 139 2000-01-14

For each input pin the can be programmed to detect the following changes individually

(table 106).

Whenever an input pin meets the specified condition then the sets the corresponding bit

within the register DHOLD and also the IPP bit of the STATUS register. Therefore the

STATUS register collects all events at any pin. The change of bit STATUS:PPI can also

trigger an external interrupt depending on the mask register INTM. The bit STATUS:IPP

is reset when the register DHOLD is read by the controller. The register DHOLD is also

cleared at this time (i.e. when it is read).

Note: The edge detection can be stopped by writing 0 to the register DHOLD. Writing

any other value to DHOLD starts the edge detection according to the programmed

masks. Edge detection must be started after a wake-up as it is disabled by default.

Table 106 Interrupt Mask Definition for Parallel Port

DMASK1 DMASK2 Prev. Value Cur. Value Remark

0 0 - - disabled

0 1 0 1 rising edge

1 0 1 0 falling edge

1 1 0 (1) 1 (0) both edges

PSB 4860

Data Sheet 140 2000-01-14

PSB 4860

Data Sheet 141 2000-01-14

3 Detailed Register Description

The has a single status register (read only) and an array of data registers (read/write).

The purpose of the status register is to inform the external microcontroller of important

status changes of the and to provide a handshake mechanism for data register reading

or writing. If the generates an interrupt, the status register contains the reason of the

interrupt.

3.1 Status Register

RDY Ready

0: The last command (if any) is still in progress.

1: The last command has been executed.

ABT Abort

0: No exception during operation

1: An exception caused the to abort any operation currently in

progress. The ABT bit is cleared by writing the revision register. No

other command is accepted by the while ABT is set.

GAP Gap Being Detected

0: Currently no gap is being detected during recording

1: Currently a gap is being detected during recording

VOX VOX detection

0: The input signal of the speech coder contains voice

1: The input signal represents silence, noise, constant or periodic signals

CIA Caller ID Available

0: No new data for caller ID

1: New caller ID byte available

CIR Caller ID Request

0: No new data for caller ID sender requested

1: New caller ID byte requested

15 0

RDY ABT GAP VOX CIA

CIR

CIS

CPT

UTD CNG SD ERR BSY DTV ATV DA

DRQ PQE PPI

PSB 4860

Data Sheet 142 2000-01-14

CD Carrier Detect

0: No carrier detected

1: Carrier detected

CIS Caller ID Stop Bits

0: The caller ID sender still sends data

1: The caller ID sender sends stop bits

CPT Call Progress Tone

0: Currently no call progress tone detected or pause detected (raw mode)

1: Currently a call progress is detected

UTD Universal Tone Detected

0: Currently no tone is being detetced

1: Currently a tone is being detected

CNG Fax Calling Tone

0: Currently no fax calling tone is being detected

1: Currently a fax calling tone is being detected

SD Speech Detected

0: No speech detected

1: Speech signal at input of coder

ERR Error (File Command)

0: No error

1: Last file command has resulted in an error

BSY Busy (File Command)

0: File system idle

1: File system still busy (also set during encoding/decoding)

DTV DTMF Tone Valid

0: No new DTMF code available

1: New DTMF code available in DDCTL

ATV Alert Tone Valid

0: No new alert tone code available

PSB 4860

Data Sheet 143 2000-01-14

1: New alert tone code available in ADCTL0

DA Data Available

0: No data available

1: Data of speech encoder to be fetched by microcontroller

DRQ Data Request

0: No data requested

1: New data for speech decoder requested from the microcontroller

PQE Phrase Queue Empty

0: No new phrase requested

1: New phrase number requested for continuous phrase playing

PPI Parallel Port Interrupt

0: No unmasked change at input ports of parallel port

1: At least one unmasked input has changed at the parallel port

PSB 4860

Data Sheet 144 2000-01-14

3.2 Hardware Configuration Registers

HWCONFIG 0 - Hardware Configuration Register 0

PPSDX Push/Pull for SDX

0: The SDX pin has open-drain characteristic

1: The SDX pin has push/pull characteristic

PPINT Push/Pull for INT

0: The INT pin has open-drain characteristic

1: The INT pin has push/pull characteristic

PFRDY Pullup for FRDY

0: The internal pullup resistor of pin FRDY is enabled

1: The internal pullup resistor of FRDY is disabled

PPSDI Push/Pull for SDI interface

0: The DU and DD pins have open-drain characteristic

1: The DU and DD pins have push/pull characteristic

OSC Enable Auxiliary Oscillator

0: The auxiliary oscillator (OSC1, OSC2) is disabled

1: The auxiliary oscillator (OSC1, OSC2) is enabled

RTC Enable Real Time Clock

0: The real time clock is disabled

1: The real time clock (RTC) is enabled.

ACS AFE Clock Source

0: AFECLK is derived from the main oscillator

1: AFECLK is derived from the CLK input

PD Power Down (read only)

0: The is in active mode

1: The is in power down mode

7 0

PD ACS RTC OSC PPSDI PFRDY PPINT PPSDX

PSB 4860

Data Sheet 145 2000-01-14

HWCONFIG 1 - Hardware Configuration Register 1

APP Auxiliary Parallel Port

ACT AFE Clock Tracking

0: AFECLK tracking disabled

1: AFECLK tracking enabled

ADS AFE Double Speed

0: 8 kHz AFEFS

1: 16 kHz AFEFS

MFS Master Frame Sync Selection

0: AFEFS

1: FSC

XTAL XTAL Frequency

SSDI SSDI Interface Selection

0: IOM®-2 Interface

1: SSDI Interface

7 0

APP ACT ADS MFS XTAL SSDI

76Description

0 0 normal (ARAM/DRAM, Intel type flash, voice prompt EPROM)

0 1 APP static mode

1 0 APP multiplex mode

1 1 reserved

21Factor p

1) The factor p is needed to calculate the clock frequency at AFECLK.

Description

0 0 5 34.560 MHz

0 1 4.5 31.104 MHz

104 reserved

1 1 reserved reserved

PSB 4860

Data Sheet 146 2000-01-14

HWCONFIG 2 - Hardware Configuration Register 2

PPM Push/Pull for Memory Interface (reset, power down)

0: The signals for the memory interface have push/pull characteristic

1: The signals for the memory interface have pullup/pulldown characteristic

ESDX Edge Select for DX

0: DU/DX is transmitted with the rising edge of DCL

1: DU/DX is transmitted with the falling edge of DCL

ESDR Edge Select for DR

0: DD/DR is latched with the falling edge of DCL

1: DD/DR is latched with the rising edge of DCL

RSEL Refresh Select

7 0

PPM ESDX ESDR 0 0 0 RSEL

10Description

0 0 64 kHz refresh frequency

0 1 32 kHz refresh frequency

1 0 16 kHz refresh frequency

1 1 8 kHz refresh frequency

PSB 4860

Data Sheet 147 2000-01-14

HWCONFIG 3 - Hardware Configuration Register 3

LCM Low Clock Mode

0: normal XTAL frequency range

1: 15.368 MHz XTAL frequency

SFI Serial Flash Interface

0: MD0-MD7 are used for ARAM/DRAM or parallel flash interface

1: MD0-MD7 are used for serial flash interface

MPM Mixed Port Mode

0: APP interface compatible with PSB 4860 V2.1

1: MA0-MA7 and MA12-MA15 are APP, MA8-MA11 select flash devices

7 0

0 0 0 LCM SFI MPM 0 0

PSB 4860
Data Sheet  148 2000-01-14
 
3.3 Read/Write Registers
The following sections contains all read/write registers of the . The register addresses
are given as hexadecimal values. Registers marked with an R are affected by reset or a
wake up after power down. All other registers retain their previous value. No access must
be made to addresses other than those associated with a read/write register.
3.3.1 Register Table
Address. Name Long Name Page
00h REV Revision ............................................................................. 153
01h R CCTL Chip Control  ...................................................................... 154
02h R INTM Interrupt Mask Register ..................................................... 156
03h R AFECTL Analog Front End Interface Control ................................... 157
04h R IFS1 Interface Select 1  .............................................................. 158
05h R IFG1 Interface Gain 1 ................................................................. 159
06h R IFG2 Interface Gain 2 ................................................................. 160
07h R IFS2 Interface Select 2  .............................................................. 161
08h R IFG3 Interface Gain 3 ................................................................. 162
09h R IFG4 Interface Gain 4 ................................................................. 163
0AhR SDCONF Serial Data Interface Configuration  ................................... 164
0BhR SDCHN1 Serial Data Interface Channel 1  ........................................ 165
0ChR IFS3 Interface Select 3  .............................................................. 167
0DhR SDCHN2 Serial Data Interface Channel 2  ........................................ 168
0EhR IFS4 Interface Select 4  .............................................................. 169
0Fh R IFG5 Interface Gain 5 ................................................................. 170
10h R UA Universal Attenuator .......................................................... 171
11h R DGCTL DTMF Generator Control ................................................... 172
12h DGF1 DTMF Generator Frequency 1  .......................................... 173
13h DGF2 DTMF Generator Frequency 2  .......................................... 174
14h DGL DTMF Generator Level ...................................................... 175
15h DGATT DTMF Generator Attenuation ............................................ 176
16h R CNGCTL Calling Tone Control .......................................................... 177
17h CNGBT CNG Burst Time  ................................................................ 178
18h CNGLEV CNG Minimal Signal Level  ................................................ 179
19h CNGRES CNG Signal Resolution  ..................................................... 180
1AhR ATDCTL0 Alert Tone Detection 0 ....................................................... 181
1Bh ATDCTL1 Alert Tone Detection 1 ....................................................... 182
1ChR CIDCTL0 Caller ID Control 0 ............................................................. 183
1Dh CIDCTL1 Caller ID Control 1 ............................................................. 184
1EhR IFS5 Interface Select 5  .............................................................. 185
1Fh R IFG6 Interface Gain 6 ................................................................. 186
20h R CPTCTL Call Progress Tone Control ............................................... 187
21h CPTTR  Call Progress Tone Thresholds ......................................... 188

PSB 4860
Data Sheet  149 2000-01-14
 
22h CPTMN CPT Minimum Times ..........................................................189
23h CPTMX CPT Maximum Times .........................................................190
24h CPTDT CPT Delta Times ................................................................191
25h R LECCTL Line Echo Cancellation Control ..........................................192
26h LECLEV Minimal Signal Level for Line Echo Cancellation  ...............193
27h LECATT Externally Provided Attenuation  .........................................194
28h LECMGN Margin for Double Talk Detection .......................................195
29h R DDCTL DTMF Detector Control ......................................................196
2Ah DDTW  DTMF Detector Signal Twist  ..............................................197
2Bh DDLEV DTMF Detector Minimum Signal Level  ..............................198
2EhR FCFCTL Equalizer Control ................................................................199
2Fh FCFCOF Equalizer Coefficient Data ..................................................201
30h R SCCTL Speech Coder Control ........................................................202
31h SCCT2 Speech Coder Control 2 .....................................................203
32h SCCT3 Speech Coder Control 3 .....................................................204
33h SCDATA Speech Encoder Data  ........................................................205
34h R SDCTL Speech Decoder Control ....................................................206
35h SDCT2 Speech Decoder Control 2 .................................................207
36h SDDATA Speech Decoder Data ........................................................208
38h R AGCCTL AGC Control .......................................................................209
39h AGCATT Automatic Gain Control Attenuation ...................................210
3Ah AGC1 Automatic Gain Control 1 ...................................................211
3Bh AGC2 Automatic Gain Control 2 ...................................................212
3Ch AGC3 Automatic Gain Control 3 ...................................................213
3Dh AGC4 Automatic Gain Control 4 ...................................................214
3Eh AGC5 Automatic Gain Control 5 ...................................................215
40h R FCTL File Control .........................................................................216
41h R FCMD File Command ....................................................................217
42h R FDATA File Data .............................................................................219
43h R FPTR File Pointer  .........................................................................220
45h R PDCTL Peak Detector Control ........................................................221
46h PDDATA Peak Detector Data ............................................................222
47h R SPSCTL SPS Control  .......................................................................223
48h R RTC1 Real Time Clock 1 ..............................................................224
49h R RTC2 Real Time Clock 2 ..............................................................225
4AhR DOUT0 Data Out (Timeslot 0) .........................................................226
4BhR DOUT1 Data Out (Timeslot 1) .........................................................227
4ChR DOUT2 Data Out (Timeslot 2) .........................................................228
4DhR DOUT3 Data Out (Timeslot 3 or Static Mode) .................................229
4Eh DIN Data In (Timeslot 3 or Static Mode)  ...................................230
4Fh R DDIR Data Direction (Timeslot 3 or Static Mode)  ........................231
50h DMASK1 Data In Mask 1 (Timeslot 3 or Static Mode) .......................232
51h DMASK2 Data In Mask 2 (Timeslot 3 or Static Mode) .......................233

PSB 4860
Data Sheet  150 2000-01-14
 
52h R DHOLD Data In Hold (Timeslot 3 or Static Mode)  .......................... 234
53h SCVOX1  Vox Detector 1 ................................................................... 235
54h SCVOX2  Vox Detector 2 ................................................................... 236
55h SCVOX3  Vox Detector 3 ................................................................... 237
56h SCVOX4  Vox Detector 4 ................................................................... 238
57h SCVOX5  Vox Detector 5 ................................................................... 239
58h SCVOX6  Vox Detector 6 ................................................................... 240
5Ah SCGAP1  Speech Coder Gap Control 1 ............................................ 241
5Bh SCGAP2  Speech Coder Gap Control 2 ............................................ 242
5Ch SCGAP3 Speech Coder Gap Control 3 ............................................ 243
5Dh SCGAP4  Speech Coder Gap Control 4 ............................................ 244
60h R SCTL Speakerphone Control  ...................................................... 245
62h R SSRC1  Speakerphone Source 1 .................................................... 246
63h R SSRC2  Speakerphone Source 2 .................................................... 247
64h SSDX1  Speech Detector (Transmit) 1  ........................................... 248
65h SSDX2  Speech Detector (Transmit) 2  ........................................... 249
66h SSDX3 Speech Detector (Transmit) 3  ........................................... 250
67h SSDX4  Speech Detector (Transmit) 4  ........................................... 251
68h SSDR1 Speech Detector (Receive) 1  ............................................ 252
69h SSDR2 Speech Detector (Receive) 2  ............................................ 253
6Ah SSDR3 Speech Detector (Receive) 3  ............................................ 254
6Bh SSDR4 Speech Detector (Receive) 4  ............................................ 255
6Ch SSCAS1 Speech Comparator (Acoustic Side) 1 .............................. 256
6Dh SSCAS2 Speech Comparator (Acoustic Side) 2 .............................. 257
6Eh SSCAS3 Speech Comparator (Acoustic Side) 3 .............................. 258
6Fh SSCLS1 Speech Comparator (Line Side) 1 ..................................... 259
70h SSCLS2 Speech Comparator (Line Side) 2 ..................................... 260
71h SSCLS3 Speech Comparator (Line Side) 3 ..................................... 261
72h SATT1 Attenuation Unit 1 .............................................................. 262
73h SATT2 Attenuation Unit 2 .............................................................. 263
74h SAGX1 Automatic Gain Control (Transmit) 1 ................................. 264
75h SAGX2 Automatic Gain Control (Transmit) 2 ................................. 265
76h SAGX3 Automatic Gain Control (Transmit) 3 ................................. 266
77h SAGX4 Automatic Gain Control (Transmit) 4 ................................. 267
78h SAGX5 Automatic Gain Control (Transmit) 5 ................................. 268
79h SAGR1 Automatic Gain Control (Receive) 1 .................................. 269
7Ah SAGR2 Automatic Gain Control (Receive) 2 .................................. 270
7Bh SAGR3 Automatic Gain Control (Receive) 3 .................................. 271
7Ch SAGR4 Automatic Gain Control (Receive) 4 .................................. 272
7Dh SAGR5 Automatic Gain Control (Receive) 5 .................................. 273
7Eh SLGA Line Gain  ........................................................................... 274
80h SAELEN Acoustic Echo Cancellation Length ................................... 275
81h SAEATT Acoustic Echo Cancellation Double Talk Attenuation  ....... 276

PSB 4860
Data Sheet  151 2000-01-14
 
82h SAEGS Acoustic Echo Cancellation Global Scale  ..........................277
83h SAEPS1 Acoustic Echo Cancellation Partial Scale  ..........................278
84h SAEPS2 Acoustic Echo Cancellation First Block ..............................279
9AhR CIDMF1 Caller ID Message Format  .................................................280
9BhR CIDMF2 Caller ID Message Format  .................................................281
9ChR CIDMF3 Caller ID Message Format  .................................................282
9DhR CIDMF4 Caller ID Message Format  .................................................283
9EhR CIDMF5 Caller ID Message Format  .................................................284
9Fh R CIDMF6 Caller ID Message Format  .................................................285
A0hR UTDCTL Universal Tone Detector Control ........................................286
A1h UTDCF Center Frequency for UTD .................................................287
A2h UTDBW Band Width for UTD ...........................................................288
A3h UTDLIM  Limiter Limit for UTD  ..........................................................289
A4h UTDLEV  Minimal Signal Level for UTD .............................................290
A5h UTDDLT  Minimum Difference for UTD ..............................................291
A6h UTDTMT Tone Times for UTD ...........................................................292
A7h UTDTMG Gap Times for UTD  ............................................................293
AAhR CISCTL Caller ID Sender Control ....................................................294
ABh CISDATA Data Byte for Caller ID Sender ...........................................295
ACh CISLEV  Level of Signal for Caller ID Sender ...................................296
ADh CISSZR  Number of Seizure Bits  ......................................................297
AEh CISMRK  Number of Mark Bits  ..........................................................298
Note: Registers CCTL, RTC1, RTC2, DOUT0, DOUT1, DOUT2, DOUT3 and  DDIR are
only affected by reset, not by wakeup. For register SPSCTL see the register
description for the exact behaviour.
3.3.2 Register Naming Conventions
Several registers contain one or more fields for input signal selection. All fields labelled
I1 (I2, I3) are five bits wide and use the same coding as shown in table 107. Values not
shown in the table are reserved.
Table 107 Signal Encoding
43210SignalDescription
00000S
0Silence
00001S
1Analog line input (channel 1 of PSB 4851 interface)
00010S
2Analog line output (channel 1 of PSB 4851 interface)
00011S
3Microphone input (channel 2 of PSB 4851 interface)
00100S
4Loudspeaker/Handset output (channel 2 of PSB 
4851 interface)

PSB 4860

Data Sheet 152 2000-01-14

00101S

5Serial interface input, channel 1

00110S

6Serial interface output, channel 1

00111S

7Serial interface input, channel 2

01000S

8Serial interface output, channel 2

01001S

9DTMF generator output

01010S

10 DTMF generator auxiliary output

01011S

11 Speakerphone output (acoustic side)

01100S

12 Speakerphone output (line side)

01101S

13 Speech decoder output

01110S

14 Universal attenuator output

01111S

15 Line echo canceller output

10000S

16 AGC unit output (after AGC)

10001S

17 AGC unit output (before AGC)

10010S

18 Equalizer output

10110S

22 Caller ID sender output

10111S

23 Serial interface input, channel 3

11000S

24 Serial interface output, channel 3

Table 107 Signal Encoding

43210SignalDescription

PSB 4860

Data Sheet 153 2000-01-14

00hREV Revision

The revision register can only be read.

Note: A write access to the revision register does not change its content. It does,

however, clear the ABT bit of the STATUS register.

15 0

0001001100000000

PSB 4860

Data Sheet 154 2000-01-14

01hRCCTL Chip Control

CDIV Clock Division for Serial Flash Interface (MD0/SCLK frequency)

SFT Serial Flash Type

MV Voice Prompt Directory

0: not available

1: available (within EPROM or Flash)

EM Emergency Mode

0: normal mode

1: enter emergency mode

PD Power Down

0: is in active mode

1: enter power-down mode

15 0

CDIV SFT MV EM 0 PD 0 0 0 MQ MT CS9 SAS

Reset Value

0000000000000000

15 14 Description Example (XTAL=31.104 MHz)

0 0 XTAL:8 3.9 MHz

0 1 XTAL:16 1.9 MHz

1 0 XTAL:32 1 MHz

1 1 XTAL:64 500 kHz

13 12 Description

0 0 none

01Toshiba

10Atmel

PSB 4860

Data Sheet 155 2000-01-14

MQ Memory Quality

0: ARAM

1: DRAM

MT Memory Type

CS9 CAS selection

0: other memory

1: 256kx4 or 512kx8 memory

SAS Split Address Space

0: other ARAM/DRAM

1: two 2Mx8 devices

32Description

0 0 ARAM/DRAM

0 1 Serial flash memory

1 1 Samsung flash memory

PSB 4860

Data Sheet 156 2000-01-14

02hRINTM Interrupt Mask Register

If a bit of this register is set to 0, the corresponding bit of the status register does not

generate an interrupt.

If a bit of this register is set to 1, an external interrupt can be generated by the

corresponding bit of the status register.

15 0

RDY 1 GAP VOX CIA

CIR

CIS

CPT

UTD CNG SD 0 BSY DTV ATV DA

DRQ PQE PPI

Reset Value

0100000000000000

PSB 4860

Data Sheet 157 2000-01-14

03hRAFECTL Analog Front End Interface Control

ALS Loudspeaker Amplification

This value is transferred on channel C3 of the AFE interface. If the PSB 4851 is used it

represents the amplification of the loudspeaker amplifier.

EN Interface Enable

0: AFE interface disabled

1: AFE interface enabled

15 0

0000 ALS 0000000EN

Reset Value

0000 0 00000000

PSB 4860

Data Sheet 158 2000-01-14

04hRIFS1 Interface Select 1

The signal selection fields I1, I2 and I3 of IFS1 determine the outgoing signal of

channel 1 of the analog interface. For the PSB 4851 this is usually the line out signal.

The HP bit enables a high-pass for the incoming signal of channel 1 of the analog

interface. For the PSB 4851 this is usually the line in signal.

HP High-Pass for S1

0: Disabled

1: Enabled

I1 Input signal 1 for IG2

I2 Input signal 2 for IG2

I3 Input signal 3 for IG2

Note: As all sources are always active, unused sources must be set to 0 (S0).

15 0

HP I1 I2 I3

Reset Value

00 0 0

PSB 4860

Data Sheet 159 2000-01-14

05hRIFG1 Interface Gain 1

IFG1 is associated with the incoming signal of channel 1 of the analog interface. For the

PSB 4851 this is usually the line in signal.

IG1

In order to obtain a gain G the parameter IG1 can be calculated by the following formula:

15 0

0IG1

Reset Value

0 8192 (0 dB)

IG1 32768 G 12.04 dB–()20 dB⁄

×10=

PSB 4860

Data Sheet 160 2000-01-14

06hRIFG2 Interface Gain 2

IFG2 is associated with the outgoing signal of channel 1 of the analog interface. For the

PSB 4851 this is usually the line out signal.

IG2 Gain of Amplifier IG2

In order to obtain a gain G the parameter IG2 can be calculated by the following formula:

15 0

0IG2

Reset Value

0 8192 (0 dB)

IG2 32768 G 12.04 dB–()20 dB⁄

×10=

PSB 4860

Data Sheet 161 2000-01-14

07hRIFS2 Interface Select 2

The signal selection fields I1, I2 and I3 of IFS2 determine the outgoing signal of

channel 2 of the analog interface. For the PSB 4851 this is usually the loudspeaker

signal.

The HP bit enables a high-pass for the incoming signal of channel 2 of the analog

interface. For the PSB 4851 this is usually the microphone signal.

HP High-Pass for S3

0: Disabled

1: Enabled

I1 Input signal 1 for IG4

I2 Input signal 2 for IG4

I3 Input signal 3 for IG4

Note: As all sources are always active, unused sources must be set to 0 (S0).

15 0

HP I1 I2 I3

Reset Value

0000

PSB 4860

Data Sheet 162 2000-01-14

08hRIFG3 Interface Gain 3

IFG3 is associated with the incoming signal of channel 2 of the analog interface. For the

PSB 4851 this is usually the microphone signal.

IG3 Gain of Amplifier IG3

In order to obtain a gain G the parameter IG3 can be calculated by the following formula:

15 0

0IG3

Reset Value

0 8192 (0 dB)

IG3 32768 G 12.04 dB–()20 dB⁄

×10=

PSB 4860

Data Sheet 163 2000-01-14

09hRIFG4 Interface Gain 4

IFG4 is associated with the outgoing signal of channel 2 of the analog interface. For the

PSB 4851 this is usually the loudspeaker signal.

IG4 Gain of Amplifier IG4

In order to obtain a gain G the parameter IG4 can be calculated by the following formula:

15 0

0IG4

Reset Value

0 8192 (0 dB)

IG4 32768 G 12.04 dB–()20 dB⁄

×10=

PSB 4860

Data Sheet 164 2000-01-14

0AhRSDCONF Serial Data Interface Configuration

NTS Number of Timeslots

DCL Double Clock Mode

0: Single Clock Mode

1: Double Clock Mode

EN Enable Interface

0: Interface is disabled (both channels)

1: Interface is enabled (depending on separate channel enable bits)

15 0

00 NTS 00000DCL0EN

Reset Value

00 0 00000000

13 12 11 10 9 8 Description

0000001

0000012

... ... ... ... ... ... ...

11111164

PSB 4860

Data Sheet 165 2000-01-14

0BhRSDCHN1 Serial Data Interface Channel 1

NAS Number of active DRST strobe (SSDI interface mode)

PCD PCM Code

0: A-law

1: µ-law

EN Enable Interface

0: Interface is disabled

1: Interface is enabled if SDCONF:EN=1

PCM PCM Mode

0: 16 Bit Linear Coding (two timeslots)

1: 8 Bit PCM Coding (one timeslot)

DD Data Direction

0: DD: Data Downstream, DU: Data Upstream

1: DD: Data Upstream, DU: Data Downstream

TS Timeslot for Channel 1

15 0

NAS 0 0 PCD EN PCM DD TS

Reset Value

0 000000 0

15 14 13 12 Description

00001

... ... ... ... ...

111116

543210Description

0000000

PSB 4860

Data Sheet 166 2000-01-14

Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used.

Only even timeslots are allowed in this case.

... ... ... ... ... ... ...

11111163

543210Description

PSB 4860

Data Sheet 167 2000-01-14

0ChRIFS3 Interface Select 3

The signal selection fields I1, I2 and I3 of IFS3 determine the outgoing signal of channel

1 of the IOM/SSDI-interface.

The HP bit enables a high-pass for the incoming signal of channel 1 of the analog IOM®-

2/SSDI-interface.

HP High-Pass for S5

0: Disabled

1: Enabled

I1 Input signal 1 for S6

I2 Input signal 2 for S6

I3 Input signal 3 for S6

Note: As all sources are always active, unused sources must be set to 0 (S0).

15 0

HP I1 I2 I3

Reset Value

0000

PSB 4860

Data Sheet 168 2000-01-14

0DhRSDCHN2 Serial Data Interface Channel 2

CS Channel Split

0: Single 16 bit or single 8 bit channel

1: Two adjacent 8 bit channels (SDCHN2:PCM must be set to 0)

PCD PCM Code (for both 8 bit channels if CS=1)

0: A-law

1: µ-law

EN Enable Interface

0: Interface is disabled

1: Interface is enabled if SDCONF:EN=1

PCM PCM Mode

0: 16 Bit Linear Coding (two timeslots)

1: 8 Bit PCM Coding (one timeslot)

DD Data Direction

0: DD: Data Downstream, DU: Data Upstream

1: DD: Data Upstream, DU: Data Downstream

TS Timeslot for Channel 2

Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used.

Only even timeslots are allowed in this case.

15 0

CS00000PCDENPCMDD TS

Reset Value

0000000000 0

543210Description

0000000

0000011

... ... ... ... ... ... ...

11111163

PSB 4860

Data Sheet 169 2000-01-14

0EhRIFS4 Interface Select 4

The signal selection fields I1, I2 and I3 of IFS4 determine the outgoing signal of

channel 2 of the IOM®-2/SSDI-interface. The HP bit enables a high-pass for the

incoming signal of channel 2.

HP High-Pass for S7

0: Disabled

1: Enabled

I1 Input signal 1 for S8

I2 Input signal 2 for S8

I3 Input signal 3 for S8

Note: As all sources are always active, unused sources must be set to 0 (S0).

15 0

HP I1 I2 I3

Reset Value

0000

PSB 4860

Data Sheet 170 2000-01-14

0FhRIFG5 Interface Gain 5

ATT1 Attenuation for I3 (Channel 1)

In order to obtain an attenuation A [dB] at I3 of channel 1 of the IOM®-2/SSDI interface

(S6), the parameter ATT1 can be calculated by the following formula:

ATT2 Attenuation for I3 (Channel 2)

In order to obtain an attenuation A [dB] at I3 of channel 2 of the IOM®-2/SSDI interface

(S6), the parameter ATT1 can be calculated by the following formula:

15 0

ATT1 ATT2

Reset Value

255 (0 dB) 255 (0 dB)

ATT1 256 A20dB⁄

×10=

ATT2 256 A20dB⁄

×10=

PSB 4860

Data Sheet 171 2000-01-14

10hRUA Universal Attenuator

ATT Attenuation for UA

For a given attenuation A[dB] the parameter ATT can be calculated by the following

formula:

I1 Input Selection for UA

15 0

ATT 0 0 0 I1

Reset Value

0 (-100 dB) 0 0 0 0

ATT 256 A20dB⁄

×10=

PSB 4860

Data Sheet 172 2000-01-14

11hRDGCTL DTMF Generator Control

EN Generator Enable

0: Disabled

1: Enabled

MD Mode

0: raw

1: cooked

DTC Dial Tone Code (cooked mode)

15 0

ENMD0000000000 DTC

Reset Value

000000000000 0

3 2 1 0 Digit Frequency

0 0 0 0 1 697/1209

0 0 0 1 2 697/1336

0 0 1 0 3 697/1477

0 0 1 1 A 697/1633

0 1 0 0 4 770/1209

0 1 0 1 5 770/1336

0 1 1 0 6 770/1477

0 1 1 1 B 770/1633

1 0 0 0 7 852/1209

1 0 0 1 8 852/1336

1 0 1 0 9 852/1477

1 0 1 1 C 852/1633

1 1 0 0 * 941/1209

1 1 0 1 0 941/1336

1 1 1 0 # 941/1477

1 1 1 1 D 941/1633

PSB 4860

Data Sheet 173 2000-01-14

12hDGF1 DTMF Generator Frequency 1

FRQ Frequency of Generator 1

The parameter FRQ for a given frequency f[Hz] can be calculated by the following

formula:

15 0

0FRQ

FRQ 32768 f

4000Hz

-------------------×=

PSB 4860

Data Sheet 174 2000-01-14

13hDGF2 DTMF Generator Frequency 2

FRQ Frequency of Generator 2

The parameter FRQ for a given frequency f[Hz] can be calculated by the following

formula:

15 0

0FRQ

FRQ 32768 f

4000Hz

-------------------×=

PSB 4860

Data Sheet 175 2000-01-14

14hDGL DTMF Generator Level

LEV2 Signal Level of Generator 2

In order to obtain a signal level L (relative to the PCM maximum value) for generator 2

the value of LEV2 can be calculated according to the following formula:

LEV1 Signal Level of Generator 1

In order to obtain a signal level L (relative to the PCM maximum value) for generator 1

the value of LEV1 can be calculated according to the following formula:

15 0

0LEV20LEV1

LEV2 128 L20dB⁄

×10=

LEV1 128 L20dB⁄

×10=

PSB 4860

Data Sheet 176 2000-01-14

15hDGATT DTMF Generator Attenuation

ATT2 Attenuation of Signal S10

In order to obtain attenuation A the parameter ATT2 can be calculated by the formula:

ATT1 Attenuation of Signal S9

In order to obtain attenuation A the parameter ATT1 can be calculated by the formula:

15 0

ATT2 ATT1

ATT2 128 1024 A20dB⁄

×10+A18–1dB,<;

128 A20dB⁄

×10 A 18–1dB,>;

ATT1 128 1024 A20dB⁄

×10+A18–1dB,<;

128 A20dB⁄

×10 A 18–1dB,>;

PSB 4860

Data Sheet 177 2000-01-14

16hRCNGCTL Calling Tone Control

EN Enable

0: CNG unit disabled

1: CNG unit enabled

I1 Input Selection for Calling Tone Detector

15 0

EN0000000000 I1

Reset Value

00000000000 0

PSB 4860

Data Sheet 178 2000-01-14

17hCNGBT CNG Burst Time

TIME Minimum Time for Calling Tone

In order to obtain the parameter TIME for a minimum time t [ms] the following formula

can be used:

15 0

0TIME

TIME t 0.125 ms⁄=

PSB 4860

Data Sheet 179 2000-01-14

18hCNGLEV CNG Minimal Signal Level

MIN Minimum Signal Level for Calling Tone

In order to obtain the parameter MIN for a minimum signal level L [dB] the following

formula can be used:

15 0

00 MIN

MIN 16384 L20dB⁄

×10=

PSB 4860

Data Sheet 180 2000-01-14

19hCNGRES CNG Signal Resolution

RES Signal Resolution

The parameter RES depends on the noise level L [dB] as follows:

15 0

1111 RES

RES 4096–L20dB⁄

×10=

PSB 4860

Data Sheet 181 2000-01-14

1AhRATDCTL0 Alert Tone Detection 0

EN Enable alert tone detection

0: The alert tone detection is disabled

1: The alert tone detection is enabled

I1 Input signal selection

ATC Alert Tone Code

15 0

EN00 I1 000000 ATC

Reset Value

000 0 000000 -

1) undefined

10 Description

0 0 no tone

0 1 2130

1 0 2750

1 1 2130/2750

PSB 4860

Data Sheet 182 2000-01-14

1BhATDCTL1 Alert Tone Detection 1

MD Alert tone detection mode

0: Only dual tones will be detected

1: Either dual or single tones will be detected

DEV Maximum frequency deviation for alert tone

0: 0.5%

1: 1.1%

ONH On Hook

0: Off Hook

1: On Hook

MIN Minimum level of alert tone signal

For a minimum signal level min [dB] the parameter MIN is given by the following formula:

15 0

MD00DEV000ONH MIN

MIN 2560 min 20 dB⁄

×10=

PSB 4860

Data Sheet 183 2000-01-14

1ChRCIDCTL0 Caller ID Control 0

EN CID Enable

0: Disabled

1: Enabled

DOT Drop Out Tolerance

0: Drop out during mark or seizure sequence aborts recognition

1: Drop out tolerance during mark or seizure sequence.

CM Compatibilitiy Mode

0: Standard Caller ID Decoder

1: Improved Caller ID Decoder

I1 Input signal selection

DATA Last received data byte

15 0

EN DOT CM I1 DATA

Reset Value

000 0 0

PSB 4860

Data Sheet 184 2000-01-14

1DhCIDCTL1 Caller ID Control 1

NMB Minimum Number of Mark Bits

NMSS Minimum Number of Mark/Space Sequences

MIN Minimum Signal Level for CID Decoder

For a minimum signal level min [dB] the parameter MIN is given by the following formula:

15 0

NMB NMSS MIN

15 14 13 12 11 Description

000000

0000110

0001020

... ... ... ... ... ...

11111310

10 9 8 7 6 Description

000001

0000111

0001021

... ... ... ... ...

11111311

MIN 640 min 20 dB⁄

×10=

PSB 4860

Data Sheet 185 2000-01-14

1EhRIFS5 Interface Select 5

The signal selection fields I1, I2 and I3 of IFS5 determine the outgoing signal of channel

3 of the IOM/SSDI-interface. The HP bit enables a high-pass for the incoming signal of

channel 3.

HP High-Pass for S23

0: Disabled

1: Enabled

I1 Input signal 1 for S24

I2 Input signal 2 for S24

I3 Input signal 3 for S24

Note: As all sources are always active, unused sources must be set to 0 (S0).

15 0

HP I1 I2 I3

Reset Value

0000

PSB 4860

Data Sheet 186 2000-01-14

1FhRIFG6 Interface Gain 6

ATT3 Attenuation for I3 (Channel 3)

In order to obtain an attenuation A [dB] the parameter ATT3 can be calculated by the

following formula:

15 0

ATT3 00000000

Reset Value

255 (0dB) 00000000

ATT3 256 A20dB⁄

×10=

PSB 4860

Data Sheet 187 2000-01-14

20hRCPTCTL Call Progress Tone Control

EN CPT Detector Enable

0: Disabled

1: Enabled

MD CPT Mode

0: raw

1: cooked

I1 Input signal selection

15 0

ENMD000000000 I1

Reset Value

00000000000 0

PSB 4860

Data Sheet 188 2000-01-14

21hCPTTR Call Progress Tone Thresholds

NUM Number of Cycles

SN Minimal Signal-to-Noise Ratio

MIN Minimum Signal Level for CPT Detector

15 0

NUM 0 SN MIN

15 14 13 cooked mode raw mode

0 0 0 reserved 0

0 0 1 2 reserved

... ... ... ... reserved

1 1 1 8 reserved

11 10 9 8 Description

11119dB

100012dB

010015dB

001018dB

000022dB

Value Description

64h-30 dB

60h-32 dB

7Ah-34 dB

74h-36 dB

70h-38 dB

89h-40 dB

85h-42 dB

80h-44 dB

9Ah-46 dB

95h-48 dB

90h-50 dB

PSB 4860

Data Sheet 189 2000-01-14

22hCPTMN CPT Minimum Times

MINB Minimum Time for CPT Burst

The parameter MINB for a minimal burst time TBmin [ms] can be calculated by the

following formula:

MING Minimum Time for CPT Gap

The parameter MING for a minimal burst time TGmin [ms] can be calculated by the

following formula:

15 0

MINB MING

MINB TBmin 32 ms–

--------------------------------------=

MING TGmin 32 ms–

--------------------------------------=

PSB 4860

Data Sheet 190 2000-01-14

23hCPTMX CPT Maximum Times

MAXB Maximum Time for CPT Burst

The parameter MAXB for a maximal burst time of TBmax [ms] can be calculated by the

following formula:

MAXG Maximum Time for CPT Gap

The parameter MAXG for a maximal burst time of TGmax [ms] can be calculated by the

following formula:

15 0

MAXB MAXG

MAXB TBmax TBmin–

-----------------------------------------=

MAXG TGmax TGmin–

------------------------------------------=

PSB 4860

Data Sheet 191 2000-01-14

24hCPTDT CPT Delta Times

DIFB Maximum Time Difference between Consecutive Bursts

The parameter DIFB for a maximal difference of t[ms] of two burst durations can be

calculated by the following formula:

DIFG Maximum Time Difference between Consecutive Gaps

The parameter DIFG for a maximal difference of t[ms] of two gap durations can be

calculated by the following formula:

15 0

DIFB DIFG

DIFB t

2ms

-----------=

DIFG t

2ms

-----------=

PSB 4860

Data Sheet 192 2000-01-14

25hRLECCTL Line Echo Cancellation Control

EN Enable

0: Disabled

1: Enabled

MD Mode

0: Normal

1: Extended

CM Compatibilitiy Mode

0: Standard Line Echo Canceller

1: Improved Line Echo Canceller

AS Adaption Stop

0: Adation enabled

1: Adation stopped

I1 Input signal selection for I1

I2 Input signal selection for I2

15 0

EN MD CM AS 0 0 I1 I2

Reset Value

000000 0 0

PSB 4860

Data Sheet 193 2000-01-14

26hLECLEV Minimal Signal Level for Line Echo Cancellation

MIN

The parameter MIN for a minimal signal level L (dB) can be calculated by the following

formula:

15 0

0MIN

MIN 512 96.3 L+

()×

5 log2×

----------------------------------------=

PSB 4860

Data Sheet 194 2000-01-14

27hLECATT Externally Provided Attenuation

ATT

The parameter ATT for an externally provided attenuation A (dB) can be calculated by

the following formula:

Note: ATT has a slightly different meaning in normal and in superior mode. In normal

mode, it represents just the externally provided attenunation while in superior

mode, it represents the externally provided attenuation minus a threshold.

15 0

0ATT

ATT 512 A

5 log2×

-------------------=

PSB 4860

Data Sheet 195 2000-01-14

28hLECMGN Margin for Double Talk Detection

MGN

The parameter MGN for a margin of L (dB) can be calculated by the following formula:

Note: MGM has a different meaning in normal and in superior mode. The formula above

holds in any mode, though.

15 0

0MGN

MGN 512 L

5 log2×

-------------------=

PSB 4860

Data Sheet 196 2000-01-14

29hRDDCTL DTMF Detector Control

EN Enable DTMF tone detection

0: The DTMF detection is disabled

1: The DTMF detection is enabled

I1 Input signal selection

DTC DTMF Tone Code

15 0

EN00 I1 000 DTC

Reset Value

000 0 000 -

1) undefined

43210 Frequency Digit

1 0 0 0 0 941 / 1633 D

1 0 0 0 1 697 / 1209 1

1 0 0 1 0 697 / 1336 2

1 0 0 1 1 697 / 1477 3

1 0 1 0 0 770 / 1209 4

1 0 1 0 1 770 / 1336 5

1 0 1 1 0 770 / 1477 6

1 0 1 1 1 852 / 1209 7

1 1 0 0 0 852 / 1336 8

1 1 0 0 1 852 / 1477 9

1 1 0 1 0 941 / 1336 0

1 1 0 1 1 941 / 1209 *

1 1 1 0 0 941 / 1477 #

1 1 1 0 1 697 / 1633 A

1 1 1 1 0 770 / 1633 B

1 1 1 1 1 852 / 1633 C

PSB 4860

Data Sheet 197 2000-01-14

2AhDDTW DTMF Detector Signal Twist

TWIST Signal twist for DTMF tone

In order to obtain a minimal signal twist T the parameter TWIST can be calculated by the

following formula:

Note: TWIST must be in the range [4096,20480], which corrsponds to [8.5 dB,1.5 dB].

15 0

0TWIST

TWIST 32768 0.5 dB T+()–()10 dB⁄

×10=

PSB 4860

Data Sheet 198 2000-01-14

2BhDDLEV DTMF Detector Minimum Signal Level

MIN Minimum Signal Level

Note: Values outside the given range are reserved and must not be used.

15 0

1111111111 MIN

543210 Description

001110 -50dB

001111 -49dB

... ... ... ... ... ... ...

100001 -31dB

100010 -30dB

PSB 4860

Data Sheet 199 2000-01-14

2EhRFCFCTL Equalizer Control

EN Enable equalizer

0: The equalizer is disabled

1: The equalizer is enabled

ADR Coefficient address

15 0

EN 0 ADR 0 0 0 I

Reset Value

00 0 000 0

13 12 11 10 9 8 Coefficient

000000 A1

000001 A2

000010 A3

000011 A4

000100 A5

000101 A6

000110 A7

000111 A8

001000 A9

001001 B2

001010 B3

001011 B4

001100 B5

001101 B6

001 110 B7

001111 B8

010000 B9

010001 C1

010010 D1

010011 D2

010100 D3

010101 D4

01 0110 D5

PSB 4860

Data Sheet 200 2000-01-14

I1 Input signal selection

010111 D6

011000 D7

011001 D8

011010 D9

011011 D10

011100 D11

011101 D12

01 1 110 D13

011111 D14

100000 D15

100001 D16

100010 D17

100011 C2

13 12 11 10 9 8 Coefficient

PSB 4860

Data Sheet 201 2000-01-14

2FhFCFCOF Equalizer Coefficient Data

V Coefficient value

For the coefficient A1-A9, B2-B9 and D1-D17 the following formula can be used to

calculate V for a coefficient c:

For the coefficients C1 and C2 the following formula can be used to calculate V for a

coefficient c:

15 0

V 32768 c×=; -1c1<≤

V 128 c×=; 1c256<≤

PSB 4860

Data Sheet 202 2000-01-14

30hRSCCTL Speech Coder Control

EN Enable

0: Disabled

1: Enabled

Q1/Q0 Coder Quality

VC Voice Controlled Start of Recording

0: Disabled

1: Enabled

VOX VOX enable

0: Disabled

1: Enabled

GAP Gap Coding

0: disabled

1: enabled

I1 Input signal selection (first input)

I2 Input signal selection (second input)

15 0

EN Q1 VC Q0 VOX GAP I1 I2

Reset Value

000000 0 0

14 12 Bit rate

0 0 3300 bit/s (average)

1 0 10300 bit/s (fixed)

1 1 5600 bit/s (fixed)

PSB 4860

Data Sheet 203 2000-01-14

31hSCCT2 Speech Coder Control 2

TIME

The parameter TIME for a time t ([ms]) can be calculated by the following formula:

MIN

The parameter MIN for a signal level L ([dB]) can be calculated by the following formula:

15 0

TIME MIN

TIME t

------=

MIN 16384

------

×10=

PSB 4860

Data Sheet 204 2000-01-14

32hSCCT3 Speech Coder Control 3

The parameter LP for a time constant of t ([ms]) can be calculated by the following

formula:

GAPT

The parameter GAPT for a minimum gap time of t ([ms]) can be calculated by the

following formula:

15 0

0 LP GAPT

LP 256

---------=

GAPT t

---=

PSB 4860

Data Sheet 205 2000-01-14

33hSCDATA Speech Encoder Data

DATA

If data transfer via SCI is enabled with bit SSCTL:SCI, DATA is the data of the speach

encoder that must be read by the microcontroller

15 0

DATA

PSB 4860

Data Sheet 206 2000-01-14

34hRSDCTL Speech Decoder Control

EN Enable

0: Disabled

1: Enabled

CS Change Speed

0: All defined bits can be written

1: Only the SPEED bit field is written (for on the fly changes)

SCI Transfer Speach Data via SCI

0: Speach data is read from / written to ARAM/DRAM/Flash

1: Speach data is provided in register SCDATA/SDDATA for read/write by the

microcontroller

CP Gap Compression

0: Gaps are played back at original length

1: Gaps are skipped during replay

CN Gap Comfort Noise

0: Disabled

1: Enabled

SPEED Playback Speed

15 0

EN CS1)

1) Write only, reads as 0.

00000SCI00CPCN00 SPEED

Reset Value

00000000000000 0

1 0 Description

0 0 normal speed

0 1 0.5 times normal speed

1 0 1.5 times normal speed

1 1 2.0 times normal speed

PSB 4860

Data Sheet 207 2000-01-14

35hSDCT2 Speech Decoder Control 2

The parameter CN for the noise level does not have a dimension. It is a linear scaling

factor with 0 representing silence and 7FFFh representing the maximum value.

15 0

0CN

PSB 4860

Data Sheet 208 2000-01-14

36hSDDATA Speech Decoder Data

DATA

If data transfer via SCI is enabled with bit SSCTL:SCI, DATA is the data for the speach

decoder. The microcontroller must makle sure that this data is writtem there on request

(bit STATUS:DRQ).

15 0

DATA

PSB 4860

Data Sheet 209 2000-01-14

38hRAGCCTL AGC Control

EN Enable

0: Disabled

1: Enabled

I1 Input signal selection for I1

I2 Input signal selection for I2

15 0

EN00000 I1 I2

Reset Value

000000 0 0

PSB 4860

Data Sheet 210 2000-01-14

39hAGCATT Automatic Gain Control Attenuation

ATT

The parameter ATT for an attenuation A ([dB]) can be calculated by the following

formula:

15 0

0ATT

ATT 32768

------

×10=

PSB 4860

Data Sheet 211 2000-01-14

3AhAGC1 Automatic Gain Control 1

COM

The parameter COM for a signal level L ([dB]) can be calculated by the following formula:

AG_INIT

In order to obtain an initial gain G ([db]) the parameter AG_INIT can be calculated by the

following formula:

15 0

COM AG_INIT

COM 128 10+

L6622,+

-------------------------L -42,14 dB<;

L4214,+

-------------------------L -42,14 dB>;î

AG_INIT 128 10+

G1806,+

------------------------- G 6 02 dB,<;

G602,–

----------------------G 6 02 dB,>;

PSB 4860

Data Sheet 212 2000-01-14

3BhAGC2 Automatic Gain Control 2

SPEEDL

The parameter SPEEDL for a multiplication factor M is given by the following formula:

SPEEDH

The parameter SPEEDH for a multiplication factor M is given by the following formula:

15 0

SPEEDL SPEEDH

SPEEDL M 8192×=

SPEEDH M 256

×=

PSB 4860

Data Sheet 213 2000-01-14

3ChAGC3 Automatic Gain Control 3

AG_GAIN

The parameter AG_GAIN for a gain G ([dB]) can be calculated by the following formula:

AG_ATT

The parameter AG_ATT for an attenuation A ([dB]) can be calculated by the following

formula:

15 0

AG_GAIN 0 AG_ATT

AG_GAIN 128 10+

G1806,+

------------------------- G602dB,<;

G602,–

----------------------G602dB,>;î

AG_ATT 10

A4214,+

-------------------------

PSB 4860

Data Sheet 214 2000-01-14

3DhAGC4 Automatic Gain Control 4

DEC

The parameter DEC for a time constant t ([1/ms]) is given by the following formula:

LIM

The parameter LIM for a signal level L ([dB]) can be calculated by the following formula:

15 0

DEC LIM

DEC 256

---------=

LIM 128 10+

L903,+

----------------------L 66,22 dB–<;

L6622,+

-------------------------L 66,22 dB–>;

PSB 4860

Data Sheet 215 2000-01-14

3EhAGC5 Automatic Gain Control 5

The parameter LP for a time constant t ([1/ms]) is given by the following formula:

15 0

000000001 LP

LP 16

------=

PSB 4860

Data Sheet 216 2000-01-14

40hRFCTL File Control

MD Mode

0: Audio Mode

1: Binary Mode

MS Memory Space

0: R/W Memory

1: Voice Prompt Directory

TS Time Stamp

0: no update of RTC1/RTC2 entry of file descriptor

1: RTC1/RTC2 entries are updated by content of RTC1/RTC2 registers.

UD User Data

0: User data word is not changed

1: The contents of FDATA are written into the user data word.

FNO File Number

15 0

0MDMSTSUD000 FNO

Reset Value

00000000 0

PSB 4860

Data Sheet 217 2000-01-14

41hRFCMD File Command

REB Reserve Emergency Block

0: no

1: yes (initialize only)

IN Initialize

0: no

1: yes (if CMD = 01111 or 11001)

RD Remap Directory

0: no

1: yes

ICA Immediate Command Abort

0: no

1: yes (File command currently in progress will be finished as fast as possible.)

ABT Abort Command

0: no

1: abort recompress or garbage collection

CMD File Command

15 0

REBINRDICA0000ABT00 CMD

Reset Value

00000000000 0

43210Description

00000Open File

00001Activate

00010Seek

00011Cut File

00100Read Data

00101Write Data

PSB 4860

Data Sheet 218 2000-01-14

00110Memory Status

00111Recompress file

0 1 0 0 0 Read File Descriptor - User

0 1 0 0 1 Write File Descriptor - User / RTC2

0 1 0 1 0 Read File Descriptor - RTC1

0 1 0 1 1 Read File Descriptor - RTC2

0 1 1 0 0 Read File Descriptor - LEN

0 1 1 0 1 Garbage Collection

01110Open Next Free File

01111Initialize

10000DMA Read

10001DMA Write

10010Erase Block

10011Set Address

1 0 1 0 0 Delete Multiple Files

1 0 1 0 1 Check Voice Prompt Data Integrity

1 1 0 0 0 Write File Descriptor - RTC1 / RTC 2

1 1 0 0 1 Initialize Message Memory

43210Description

PSB 4860

Data Sheet 219 2000-01-14

42hRFDATA File Data

The FDATA register contains the following information after a memory status command:

FREE Free Blocks

Number of blocks (1 kByte) currently usable for recording.

NP Next Phrase

Next phrase enable for phrase queuing.

15 0

FREE

NP 0 0 0 0 Phrase selector

Reset Value

PSB 4860

Data Sheet 220 2000-01-14

43hRFPTR File Pointer

15 0

File Pointer

00000 Phrase selector

Reset Value

PSB 4860

Data Sheet 221 2000-01-14

45hRPDCTL Peak Detector Control

EN Peak Detector Enable

0: Disabled

1: Enabled

MM Min/Max

0: Maximum

1: Minimum

I1 Input signal selection

15 0

ENMM000000000 I1

Reset Value

00000000000 0

PSB 4860

Data Sheet 222 2000-01-14

46hPDDATA Peak Detector Data

DATA

Maximum or minimum value of signal since last read access.

Note: This register can only be read.

15 0

DATA

PSB 4860

Data Sheet 223 2000-01-14

47h RSPSCTL SPS Control

POS Position of Status Register Window

MODE Mode of SPS Interface

SP1 Direct Control for SPS1

0: SPS1 set to 0

1: SPS1 set to 1

SP0 Direct Control for SPS0

0: SPS0 set to 0

1: SPS0 set to 1

Note: If mode 1 has been selected prior to power-down, both mode 1 and the values of

SP1 and SP0 are retained during power-down and wake-up. Other modes are

reset to 0 during power down.

15 0

POS 0000000 MODE SP1SP0

Reset Value

0 0000000 0 -

1) undefined

-1)

15 14 13 12 SPS0SPS1

0000Bit 0 Bit 1

0001Bit 1 Bit 2

... ... ... ... ... ...

1 1 1 0 Bit 14 undefined

4 3 2 Description

0 0 0 Disabled (SPS0 and SPS1 zero)

0 0 1 Output of SP1 and SP0

1 0 0 Output of speakerphone state

1 0 1 Expanded address output

1 1 0 Output of STATUS register

PSB 4860

Data Sheet 224 2000-01-14

48hRRTC1 Real Time Clock 1

MIN Minutes

Number of minutes elapsed in the current hour (0-59).

SEC Seconds

Number of seconds elapsed in the current minute (0-59).

15 0

0000 MIN SEC

Reset Value

0000 0 0

PSB 4860

Data Sheet 225 2000-01-14

49hRRTC2 Real Time Clock 2

DAY Days

Number of days elapsed since last reset (0-2047).

HR Hours

Number of hours elapsed in the current day (0-23).

15 0

DAY HR

Reset Value

PSB 4860

Data Sheet 226 2000-01-14

4AhRDOUT0 Data Out (Timeslot 0)

DATA Output Data

Output data for pins MA0-MA11 while MA12=1 (only if HWCONFIG1:APP=10).

15 0

0000 DATA

Reset Value

0000 0

PSB 4860

Data Sheet 227 2000-01-14

4BhRDOUT1 Data Out (Timeslot 1)

DATA Output Data

Output data for pins MA0-MA11 while MA13=1 (only if HWCONFIG1:APP=10).

15 0

0000 DATA

Reset Value

0000 0

PSB 4860

Data Sheet 228 2000-01-14

4ChRDOUT2 Data Out (Timeslot 2)

DATA Output Data

Output data for pins MA0-MA11 while MA14=1 (only if HWCONFIG1:APP=10).

15 0

0000 DATA

Reset Value

0000 0

PSB 4860

Data Sheet 229 2000-01-14

4DhRDOUT3 Data Out (Timeslot 3 or Static Mode)

DATA Output Data

Output data for pins MA0-MA11 while MA15=1 (only if HWCONFIG1:APP=10).

Output data for pins MA0-MA15 (only if HWCONFIG1:APP=01)

15 0

DATA

Reset Value

PSB 4860

Data Sheet 230 2000-01-14

4EhDIN Data In (Timeslot 3 or Static Mode)

DATA Input Data

Input data for pins MA0-MA11 at falling edge of MA15 (only if HWCONFIG1:APP=10).

Input data for pins MA0-MA15 (only if HWCONFIG1:APP=01)

15 0

DATA

PSB 4860

Data Sheet 231 2000-01-14

4FhRDDIR Data Direction (Timeslot 3 or Static Mode)

DIR Port Direction

Port direction during MA15=1 or in static mode.

0: input

1: output

15 0

DIR

Reset Value

0 (all inputs)

PSB 4860

Data Sheet 232 2000-01-14

50hDMASK1 Data In Mask 1 (Timeslot 3 or Static Mode)

MASK Bit mask for falling edge detection

If a bit of the mask is set and the corresponding pin is configured as an input, a falling

edge at this input will set the PPI bit of the STATUS register.

15 0

MASK

PSB 4860

Data Sheet 233 2000-01-14

51hDMASK2 Data In Mask 2 (Timeslot 3 or Static Mode)

MASK Bit mask for rising edge detection

If a bit of the mask is set and the corresponding pin is configured as an input, a rising

edge at this input will set the PPI bit of the STATUS register.

15 0

MASK

PSB 4860

Data Sheet 234 2000-01-14

52hRDHOLD Data In Hold (Timeslot 3 or Static Mode)

DATA

All events, which were not masked by DMASK1 or DMASK2 register, are collected in this

is subsequently set if an unmasked event happens at the corresponding input pin.

15 0

DATA

PSB 4860

Data Sheet 235 2000-01-14

53hSCVOX1 Vox Detector 1

NFRAMES

Number of segments within a frame.

CVF

Minimum number of adjacent voice segments. (CVF=1 means no adjacent voice

segments.)

15 0

0 NFRAMES 0 CVF

PSB 4860

Data Sheet 236 2000-01-14

54hSCVOX2 Vox Detector 2

RLPF

More than this number of low power segments within a frame classify this frame as low

power.

RVF

Minimum number of voice segments within a frame to consider this frame as voice.

15 0

0RLPF0 RVF

PSB 4860

Data Sheet 237 2000-01-14

55hSCVOX3 Vox Detector 3

POWER

The parameter POWER for a reference power p ([dB]) can be calculated by the following

formula:

15 0

0POWER

POWER 32768

------

×10=

PSB 4860

Data Sheet 238 2000-01-14

56hSCVOX4 Vox Detector 4

CREST

The parameter CREST for a power difference d ([dB]) can be calculated by the following

formula:

15 0

0 CREST

POWER 32768

d–

------

×10=

PSB 4860

Data Sheet 239 2000-01-14

57hSCVOX5 Vox Detector 5

RPOWB

If there are less than this number of voice slices within a segment this segment is

considered as low power.

TIME

Minimum number of adjacent frames that do not contain CVF voice segments to set the

VOX bit.

15 0

0RPOWB0 TIME

PSB 4860

Data Sheet 240 2000-01-14

58hSCVOX6 Vox Detector 6

FLEN

Number of slices within a segment.

15 0

00000 FLEN

PSB 4860

Data Sheet 241 2000-01-14

5AhSCGAP1 Speech Coder Gap Control 1

LP2L

The parameter LP2L for a saturation level L (dB) can be calculated by the following

formula:

LIM

The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be

calculated by the following formula:

15 0

0LP2L0 LIM

LP2L 2L

5 log2×

-------------------=

LIM 2 96.3 L+

()×

5 log2×

----------------------------------=

PSB 4860

Data Sheet 242 2000-01-14

5BhSCGAP2 Speech Coder Gap Control 2

LP1

The parameter LP1 for a time t (ms) can be calculated by the following formula:

OFF

The parameter OFF for a level offset of O (dB) can be calculated by the following

formula:

15 0

LP1 0 OFF

LP1 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

OFF 2O

5 log2×

-------------------=

PSB 4860

Data Sheet 243 2000-01-14

5ChSCGAP3 Speech Coder Gap Control 3

PDN

The parameter PDN for a time t (ms) can be calculated by the following formula:

LP2N

The parameter LP2N for a time t (ms) can be calculated by the following formula:

15 0

PDN LP2N

PDN 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

LP2N 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

PSB 4860

Data Sheet 244 2000-01-14

5DhSCGAP4 Speech Coder Gap Control 4

PDS

The parameter PDS for a time t (ms) can be calculated by the following formula:

LP2S

The parameter LP2S for a time t (ms) can be calculated by the following formula:

15 0

PDS 0 LP2S

PDS 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

LP2S 262144

------------------=

PSB 4860

Data Sheet 245 2000-01-14

60h RSCTL Speakerphone Control

ENS Enable Echo Suppression

0: The echo suppression unit is disabled

1: The echo suppression unit is enabled

ENC Enable Echo Cancellation

0: The echo cancellation unit is disabled

1: The echo cancellation unit is enabled

MD Mode

0: Speakerphone mode

1: Loudhearing mode

SDR Signal Source of SDR

0: after AGCR

1: before AGCR

SDX Signal Source of SDX

0: after AGCX

1: before AGCX

AGR AGCR Enable

0: AGCR disabled

1: AGCR enabled

AGX AGCX Enable

0: AGCX disabled

1: AGCX enabled

15 0

ENSENC000000MDSDRSDX00AGRAGX0

Reset Value

0000000000000000

PSB 4860

Data Sheet 246 2000-01-14

62hRSSRC1 Speakerphone Source 1

I1 Input Signal Selection (Acoustic Source 1)

I2 Input Signal Selection (Acoustic Source 2)

15 0

000000 I1 I2

Reset Value

000000 0 0

PSB 4860

Data Sheet 247 2000-01-14

63hRSSRC2 Speakerphone Source 2

I3 Input Signal Selection (Line Source 1)

I4 Input Signal Selection (Line Source 2)

15 0

000000 I3 I4

Reset Value

000000 0 0

PSB 4860

Data Sheet 248 2000-01-14

64hSSDX1 Speech Detector (Transmit) 1

LP2L

The parameter LP2L for a saturation level L (dB) can be calculated by the following

formula:

LIM

The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be

calculated by the following formula:

15 0

0LP2L0 LIM

LP2L 2L

5 log2×

-------------------=

LIM 2 96.3 L+

()×

5 log2×

----------------------------------=

PSB 4860

Data Sheet 249 2000-01-14

65hSSDX2 Speech Detector (Transmit) 2

LP1

The parameter LP1 for a time t (ms) can be calculated by the following formula:

OFF

The parameter OFF for a level offset of O (dB) can be calculated by the following

formula:

15 0

LP1 0 OFF

LP1 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

OFF 2O

5 log2×

-------------------=

PSB 4860

Data Sheet 250 2000-01-14

66hSSDX3 Speech Detector (Transmit) 3

PDN

The parameter PDN for a time t (ms) can be calculated by the following formula:

LP2N

The parameter LP2N for a time t (ms) can be calculated by the following formula:

15 0

PDN LP2N

PDN 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

LP2N 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

PSB 4860

Data Sheet 251 2000-01-14

67hSSDX4 Speech Detector (Transmit) 4

PDS

The parameter PDS for a time t (ms) can be calculated by the following formula:

LP2S

The parameter LP2S for a time t (ms) can be calculated by the following formula:

15 0

PDS 0 LP2S

PDS 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

LP2S 262144

------------------=

PSB 4860

Data Sheet 252 2000-01-14

68hSSDR1 Speech Detector (Receive) 1

LP2L

The parameter LP2L for a saturation level L (dB) can be calculated by the following

formula:

LIM

The parameter LIM for a minimum signal level L (dB, relative to PCM max. value) can be

calculated by the following formula:

15 0

0LP2L0 LIM

LP2L 2L

5 log2×

-------------------=

LIM 2 96.3 L+

()×

5 log2×

----------------------------------=

PSB 4860

Data Sheet 253 2000-01-14

69hSSDR2 Speech Detector (Receive) 2

LP1

The parameter LP1 for a time t (ms) can be calculated by the following formula:

OFF

The parameter OFF for a level offset of O (dB) can be calculated by the following

formula:

15 0

LP1 0 OFF

LP1 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

OFF 2O

5 log2×

-------------------=

PSB 4860

Data Sheet 254 2000-01-14

6AhSSDR3 Speech Detector (Receive) 3

PDN

The parameter PDN for a time t (ms) can be calculated by the following formula:

LP2N

The parameter LP2N for a time t (ms) can be calculated by the following formula:

15 0

PDN LP2N

PDN 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

LP2N 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

PSB 4860

Data Sheet 255 2000-01-14

6BhSSDR4 Speech Detector (Receive) 4

PDS

The parameter PDS for a time t (ms) can be calculated by the following formula:

LP2S

The parameter LP2S for a time t (ms) can be calculated by the following formula:

15 0

PDS 0 LP2S

PDS 64 t

⁄0.5 t 64<<;

128 2048 t

⁄+ 16.2 t 2048<<;

LP2S 262144

------------------=

PSB 4860

Data Sheet 256 2000-01-14

6ChSSCAS1 Speech Comparator (Acoustic Side) 1

The parameter G for a gain A (dB) can be calculated by the following formula:

Note: The parameter G is interpreted in two’s complement.

The parameter ET for a time t (ms) can be calculated by the following formula:

15 0

GET

G2A

5 log2×

-------------------=

ET t

---=

PSB 4860

Data Sheet 257 2000-01-14

6DhSSCAS2 Speech Comparator (Acoustic Side) 2

GDN

The parameter GDN for a gain G (dB) can be calculated by the following formula:

PDN

The parameter PDN for a decay rate R (ms/dB) can be calculated by the following

formula:

15 0

0GDN PDN

GDN 4G

5 log2×

-------------------=

PDN 64

5 log2 R

××

------------------------------=

PSB 4860

Data Sheet 258 2000-01-14

6EhSSCAS3 Speech Comparator (Acoustic Side) 3

GDS

The parameter GDS for a gain G (dB) can be calculated by the following formula:

PDS

The parameter PDS for a decay rate R (ms/dB) can be calculated by the following

formula:

15 0

0GDS PDS

GDS 4G

5 log2×

-------------------=

PDS 64

5 log2 R

××

------------------------------=

PSB 4860

Data Sheet 259 2000-01-14

6FhSSCLS1 Speech Comparator (Line Side) 1

The parameter G for a gain A (dB) can be calculated by the following formula:

Note: The parameter G is interpreted in two’s complement.

The parameter ET for a time t (ms) can be calculated by the following formula:

15 0

GET

G2A

5 log2×

-------------------=

ET t

---=

PSB 4860

Data Sheet 260 2000-01-14

70hSSCLS2 Speech Comparator (Line Side) 2

GDN

The parameter GDN for a gain G (dB) can be calculated by the following formula:

PDN

The parameter PDN for a decay rate R (ms/dB) can be calculated by the following

formula:

15 0

0GDN PDN

GDN 4G

5 log2×

-------------------=

PDN 64

5 log2 R

××

------------------------------=

PSB 4860

Data Sheet 261 2000-01-14

71hSSCLS3 Speech Comparator (Line Side) 3

GDS

The parameter GDS for a gain G (dB) can be calculated by the following formula:

PDS

The parameter PDS for a decay rate R (ms/dB) can be calculated by the following

formula:

15 0

0GDS PDS

GDS 4G

5 log2×

-------------------=

PDS 64

5 log2 R

××

------------------------------=

PSB 4860

Data Sheet 262 2000-01-14

72hSATT1 Attenuation Unit 1

ATT

The parameter ATT for an attenuation A (dB) can be calculated by the following formula:

The parameter SW for a switching rate R (ms/dB) can be calculated by the following

formula:

15 0

0ATT SW

ATT 2A

5 log2×

-------------------=

128 1

5log2

×R×

------------------------------+ 0.0053 R 0.66<<;

5log2

×R×

------------------------------ 0.66 R 0.63<<;

PSB 4860

Data Sheet 263 2000-01-14

73hSATT2 Attenuation Unit 2

The parameter TW for a time t (ms) can be calculated by the following formula:

The parameter DS for a decay rate R (ms/dB) can be calculated by the following formula:

Note: The value 0xFF for the parameter DS specifies an infinite decay rate. Therefore

the speakerphone will not return to the idle state in the absence of speech signals.

It will remain in the current state until a speech signal is detected and a state

change is necessary.

15 0

TW DS

TW t

------=

DS 5 log2

×R1–×

---------------------------------------=

PSB 4860

Data Sheet 264 2000-01-14

74hSAGX1 Automatic Gain Control (Transmit) 1

AG_INIT

The parameter AG_INIT for a gain G (dB) can be calculated by the following formula:

Note: This parameter is interpreted in two’s complement.

COM

The threshold COM for a level L (dB) can be calculated by the following formula:

15 0

AG_INIT 0 COM

AG_INIT 2–G

5log2×

-------------------=

COM 2 96.3 L+

()×

5 log2×

----------------------------------=

PSB 4860

Data Sheet 265 2000-01-14

75hSAGX2 Automatic Gain Control (Transmit) 2

AG_ATT

The parameter AG_ATT for a gain G (dB) can be calculated by the following formula:

SPEEDH

The parameter SPEEDH for the regulation speed R (ms/dB) can be calculated by the

following formula:

The variable D denotes the aberration (dB).

15 0

0 AG_ATT SPEEDH

AG_ATT 2–G

5 log2×

-------------------=

SPEEDH 512

--------------=

PSB 4860

Data Sheet 266 2000-01-14

76hSAGX3 Automatic Gain Control (Transmit) 3

AG_GAIN

The parameter AG_GAIN for a gain G (dB) can be calculated by the following formula:

SPEEDL

The parameter SPEEDL for the regulation speed R (ms/dB) can be calculated by the

following formula:

The variable D denotes the aberration (dB).

15 0

AG_GAIN SPEEDL

AG_GAIN 2–G

5 log2×

-------------------=

SPEEDL 4096

--------------=

PSB 4860

Data Sheet 267 2000-01-14

77hSAGX4 Automatic Gain Control (Transmit) 4

NOIS

The parameter NOIS for a threshold level L (dB) can be calculated by the following

formula:

LPA

The parameter LPA for a low pass time constant T (ms) can be calculated by the

following formula:

15 0

0NOIS0 LPA

NOIS 296.3L+

()×

5 log2×

----------------------------------=

LPA 16

------=

PSB 4860

Data Sheet 268 2000-01-14

78hSAGX5 Automatic Gain Control (Transmit) 5

AG_CUR

The current gain G (dB) of the AGC can be derived from the parameter Parameter

AG_CUR by the following formula:

Note: AG_CUR is interpreted in two’s complement.

15 0

AG_CUR 00000000

G5–log2 AG_CUR

××

-----------------------------------------------------=

PSB 4860

Data Sheet 269 2000-01-14

79hSAGR1 Automatic Gain Control (Receive) 1

AG_INIT

The parameter AG_INIT for a gain G (dB) can be calculated by the following formula:

Note: This parameter is interpreted in two’s complement.

COM

The parameter COM for a threshold L (dB) can be calculated by the following formula:

15 0

AG_INIT 0 COM

AG_INIT 2–G

5log2×

-------------------=

COM 2 96.3 L+

()×

5 log2×

----------------------------------=

PSB 4860

Data Sheet 270 2000-01-14

7AhSAGR2 Automatic Gain Control (Receive) 2

AG_ATT

The parameter AG_ATT for a gain G (dB) can be calculated by the following formula:

SPEEDH

The parameter SPEEDH for the regulation speed R (ms/dB) can be calculated by the

following formula:

The variable D denotes the aberration (dB).

15 0

0 AG_ATT SPEEDH

AG_ATT 2–G

5 log2×

-------------------=

SPEEDH 512

--------------=

PSB 4860

Data Sheet 271 2000-01-14

7BhSAGR3 Automatic Gain Control (Receive) 3

AG_GAIN

The parameter AG_GAIN for a gain G (dB) can be calculated by the following formula:

SPEEDL

The parameter SPEEDL for the regulation speed R (ms/dB) can be calculated by the

following formula:

The variable D denotes the aberration (dB).

15 0

AG_GAIN SPEEDL

AG_GAIN 2–G

5 log2×

-------------------=

SPEEDL 4096

--------------=

PSB 4860

Data Sheet 272 2000-01-14

7ChSAGR4 Automatic Gain Control (Receive) 4

NOIS

The parameter NOIS for a threshold level L (dB) can be calculated by the following

formula:

LPA

The parameter LPA for a low pass time constant T (mS) can be calculated by the

following formula:

15 0

0NOIS0 LPA

COM 2 96.3 L+

()×

5 log2×

----------------------------------=

LPA 16

------=

PSB 4860

Data Sheet 273 2000-01-14

7DhSAGR5 Automatic Gain Control (Receive) 5

AG_CUR

The current gain G (dB) of the AGCR can be derived from the parameter AG_CUR by

the following formula:

Note: AG_CUR is interpreted in two’s complement.

15 0

AG_CUR 00000000

G5–log2 AG_CUR

××

-----------------------------------------------------=

PSB 4860

Data Sheet 274 2000-01-14

7EhSLGA Line Gain

LGAR

The parameter LGAR for a gain G (dB) is given by the following formula:

LGAX

The parameter LGAX for a gain G (dB) is given by the following formula:

15 0

0LGAR0LGAX

LGAR 128 G12–()20⁄

×10=

LGAX 128 G12–()20⁄

×10=

PSB 4860

Data Sheet 275 2000-01-14

80hSAELEN Acoustic Echo Cancellation Length

LEN

LEN denotes the number of FIR-taps used.

Recommended values are: 127, 255, 383, 511

15 0

0000000 LEN

PSB 4860

Data Sheet 276 2000-01-14

81hSAEATT Acoustic Echo Cancellation Double Talk Attenuation

ATT

The parameter ATT for an attenuation A (dB) is given by the following formula:

15 0

0ATT

ATT 512 A

5 log2×

-------------------=

PSB 4860

Data Sheet 277 2000-01-14

82hSAEGS Acoustic Echo Cancellation Global Scale

All coefficients of the FIR filter are scaled by a factor C. This factor is given by the

following equation:

15 0

0000000000000 GS

PSB 4860

Data Sheet 278 2000-01-14

83hSAEPS1 Acoustic Echo Cancellation Partial Scale

The additional scaling coefficient AC is given by the following formula:

15 0

0000000000000 PS

AC 2PS

PSB 4860

Data Sheet 279 2000-01-14

84hSAEPS2 Acoustic Echo Cancellation First Block

The parameter FB denotes the first block that is affected by the partial scaling coefficient.

If the partial coefficient is one, FB is disregarded.

15 0

0000000000000 FB

PSB 4860

Data Sheet 280 2000-01-14

9AhRCIDMF1 Caller ID Message Format

MF Message Format

Valid start byte.

15 0

0MF

Reset Value

PSB 4860

Data Sheet 281 2000-01-14

9BhRCIDMF2 Caller ID Message Format

MF Message Format

Valid start byte.

15 0

0MF

Reset Value

PSB 4860

Data Sheet 282 2000-01-14

9ChRCIDMF3 Caller ID Message Format

MF Message Format

Valid start byte.

15 0

0MF

Reset Value

PSB 4860

Data Sheet 283 2000-01-14

9DhRCIDMF4 Caller ID Message Format

MF Message Format

Valid start byte.

15 0

0MF

Reset Value

PSB 4860

Data Sheet 284 2000-01-14

9EhRCIDMF5 Caller ID Message Format

MF Message Format

Valid start byte.

15 0

0MF

Reset Value

PSB 4860

Data Sheet 285 2000-01-14

9FhRCIDMF6 Caller ID Message Format

MF Message Format

Valid start byte.

15 0

0MF

Reset Value

PSB 4860

Data Sheet 286 2000-01-14

A0hRUTDCTL Universal Tone Detector Control

EN UTD Detector Enable

0: Disabled

1: Enabled

I1 Input signal selection

15 0

EN0000000000 I1

Reset Value

00000000000 0

PSB 4860

Data Sheet 287 2000-01-14

A1hUTDCF Center Frequency for UTD

The parameter CF for a center frequency f (Hz) can be calculated by the following

formula:

Note: The parameter CF is implemented in two’s complement.

15 0

CF 32768 2π× f×

8000

--------------------

èø

æö

cos×=

PSB 4860

Data Sheet 288 2000-01-14

A2hUTDBW Band Width for UTD

The parameter BW for a band width B (Hz) can be calculated by the following formula:

15 0

0BW

BW 65536 πB×8000⁄()tan

1πB 8000⁄×()tan+

----------------------------------------------------

×=

PSB 4860

Data Sheet 289 2000-01-14

A3hUTDLIM Limiter Limit for UTD

LIM Signal Limit

The parameter LIM for a limit of L[dB] can be calculated by the following formula:

15 0

0LIM

LIM 32768 L20⁄

×10=

PSB 4860

Data Sheet 290 2000-01-14

A4hUTDLEV Minimal Signal Level for UTD

LEV Minimal level of signal

The parameter LEV for a minimum in-band signal level of L[dB] can be calculated by the

following formula:

15 0

0LEV

LEV 32768 L20⁄

×10=

PSB 4860

Data Sheet 291 2000-01-14

A5hUTDDLT Minimum Difference for UTD

DELTA Minimal difference between in-band signal and out-of-band signal

The parameter DELTA for a signal difference of d [dB] can be calculated by the following

formula:

15 0

DELTA

DELTA d()sgn 32768×d()20⁄–

×10=

PSB 4860

Data Sheet 292 2000-01-14

A6hUTDTMT Tone Times for UTD

TTONE Minimum Time for Activation

The parameter TTONE for a minimal activation time t [ms] can be calculated by the

following formula:

TB1 Maximum Break Time for TTONE

The parameter TB1 for a maximum break time is given in milliseconds.

15 0

TTONE TB1

TTONE t

---=

PSB 4860

Data Sheet 293 2000-01-14

A7hUTDTMG Gap Times for UTD

TGAP Minimum Time for Deactivation

The parameter TGAP for a minimal deactivation time t [ms] can be calculated by the

following formula:

TB2 Maximum Break Time for TGAP

The parameter TB2 for a maximum break time is given in milliseconds.

15 0

TGAP TB2

TGAP t

---=

PSB 4860

Data Sheet 294 2000-01-14

AAhRCISCTL Caller ID Sender Control

EN Caller ID Sender Enable

0: Disabled

1: Enabled

MD Mode

0: V.23

1: Bellcore

15 0

ENMD00000000000000

Reset Value

0000000000000000

PSB 4860

Data Sheet 295 2000-01-14

ABhCISDATA Data Byte for Caller ID Sender

DATA Data byte to send

A write access to this registers resets the status bits CIS and CIR.

15 0

00000000 DATA

PSB 4860

Data Sheet 296 2000-01-14

AChCISLEV Level of Signal for Caller ID Sender

LEV Signal Level

The parameter LEV for a level of L [dB] can be calculated by the following formula:

15 0

0LEV

LEV 32768 L6+()20⁄

×10=

PSB 4860

Data Sheet 297 2000-01-14

ADhCISSZR Number of Seizure Bits

SEIZ Number of Seizure Bits

The number of seizure bits to be sent before a data transmission.

15 0

0 SEIZ

PSB 4860

Data Sheet 298 2000-01-14

AEhCISMRK Number of Mark Bits

MARK Number of Mark Bits

The number of mark bits to be sent before a data transmission.

15 0

0MARK

PSB 4860

Data Sheet 299 2000-01-14

4 Electrical Characteristics

Electrical Charac teristics

4.1 Absolute Maximum Ratings

ESD integrity (according MIL-Std. 883D, method 3015.7): 2 kV

Exception: The pins INT, SDX, DU/DX, DD/DR, SPS0, SPS1 and MD0-MD7 are not

protected against voltage stress >1 kV.

Note: Conditions: Maximum ratings are stress ratings only, and functional operation and

reliability under conditions beyond those defined in the "recommended operating

conditions" is not guaranteed. Stresses above the maximum ratings are likely to

cause permant damage.

4.2 DC Characteristics

Parameter Symbol Limit Values Unit

Ambient temperature under bias TA-20 to 85 °C

Storage temperature TSTG – 65 to125 °C

Supply Voltage VDD -0.5 to 4.2 V

Supply Voltage VDDA -0.5 to 4.2 V

Voltage of pin with respect to ground:

OSC1, OSC2, XTAL1, XTAL2

VS0 to VDDA V

Voltage on any pin with respect to ground (except

OSC1, OSC2, XTAL1, XTAL2)

VS– 0.4 to 5.51)

1) The difference from the minumum to the maximum value for VS/VDD/VSS at any pin must never exceed 5.5 V.

VDD/VDDA = 3.3 V ± 0.3 V; VSS/VSSA = 0 V; TA = 0 to 70 °C

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Input leakage current IIL – 5.0 5.0 µA0V≤VIN ≤VDD

H-input level (except MA0-MA15,

XTAL1, OSC1)

VIH1 2.0 5.51) V

H-input level (XTAL1, OSC1)VIH2 0.8

VDD

VDDA +

0.3

H-input level (MA0-MA15, MCTL2))VIH3 2.0 VDD +

0.3

L-input level (except pins

XTAL1,OSC1)

VIL1 – 0.3 0.8 V

PSB 4860

Data Sheet 300 2000-01-14

4.3 AC Characteristics

Digital inputs are driven to 2.4 V for a logical “1” and to 0.45 V for a logical “0”. Timing

measurements are made at 2.0 V for a logical “1” and 0.8 V for a logical “0”. The AC-

testing input/output waveforms are shown below.

L-input level (XTAL1, OSC1)VIL2 – 0.3 0.2

VDDA

H-output level (except DU/DX, DD/

DR, MA0-MA15)

VOH1 VDD –

0.45

VIO = 2 mA

H-output level (MA0-MA15)VOH3 VDD –

0.45

VIO = 5 mA

H-output level (DU/DX, DD/DR) VOH4 VDD –

0.45

VIO = 7 mA

L-output level (except DU/DX, DD/

DR, MA0-MA15)

VOL1 0.45 V IO = – 2 mA

L-output level (MA0-MA15)

(address mode or APP output)

VOL2 0.45 V IO = – 5 mA

L-output current (MA0-MA15)

(after reset)

ILO 55 102 200 µARST=1

H-output current (MCTL1))IHO 55 100 157 µARST=1

L-output level (pins DU/DX, DD/

DR)

VOL3 0.45 V IO = – 7 mA

Internal pullup current (FRDY)ILI 370 680 950 µA

Input capacitance CI10 pF

Output capacitance CO15 pF

VDD+VDDA supply current

(power down, no refresh, no RTC)

IDDS1 10 50 µA

VDD+VDDA supply current

operating

IDDO 50 60 mA VDD = 3.3 V

1) The difference from the minumum to the maximum value for VS/VDD/VSS at any pin must never exceed 5.5 V.

2) MCTL signals are (W/FWE, VPRD/FCLE, RAS/FOE, CAS0/ALE, CAS1/FCS)

VDD/VDDA = 3.3 V ± 0.3 V; VSS/VSSA = 0 V; TA = 0 to 70 °C

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

PSB 4860

Data Sheet 301 2000-01-14

Figure 81 Input/Output Waveforms for AC-Tests

PSB 4860

Data Sheet 302 2000-01-14

DTMF Detector

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Frequency deviation accept -1.5 1.5 %

Frequency deviation reject 3.5 -3.5 %

Acceptance level -45 0 dB rel. to max. PCM

Rejection level -50 dB rel. to max. PCM

Twist deviation accept +/-2 +/-8 dB programmable

Noise Tolerance 12 dB

Signal duration accept 40 ms

Signal duration reject 23 ms

Gap duration accept 40 ms

Gap duration reject 23 ms

CPT Detector

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Frequency acceptance range 300 640 Hz

Frequency rejection range 800 200 Hz

Acceptance level -45 0 dB rel. to max. PCM

Rejection level -50 dB rel. to max. PCM

Signal duration accept 50 ms programmable

Signal duration reject 10 ms

Caller ID Decoder

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Frequency deviation accept -2 2 %

Acceptance level -45 0 dB rel. to max. PCM

Transmission rate 1188 1200 1212 baud

Noise Tolerance (CM=1), out

of band

-12 dB

Noise Tolerance (CM=1), in

band

25 dB 200 to 3200 Hz

PSB 4860

Data Sheet 303 2000-01-14

Alert Tone Detector

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Frequency deviation accept -0.5 0.5 % ATDCTL1:DEV=0

Frequency deviation accept -1.1 1.1 % ATDCTL1:DEV=1

Frequency deviation reject 3.5 -3.5 %

Acceptance level -40 0 dB rel. to max. PCM

Rejection level -5 dB rel. to acceptance level

Twist deviation accept +/-7 dB

Noise Tolerance 20 dB

Signal duration accept 75 ms

Gap duration accept (off-hook) 50 ms ATDCTL1:ONH=0

Gap duration accept (on-hook) 16 ms ATDCTL1:ONH=1

CNG Detector

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Frequency deviation accept -30 30 Hz

Frequency deviation reject -50 50 Hz

Acceptance level -45 0 dB SNR >10 dB

Acceptance level -50 0 dB SNR >15 dB

Rejection level -5 dB dB rel. to CNGLEV:MIN

Signal duration reject -1 % rel. to CNGBT:TIME

PSB 4860

Data Sheet 304 2000-01-14

Status Register Update Time

The individual bits of the STATUS register may change due to an event (like a

recognized DTMF tone) or a command. The timing can be divided into four classes

With these definitions the timing of the individual bits in the STATUS register can be

given as shown in table:

Table 108 Status Register Update Timing

Class Timing Comment

Min. Max.

I 0 0 Immediately after command has been issued

A 0 150 µs1)

1) 250 us if speakerphone enabled

Command has been accepted

E - - Associated event has happened

Bit RDY ABT CIA CD CPT CNG SD ERR BSY DTV ATV

0->1 AEEEEEEEAEE

1->0 I A AE,AE,AAE,AA EE,AE,A

Bit GAP VOX PQE PPI

0->1 EEEE

1->0 E,A E,A E A

PSB 4860

Data Sheet 305 2000-01-14

Figure 82 Oscillator Circuits

Note: This generally recommended circuity and the values must be verified for each

board design. Please use the appropriate Application Note for doing so.

Furthermore, the provider of the crystal must be consulted for verification of the

circuitry.

Recommended / Maximum Values

Oscillator Circuit

Value Unit

Min Typ Max

Main Oscillator

Crystal Load Capacitance CL12

Ext. Capacitors CA1= CA2 @ 34.560MHz 5 8.2 12 pF

Ext. Capacitors CA1= CA2 @ 31.104MHz 5 10 15 pF

Static (parallel) capacitance X17pF

Resonance resistance X140 Ω

Frequency deviation 5001)

1) The frequency deviation must not exceed 500 ppm if AFE clock tracking (bit ACT in register HWCONFIG1) is

enabled.

ppm

Auxilliary Oscillator (f = 32.768kHz)

Crystal Load Capacitance CL10 pF

Ext. Capacitors CB1= CB2 520pF

Static Capacitance X23pF

Resonance resistor X240 kΩ

XTAL1

XTAL2

CA1

CA2

OSC1

OSC2

CB1

CB2

Main Oscillator Auxilliary Oscillator

PSB 4860

Data Sheet 306 2000-01-14

Figure 83 SSDI/IOM®-2 Interface - Bit Synchronization Timing

Figure 84 SSDI/IOM®-2 Interface - Frame Synchronization Timing

Parameter

SSDI/IOM®-2 Interface

Symbol Limit values Unit

Min Max

DCL period t1 90 ns

DCL high t2 35 ns

DCL low t335 ns

Input data setup t4 20 ns

DD/DR

DCL

DU/DX

first bit last bit

bit n bit n+1

t6t7

FSC

DCL

t9t10

PSB 4860

Data Sheet 307 2000-01-14

Input data hold t520 ns

Output data from high impedance to active

(FSC high or other than first timeslot)

t6 30 ns

Output data from active to high impedance t7 30 ns

Output data delay from clock t830 ns

FSC setup t940 ns

FSC hold t10 40 ns

FSC jitter (deviation per frame) -200 200 ns

Parameter

SSDI/IOM®-2 Interface

Symbol Limit values Unit

Min Max

PSB 4860

Data Sheet 308 2000-01-14

Figure 85 SSDI Interface - Strobe Timing

Parameter

SSDI Interface

Symbol Limit values Unit

Min Max

DXST delay t120 ns

DRST inactive setup t220 ns

DRST inactive hold t320 ns

DRST active setup t420 ns

DRST active hold t520 ns

FSC setup t68 DCL cycles

FSC hold t740 ns

DRST

DCL

t4t5

t2t3

FSC

t6t7

DXST

PSB 4860

Data Sheet 309 2000-01-14

Figure 86 Serial Control Interface

Parameter

SCI Interface

Symbol Limit values Unit

Min Max

SCLK cycle time t1500 ns

SCLK high time t2 100 ns

SCLK low time t3 100 ns

CS setup time t4 40 ns

CS hold time t510 ns

SDR setup time t6 40 ns

SDR hold time t7 40 ns

SDX data out delay t8 80 ns

CS high to SDX tristate t940 ns

SCLK to SDX active t10 80 ns

SCLK to SDX tristate t11 40 ns

CS to INT delay t12 80 ns

SCLK

SDR

SDX

INT

t4t2t3

t12

t10

t11

t6t7

PSB 4860

Data Sheet 310 2000-01-14

Figure 87 Analog Front End Interface

Parameter

AFE Interface

Symbol Limit values Unit

Min Max

AFECLK period t1 125 165 ns

AFECLK high t2 21/f

XTAL

AFECLK low t321/f

XTAL

AFEDU setup t4 20 ns

AFEDU hold t520 ns

AFEDD output delay t630 ns

AFEFS output delay t730 ns

AFEDU

AFECLK

AFEDD bit n bit n+1

AFEFS

PSB 4860

Data Sheet 311 2000-01-14

Figure 88 Memory Interface - DRAM Read Access

Parameter

Memory Interface - DRAM Read Access

Symbol Limit values Unit

Min Max

row address setup time t1 50 ns

row address hold time t2 50 ns

column address setup time t350 ns

RAS precharge time t4 110 ns

RAS to CAS delay t5110 2000 ns

CAS pulse width t6 110 2000 ns

Data input setup time t7 40 ns

Data input hold time t80ns

MA0-MA13

MD0-MD7

CAS0,CAS1

RAS

row addr. col. addr.

t1t2

t7t8

PSB 4860

Data Sheet 312 2000-01-14

Figure 89 Memory Interface - DRAM Write Access

Parameter

Memory Interface - DRAM Write Access

Symbol Limit values Unit

Min Max

row address setup time t1 50 ns

row address hold time t2 50 ns

column address setup time t350 ns

RAS precharge time t4 110 ns

RAS to CAS delay t5110 2000 ns

CAS pulse width t6 110 2000 ns

Data output setup time t7100 ns

Data output hold time t850 ns

RAS to W delay t950 ns

W to CAS setup t10 50 ns

MA0-MA13

MD0-MD7

CAS0,CAS1

RAS

row addr. col. addr.

t1t2

t7t8

t9t10

PSB 4860

Data Sheet 313 2000-01-14

Figure 90 Memory Interface - DRAM Refresh Cycle

Note: The frequency of the DRAM refresh cycle depends on the selected mode. In active

mode or normal refresh mode (during power down) the minimal frequency is 64

kHz. In battery backup mode, the refresh frequency is 8 kHz.

Parameter

Memory Interface - DRAM Refresh Cycle

Symbol Limit values Unit

Min Max

RAS precharge time t1 100 ns

RAS low time t2 200 5000 ns

CAS setup t3100 ns

CAS hold t4 100 ns

CAS0,CAS1

RAS

t1t2

PSB 4860

Data Sheet 314 2000-01-14

Figure 91 Memory Interface - EPROM Read

Parameter

Memory Interface - EPROM Read

Symbol Limit values Unit

Min Max

Address setup before VPRD t1 110 ns

VPRD low time t2 500 ns

Data setup time t340 ns

Data hold time t4 0ns

MA0-MA15

MD0-MD7

VPRD

linear address

t1t2

t3t4

PSB 4860

Data Sheet 315 2000-01-14

Figure 92 Memory Interface - Samsung Command Write

Note: FCS stays low if other cycles follow for the same access.

Parameter

Memory Interface - Samsung Command

Write

Symbol Limit values Unit

Min Max

Address setup before FCS, FCLE t1 100 ns

FCS low time, FCLE high time t2 400 ns

FWR hold after FCLE rising t3100 ns

FWR low time t4 200 ns

FWR setup before FCLE falling t5100 ns

Data setup time t6200 ns

Data hold time t750 ns

MA0-MA11

MD0-MD7

FCS(FCS0-FCS3)

A16-A23 and FCS0-FCS3

FWR

FCLE

t3t4t5

t6t7

PSB 4860

Data Sheet 316 2000-01-14

Figure 93 Memory Interface - Samsung Address Write

Parameter

Memory Interface - Samsung Address

Write

Symbol Limit values Unit

Min Max

ALE high time t1 400 ns

FWR hold after ALE rising t2100 ns

FWR low time t3 200 ns

FWR setup before ALE falling t4100 ns

Data setup time t5200 ns

Data hold time t650 ns

MD0-MD7

FWR

ALE

t2t3t4

t5t6

PSB 4860

Data Sheet 317 2000-01-14

Figure 94 Memory Interface - Samsung Data Write

Parameter

Memory Interface - Samsung Data Write

Symbol Limit values Unit

Min Max

FWR low time t1 200 ns

Data setup time t2200 ns

Data hold time t350 ns

MD0-MD7

FWR

t2t3

PSB 4860

Data Sheet 318 2000-01-14

Figure 95 Memory Interface - Samsung Data Read

Parameter

Memory Interface - Samsung Data Read

Symbol Limit values Unit

Min Max

FOE low time t1 200 ns

Data setup time t240 ns

Data hold time t30ns

MD0-MD7

FOE

t2t3

PSB 4860

Data Sheet 319 2000-01-14

Figure 96 Auxiliary Parallel Port - Multiplex Mode

Parameter

Auxiliary Port Interface - Multiplex Mode

Symbol Limit values Unit

Min Typ Max

Active time (MA0-MA15)t1 2ms

Gap time (MA0-MA15)t2125 µs

Data setup time t350 ns

Data hold time t40ns

MA0-MA11

MA12

t3t4

t1t2

MA13

PSB 4860

Data Sheet 320 2000-01-14

Figure 97 Reset Timing

Parameter

Reset Timing

Symbol Limit values Unit

Min Max

VDD/VDDP/VDDA rise time 5%-95% t1 20 ms

Supply voltages stable to RST high t2 0ns

Supply voltages stable to RST low t30.1 ms

RST high time t41000 ns

RST

VDD/VDDP

t2t4

PSB 4860

Data Sheet 321 2000-01-14

5 Package Outlines

Plastic Package, P-MQFP-80 (SMD)

(Plastic Metric Quad Flat Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

PSB 4860
Data Sheet 322 2000-01-14
A
Abort
Clearing Event 104, 153
Functional Description 104
Status Bit 141
Alert Tone Detector
Electrical Characteristics 303
Functional Description 50
Registers 181–182
Status Bit 142
Analog Front End Interface
Electrical Characteristics 310
Functional Description 69
Registers 157–163
Timing 117
ARAM
see Memory Interface
Automatic Gain Control
Functional Description 73
Registers 209–215
Auxiliary Parallel Port
Electrical Characteristics 319
Mode Bits 145
Multiplex Mode 137
Registers 226–231
Static Mode 137
C
Caller ID Decoder
Electrical Characteristics 302
Functional Description 55, 57
Registers 183–184
Status Bits 141–142
CNG Detector
Electrical Characteristics 303
Functional Description 49
Registers 177–180
Status Bit 142
CPT Detector
Electrical Characteristics 302
Functional Description 53
Registers 187–191, 221–222
Status Bit 142
D
Digital Interface
Functional Description 70
Mode Bits 145
Registers 164–186
DRAM
see Memory Interface
DTMF Detector
Electrical Characteristics 302
Functional Description 48
Registers 196–198
Status Bit 142
DTMF Generator
Functional Description 59
Registers 172–176
E
EPROM
see Memory Interface
Equalizer
Functional Description 75
Registers 199–201
Execution Times
File Commands 98
F
File
Commands
Access File Descriptor 92
Compress 90
Create Next New 88
Delete 89–90
Execution Times 98
New File 87
Open 87
Read Binary Data 86, 93
Registers 216–220
Restrictions 99
Seek 89
Status Bits 142
Tailcut 89–90
Write Binary Data 93
Type
Audio 80
Binary 81

PSB 4860
Data Sheet 323 2000-01-14
Phrase 81
User Data Word 82–83
Flash Memory
see Memory Interface
G
Group Listening 41
H
Hardware Configuration
Functional Description 104
Registers 144
I
Interrupt
Functional Description 102
Pin Configuration 144
Register 156
IOM®-2 Interface
Electrical Characteristics 306–307
Functional Description 111
see also: Digital Interface
L
Line Echo Canceller
Functional Description 45
Registers 192–195
Loudhearing 41
M
Memory Interface
ARAM/DRAM
Connection Diagram 127
Electrical Characteristics 311–
313
Refresh 129, 146
Timing 128
EPROM
Connection Diagram 130
Electrical Characteristics 314
Timing 130
Flash
Connection Diagram 131, 135
Electrical Characteristics 315–
318
In-Circuit Programming 125, 146
Multiple Devices 132
Timing 133
Register 154
Supported Devices 125
Memory Management
Activation 85
Directories 79–80
ExecutionTimes 98
Files 80
Garbage Collection 91
Initialization 83–84
Memory Status 91
Overview 79
Status 82
O
Oscillator
Electrical Characteristics 305
Mode Bits 145
P
Power Down
Functional Description 102
Status Bit 144
R
Real Time Clock
Configuration Bits 144
Functional Description 101
Oscillator 305
Registers 224–225
Recompression 90
Reset
Electrical Characteristics 320
Functional Description 102
Register Values 148
Restrictions
File Commands 99
Modules 106
Revision
Functional Description 104
Register 153
S
Serial Control Interface
Command Opcodes 110, 122
Electrical Characteristics 309
Functional Description 119
Signals

PSB 4860
Data Sheet 324 2000-01-14
Encoding 151
Reference Table 151
Speakerphone
Functional Description
Automatic Gain Control 41
Control 40
Echo Cancellation 30
Echo Suppression 32
Overview 29
Speech Comparator 37
Speech Detector 34
Registers 245–278
Speech Coder
Functional Description 60
Registers 202–208
Speech Decoder
Functional Description 66
Register 206
SPS Outputs
Functional Description 41, 101
Register 223
SSDI Interface
Electrical Characteristics 306–308
Functional Description 115
see also: Digital Interface
Status Register
Definition 141
Update Timing 304
U
Universal Attenuator
Functional Description 72
Register 171