1. General description
The PCA9620 is a peripheral device which interfaces to almost any Liq uid Crysta l Display
(LCD)1 with low multiplex rates. It generates the drive signals for any sta tic or multiplexe d
LCD containing up to eight backplanes, 60 segments, and up to 480 elements. The
PCA9620 is compatible with most microprocessor s or microcontrollers and communicates
via a two-line bidirectional I2C-bus. Communication overheads are minimized using a
display RAM with auto-incremented addressing and display memory switching. The
PCA9620 features an internal charge pump with internal cap acitors for on-chip generation
of the LCD driving voltages
2. Features and benefits
AEC Q100 grade 2 compliant for automotive applications
Low power consum ption
Extended operating temperature range from 40 C to +105 C
60 segments and 8 backpla ne s allo win g to dr ive :
up to 60 7-segment alphanumeric characters
up to 30 14-segment alphanumeric characters
any graphics of up to 48 0 elements
480-bit RAM for display data storage
Selectable backplane drive configuration: static, 2, 4, 6, or 8 backplane multiplexing
Programmable internal charge pump for on-chip LCD voltage generation up to
3VDD2
400 kHz I2C-bus inter face
Selectable linear temperature compensation of VLCD
Selectable display bias configuration
Wide range for digital and analog power supply: from 2.5 V to 5.5 V
Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high
threshold (automobile) twisted nematic LCDs
Display memory bank switching in static, d uplex, and quadruplex drive modes
Programmable frame frequency in steps of 10 Hz in the range of 60 Hz to 300 Hz;
factory calibrated with a tolerance of 15 % covering the whole temperature and
voltage range
Selectable inversion scheme for LCD driving waveforms: frame or line inversion
Integrated temperature sensor with temperature readout
On chip calibration of internal oscillator frequency and VLCD
PCA9620
60 x 8 LCD high-drive segment driver for automotive and
industrial
Rev. 3 — 3 July 2013 Product data sheet
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20 on page 73.
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Product data sheet Rev. 3 — 3 July 2013 2 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
3. Applications
Automotive
Instrument cluster
Car radio
Climate control units
Industrial
Machine control systems
Measuring equipment
Signage
Information boards
Panels
4. Ordering information
4.1 Ordering options
5. Marking
Table 1. Ordering information
Type number Package
Name Description Version
PCA9620H LQFP80 plastic low profile quad flat package; 80 leads;
body 12 12 1.4 mm SOT315-1
PCA9620U bare die 80 bonding pads PCA9620U
Table 2. Ordering options
Product type number Sales item (12NC) Orderable part
number IC
revision Delivery form
PCA9620H/Q900/1 935291899518 PCA9620H/Q900/1,51 1 tape and reel, 13 inch, dry pack
PCA9620U/5GA/Q1 935295801015 PCA9620U/5GA/Q1,01 1 wafer, unsawn
Table 3. Marking codes
Type number Marking code
PCA9620H PCA9620H/Q900
PCA9620U PC9620-1
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Product data sheet Rev. 3 — 3 July 2013 3 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
6. Block diagram
(1) The charge pump can generate a maximum output voltage of 3 VDD2.
Fig 1. Block diagram of PCA9620
013aaa246
LCD
VOLTAGE
SELECTOR
CLOCK SELECT
AND TIMING
OSCILLATOR POWER-ON
RESET
CLK
SCL
SDA
A0
BACKPLANE
OUTPUTS
DISPLAY
CONTROL
BP0 to BP7
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
60
S0 to S59
PCA9620
LCD BIAS
GENERATOR
VSS
VLCD
COMMAND
DECODER WRITE DATA
CONTROL
A1 VDD1
VDD2
CHARGE
PUMP(1)
(VOLTAGE
MULTIPLIER)
T1 T2
TEMPERATURE
SENSOR
T3
I2C-BUS
CONTROLLER
DATA POINTER,
AUTO INCREMENT
DISPLAY RAM
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Product data sheet Rev. 3 — 3 July 2013 4 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
7. Pinning information
7.1 Pinning
Top view. For mechanical details, see Figure 58 on page 63.
Fig 2. Pin configuration for LQFP80 (PCA9620H )
PCA9620H
S20 SDA
S21 SCL
S22 A1
S23 A0
S24 CLK
S25 T3
S26 T2
S27 T1
S28 VSS
S29 VDD1
S30 VDD2
S31 VLCD
S32 BP7
S33 BP6
S34 BP5
S35 BP4
S36 BP3
S37 BP2
S38 BP1
S39 BP0
S40 S19
S41 S18
S42 S17
S43 S16
S44 S15
S45 S14
S46 S13
S47 S12
S48 S11
S49 S10
S50 S9
S51 S8
S52 S7
S53 S6
S54 S5
S55 S4
S56 S3
S57 S2
S58 S1
S59 S0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
013aaa244
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Product data sheet Rev. 3 — 3 July 2013 5 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
Viewed from active side. For mechanical details, see Figure 59 on page 64.
Fig 3. Pin configuration for PCA9620U (bare die)
PCA9620U
S20 SDA
S21 SCL
S22 A1
S23 A0
S24 CLK
S25 T3
S26 T2
S27 T1
S28 VSS
S29 VDD1
S30 VDD2
S31 VLCD
S32 BP7
S33 BP6
S34 BP5
S35 BP4
S36 BP3
S37 BP2
S38 BP1
S39 BP0
S40 S19
S41 S18
S42 S17
S43 S16
S44 S15
S45 S14
S46 S13
S47 S12
S48 S11
S49 S10
S50 S9
S51 S8
S52 S7
S53 S6
S54 S5
S55 S4
S56 S3
S57 S2
S58 S1
S59 S0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
013aaa510
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Product data sheet Rev. 3 — 3 July 2013 6 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
7.2 Pin description
[1] When the internal VLCD generation is used, this pin drives the VLCD voltage. In this case pin VLCD
is an output. When the external supply is requested, then pin VLCD is an input an d VLCD can be
supplied to it. In this case, the internal charge pump must be disable d (see Table 9 on page 9).
Table 4. Pin description
Symbol Pin Type Description
S0 to S59 61 to 80 and
1 to 40 output LCD segment
BP0 to BP7 41 to 48 output LCD backplane
VLCD 49 supply/output[1] LCD supply voltage
VDD2 50 supply supply voltage 2 (charge pu mp)
VDD1 51 supply supply voltage 1 (anal og and digital)
VSS 52 supply ground supply voltage
T1 to T3 53 to 55 input test pins; must be tied to VSS in applications
CLK 56 input/output internal oscillator output, external oscillator input
A0, A1 57, 58 input I2C-bus slave address selection bit
SCL 59 input I2C-bus serial clock
SDA 60 input/output I2C-bus serial data
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Product data sheet Rev. 3 — 3 July 2013 7 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
8. Functional description
The PCA9620 is a versatile peri pheral device designed to inte rface any microprocessor or
microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed
LCD containing up to 480 elements.
8.1 Commands of PCA9620
The PCA9620 is controlled by 22 commands, which are defined in Table 5. Any other
combinations of operation code bits that are not mentioned in this document may lead to
undesired operation modes of PCA9620.
8.1.1 Command: initialize
This command generates a chip-wide reset which r esets all command values to their
default values (see Table 26 on page 17). It must be sent to the PCA9620 af ter power- on.
After this command is sent, it is possible to send additional commands without the need to
re-initialize the interface. Reset takes 100 ns to complete.
For further information, see Section 8.3 on page 16.
Table 5. Commands of PCA9620
Command name Bits Reference
76543210
initialize 00111010Section 8.1.1
OTP-refresh 11010000Section 8.1.2
oscillator-ctrl 110011COEOSCSection 8.1.3
charge-pump-ctrl110000CPE
CPC Section 8.1.4
temp-msr-ctrl 110010TCE
TME Section 8.1.5
temp-comp-SLA00011SLA[2:0] Table 30
temp-comp-SLB00100SLB[2:0]
temp-comp-SLC00101SLC[2:0]
temp-comp-SLD00110SLD[2:0]
set-VPR-MSB 0100VPR[7:4] Section 8.1.6
set-VPR-LSB 0101VPR[3:0]
display-enable 0011100ESection 8.1.7
set-MUX-mode00000M[2:0] Section 8.1.8
set-bias-mode 110001B[1:0] Section 8.1.9
load-data-pointer 1 0 P[5:0] Section 8.1.10
frame-frequency011F[4:0] Section 8.1.11
input-bank-select00001IB[2:0] Section 8.1.12.1
output-bank-select 00010OB[2:0]
write-RAM-data B[7:0] Section 8.1.13
temp-read TD[7:0] Section 8.1.14,
Section 8.4.7
invmode_CPF_ctrl110101LF
CPF Section 8.1.15
temp-filter 1101001TFESection 8.1.16
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.2 Command: OTP-refresh
In order to achieve the specified accuracy of VLCD, the frame frequen cy, and the
temperature measurement, each IC is calibrated during production and testing of the
device. This calibration is performed on EPROM cells ca lled One Time Programmable
(OTP) cells. These cells are read by the device at power-on, after a reset, and every time
when the initialize command or the OTP-refresh command is sent. This command will
take approximately 10 ms to finish.
8.1.3 Command: oscillator-ctrl
The oscillator-ctrl command switches between internal and external oscillator and enables
or disables pin CLK.
[1] Default value.
Table 6. Initialize - initialize command bit description
Bit Symbol Value Description
7 to 0 - 0011 1010 fixed value
Table 7. OT P-refresh - OTP-refresh command bit description
Bit Symbol Value Description
7 to 0 - 11010000 fixed value
Table 8. Os cillator-ctrl - oscillator control command bit descrip tion
For further information, see Section 8.5 on page 40.
Bit Symbol Value Description
7 to 2 - 110011 fixed value
1 COE control pin CLK
0[1] clock signal not available on pin CLK;
pin CLK is in 3-state and may be left floating
1 clock signal available on pin CLK
0 OSC oscillator source
0[1] internal oscillator running
1 external oscillator used;
pin CLK becomes an input
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.4 Command: charge-pump-ctrl
The charge-pump-ctrl command enables or disables the internal VLCD generation and
controls the charge pump voltage multiplier setting.
[1] Default value.
8.1.5 Command: temp-msr-ctrl
The temp-msr-ctrl command enables or disa bles the temperature measurement block a nd
the temperature compensation of VLCD.
[1] Default value.
8.1.6 Command: set-VPR-MSB and set-VPR-LSB
With these two instructions, it is possible to set the target VLCD voltage for the internal
charge pump, see Section 8.4.3 on page 33.
[1] Default value.
Table 9. Charge-pump-ctrl - charge pump control command bit d escription
Bit Symbol Value Description
7 to 2 - 110000 fixed value
1 CPE charge pump switch
0[1] charge pump disabled;
no internal VLCD generation;
external supply of VLCD
1 charge pump enabled
0 CPC charge pump voltage multiplier setting
0[1] VLCD = 2 VDD2
1V
LCD = 3 VDD2
Table 10. Temp-msr-ctrl - temperature measurem ent control command bit descrip tion
For further information, see Section 8.4.8 on page 38.
Bit Symbol Value Description
7 to 2 - 110010 fixed value
1 TCE temperature compensation switch
0 no temperature compensation of VLCD
possible
1[1] temperature compensation of VLCD possible
0 TME temperature measurement switch
0 temperature me asurement disabled;
no temperature readout possible
1[1] temperature measuremen t enabled;
temperature readout possible
Table 11. Set-VPR-MSB - set VPR MSB command bit description
Bit Symbol Value Description
7 to 4 - 0100 fixed value
3 to 0 VPR[7:4] 0000[1] to 1111 the four most significant bits of VPR[7:0]
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60 x 8 LCD high-drive segment driver for automotive and industrial
[1] Default value.
8.1.7 Command: display-enable
[1] Default value.
8.1.8 Command: set-MUX-mode
[1] Default value.
8.1.9 Command: set-bias-mode
[1] Default value.
8.1.10 Command: load-data-pointer
The load-data-pointer command defines one of the 60 display RAM addresses where the
following display data will be sent to. For further information, see Section 8.9.1 on
page 43.
Table 12. Set-VPR-LSB - set VPR LSB command bit description
Bit Symbol Value Description
7 to 4 - 0101 fixed value
3 to 0 VPR[3:0] 0000[1] to 1111 the four least significant bits of VPR[7:0]
Table 13. Display-enable - display enable command bit description
Bit Symbol Value Description
7 to 1 - 0011 100 fixed value
0E 0
[1] display disabled;
backplane and se gment outputs are inte rn a ll y
connected to VSS
1 display enabled
Table 14. Set-MUX-mode - set multiplex drive mode command bit description
Bit Symbol Value Description
7 to 3 - 00000 fixed value
2 to 0 M[2:0] 000[1], 011,
110, 111 1:8 multiplex drive mode: 8 backplane s
001 static drive mode: 1 backplane
010 1:2 multiplex drive mode: 2 backplane s
100 1:4 multiplex drive mode: 4 backplane s
101 1:6 multiplex drive mode: 6 backplane s
Table 15. Set-bias-mode - set bias mode command bit description
Bit Symbol Value Description
7 to 2 - 110001 fixed value
1 to 0 B[1:0] 00[1], 01 14 bias
11 13 bias
10 12 bias
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.11 Command: frame-frequency
With the frame-frequency command, the frame frequency and the output clock frequency
can be configured .
[1] Nominal frame frequency calculated for the default clock frequency of 9600 Hz.
[2] Duty cycle definition: % HIGH-level time : % LOW-level time.
[3] Default value.
Table 16. Load-data-pointer - load data pointer command bit description
Bit Symbol Value Description
7 to 6 - 10 fixed value
5 to 0 P[5:0] 000000 to
111111 6-bit binary value of 0 to 59
Table 17. Frame frequency - frame frequency and output clock frequency co mmand bit
description
Bit Symbol Value Description
7 to 5 - 011 f ixed value
4 to 0 F[4:0] see Table 18 nominal frame frequency (Hz)
Table 18. Frame frequency value s
F[4:0] Nominal frame
frequency, ffr (Hz)[1] Resultant oscillator
frequency, fosc (Hz) Duty cycle (%)[2]
00000 60 2880 20 : 80
00001 70 3360 7 : 93
00010 80 3840 47 : 53
00011 91 4368 40 : 60
00100 100 4800 33 : 67
00101 109 5232 27 : 73
00110 120 5760 20 : 80
00111 129.7 6226 13 : 87
01000 141.2 6778 5 : 95
01001 150 7200 50 : 50
01010 160 7680 47 : 53
01011 171.4 8227 43 : 57
01100 177.8 8534 41 : 59
01101 192 9216 36 : 64
01110[3] 200 9600 33 : 67
01111 208.7 10018 30 : 70
10000 218.2 10474 27 : 73
10001 228.6 10973 23 : 77
10010 240 11520 20 : 80
10011 252.6 12125 16 : 84
10100, 10101 266.7 12802 10 : 90
10110, 10111 282.4 13555 5 : 95
11000 to 11111 300 14400 50 : 50
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.1.12 Bank select commands
For multiplex drive modes 1:4, 1:2 and st atic d rive mode, it is possible to write data to one
area of the RAM while displaying from another. These areas are named as RAM banks.
Input and output banks can be set independently from one another with the
input-bank-select and the output-bank-select command. For further information, see
Section 8.9.2 on p age 48.
8.1.12.1 Command: input-bank-select
[1] Not applicable for multiplex drive mode 1:6 and 1:8.
[2] Default value.
8.1.12.2 Command: output-bank-select
[1] Not applicable for multiplex drive mode 1:6 and 1:8.
[2] Default value.
Table 19. Input-bank-select - input bank select command bit description[1]
Bit Symbol Value Description
7 to 3 - 00001 fixed value
2 to 0 IB[2:0] selects RAM bank to write to
static drive mode 1:2 drive mode 1:4 drive mode
000[2] bank 0: RAM-row 0 bank 0: RAM-rows 0
and 1 bank 0: RAM-rows 0,
1, 2, and 3
001 bank 1: RAM-row 1
010 bank 2: RAM-row 2 bank 2: RAM-rows 2
and 3
011 bank 3: RAM-row 3
100 bank 4: RAM-row 4 bank 4: RAM-rows 4
and 5 bank 4: RAM-rows 4,
5, 6, and 7
101 bank 5: RAM-row 5
110 bank 6: RAM-row 6 bank 6: RAM-rows 6
and 7
111 bank 7: RAM-row 7
Table 20. Output-bank-select - outpu t bank select command bit descr iption[1]
Bit Symbol Value Description
7 to 3 - 00010 fixed value
2 to 0 OB[2:0] selects RAM bank to read from to the LCD
static drive mode 1:2 drive mode 1:4 drive mode
000[2] bank 0: RAM-row 0 bank 0: RAM-rows 0
and 1 bank 0: RAM-rows 0,
1, 2, and 3
001 bank 1: RAM-row 1
010 bank 2: RAM-row 2 bank 2: RAM-rows 2
and 3
011 bank 3: RAM-row 3
100 bank 4: RAM-row 4 bank 4: RAM-rows 4
and 5 bank 4: RAM-rows 4,
5, 6, and 7
101 bank 5: RAM-row 5
110 bank 6: RAM-row 6 bank 6: RAM-rows 6
and 7
111 bank 7: RAM-row 7
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8.1.13 Command: write-RAM-data
The write-RAM-data command writes data byte-wise to the RAM. After Power-On Reset
(POR) the RAM content is ra ndom and should be br ought to a defined status by clearin g it
(setting it logic 0).
[1] For this command bit RS of the control byte has to be set logic 1 (see Table 34 on page 54).
More information about the display RAM can be found in Section 8.9 on page 42.
8.1.14 Command: temp-read
The temp-read command allows reading out the temperature values measured by the
internal temperature sensor.
[1] For this command bit R/W of the I2C-bus slave address byte has to be set logic 1 (see Table 33 on
page 53).
8.1.15 Command: invmode_CPF_ctrl
The invmode_CPF_ctrl command allows changing the drive scheme inversion mode and
the charge pump frequency.
The waveforms used to drive LCD displays inherently produce a DC voltage across the
display cell. The PCA9620 compensates for the DC voltage by inverting the waveforms on
alternate frames or alternate lines. The choice of compensation method is determined
with the LF bit.
[1] Default value.
Table 21. Write-RAM-data - write RAM data command bit description[1]
Bit Symbol Value Description
7 to 0 B[7:0] 00000000 to
11111111 writing data byte-wise to RAM
Table 22. Temp-re ad - temperature readout command bit description[1]
For further information, see Table 10 on page 9 and Section 8.4.7 on page 37.
Bit Symbol Value Description
7 to 0 TD[7:0 ] 00000000 to
11111111 readout representing the digital temperature
Table 23. Invmode_CPF_ctrl - inversion mode and charge pump frequency prescaler
command bit description
Bit Symbol Value Description
7 to 2 - 110101 fixed value
1 LF set inversion mode
0[1] line inversion mode
1 frame inversion mode
0 CPF set charge pump oscillator frequency
0[1] fosc(cp) ~1MHz
1f
osc(cp) ~ 500 kHz
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60 x 8 LCD high-drive segment driver for automotive and industrial
In frame inversion mode, the DC value is compensated across two frames and not within
one frame. Changing the inversion mode to frame inversion reduces the power
consumption, therefore it is useful when power consumption is a key point in the
application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined, however since the switching frequency is reduced there is
possibility for flicker to occur.
The waveforms of Figure 16 on page 25 to Figure 22 on page 31 are showing line
inversion mode. Figure 23 on page 32 shows one example of frame inversion.
8.1.16 Command: temp-filter
[1] Default value.
8.2 Possible display configurations
The PCA9620 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It
can directly drive any static or multiplexed LCD containing up to eight backplanes and up
to 60 segments.
The display configurations possible with the PCA9620 depend on the number of active
backplane outputs required. A selection of possible display configurations is given in
Table 25.
Table 24. Temp-filte r - digital temperature filter command bit de scription
Bit Symbol Value Description
7 to 1 - 1101001 fixed value
0 TFE digital temperature filter switch
0[1] digital temperature filter disabled;
the unfiltered digital value of TD[7:0 ] is
immediately available for the readout and
VLCD compensation, see Section 8.4.7 on
page 37
1 digital temperature filter enabled
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Product data sheet Rev. 3 — 3 July 2013 15 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
All of the display configurations in Table 25 can be implemented in the typical systems
shown in Figure 5 (internal VLCD) and in Figure 6 (external VLCD).
Fig 4. Example of displays suit able for PCA9620
Table 25. Selection of possible display configurations
Number of
Backplanes Icons Digits/Characters Dot matrix/
Elements
7-segment 14-segment
8 480 60 30 480 dots (8 60)
6 320 45 22 360 dots (6 60)
4 240 30 15 240 dots (4 60)
2 120 15 7 120 dots (2 60)
1607360dots (160)
VDD1 from 2.5 V to 5.5 V and VDD2 from 2.5 V to 5.5 V.
Fig 5. Typical system configuration when using the internal VLCD generation
7-segment with dot 14-segment with dot and accent
013aaa312
dot matrix
HOST
PROCESSOR/
MICRO-
CONTROLLER
R tr
2Cb
SDA
SCL
60 segment drives
8 backplanes
LCD PANEL
(up to 480
elements)
PCA9620
A0 A1
VDD1
VSS
VSS
013aaa247
VDD2
VLCD
VDD2
VDD1
CLK
n.c.
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60 x 8 LCD high-drive segment driver for automotive and industrial
The host microcontroller maintains the two line I2C-bus communication channel with the
PCA9620. The appropriate biasing voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required to complete the system are the
power supplies (VDD1, VDD2, VSS, VLCD), the external capacitors, and the LCD panel
selected for the application.
The minimum recommended values for external capacitors on VDD1, VDD2, and VLCD are
nominal 100 nF. When using bigger capacitors, especially on the VLCD, the generated
ripple will be consequently smaller. However it will take longer for the internal charge
pump to reach the target VLCD voltage first.
If VDD1 and VDD2 are connected externally, the capacitors on VDD1 and VDD2 can be
replaced by a single capacitor with a minimum value of 200 nF.
Remark: In the case of insufficient decoupling, ripple of VDD1 and VDD2 will create
additional VLCD ripple. The ripple on VLCD can be reduced by making the VSS connection
as low-ohmic as possible. Excessive ripple on VLCD may cause flicker on the display.
8.3 Start-up and shut-down
8.3.1 Power-On Reset (POR)
At power-on, the PCA9620 resets to starting conditions as follows:
1. All backplane outputs are set to VSS.
2. All segment outputs are set to VSS.
3. Selected drive mode is: 1:8 with 14 bias.
4. Input and output bank selectors are reset.
5. The I2C-bus interface is initialized.
6. The data pointer is cleared (set logic 0).
7. The Internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in
3-state.
8. Temperature measurement is enabled.
VDD1 from 2.5 V to 5.5 V, VDD2 from 2.5 V to 5.5 V and VLCD from 2.5 V to 9.0 V.
Fig 6. Typical system configuration when using an external VLCD
HOST
PROCESSOR/
MICRO-
CONTROLLER
R tr
2Cb
SDA
SCL
60 segment drives
8 backplanes
LCD PANEL
(up to 480
elements)
PCA9620
A0 A1
VDD1
VSS
VSS
013aaa248
VLCD
VLCD
VDD2
VDD1
CLK
n.c.
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Product data sheet Rev. 3 — 3 July 2013 17 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
9. Temperature filter is disabled.
10. The internal VLCD voltage gene ration is disabled. The charge pump is switched off.
11. The VLCD temperature compensation is enabled.
12. The display is disabled.
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
The first command sent to the device after the power-on event must be the initialize
command (see Section 8.1.1 on page 7).
After Power-On Reset (POR) and before enabling the display, the RAM content should be
brought to a defined status
by clearing it (setting it all logic 0) or
by writing meaningful content (for ex am p le, a gr ap h ic)
otherwise unwanted display artifacts may appear on the display.
Table 26. Reset states
Bits labeled - are undefined at power-on.
Command name Bits
7 6 5 4 3 2 1 0
initialize 0 0 1 1 1 0 1 0
OTP-refresh 11010000
oscillator-ctrl 11001100
charge-pump-ctrl 11000000
temp-msr-ctrl 1 1 0 0 1 0 1 1
temp-comp-SLA 00011000
temp-comp-SLB 00100000
temp-comp-SLC 00101000
temp-comp-SLD 00110000
set-VPR-MSB 01000000
set-VPR-LSB 01010000
display-enable 0 0 1 1 1 0 0 0
set-MUX-mode 00000000
set-bias-mode 11000100
load-data-pointer 1 0 0 0 0 0 0 0
frame-frequency 0 1 1 0 1 1 1 0
input-bank-select 00001000
output-bank-select 0 0 0 1 0 0 0 0
write-RAM-data --------
temp-read 01000000
invmode_CPF_ctrl11010100
temp-filter 11010010
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Product data sheet Rev. 3 — 3 July 2013 18 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.3.2 Recommended start-up sequences
This chapter describes how to proceed with the initia liza tio n of the ch ip in different
application modes.
(1) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms
to 15 ms is expected.
When using the internal VLCD generation, the display must not be enabled before the generation of
VLCD with the internal charge pump is completed. Otherwise unwanted display artifacts may
appear on the display.
(2) RAM data may be written before or during the ramp-up of VLCD.
Fig 7. Recommended start-up sequence when using th e internal charge pump and the
internal clock signal
Wait 1 ms
START
Power-on
V
DD1
and
V
DD2
at the
same time
013aaa249
Set VPR
register to
desired V
LCD
value
Set
multiplication
factor for
charge pump
and enable it
Wait till
V
LCD
reaches
programmed
value
(1)
Write RAM
content to be
displayed and
enable the
display
(2)
STOP
Initiate an
OTP-refresh
Initialize
command
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Product data sheet Rev. 3 — 3 July 2013 19 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
Fig 8. Recommended st art-up sequence when using an external supplied VLCD and the
internal clock signal
(1) The external clock signal can be applied after the generation of the VLCD voltage as well.
(2) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms
to 15 ms is expected.
(3) RAM data may be written before or during the ramp-up of VLCD.
Fig 9. Recommended start-up sequence when using th e internal charge pump and an
external clock signal
Wait 1 ms
START
Power-on
V
DD1
, V
DD2
,
and V
LCD
at the
same time
Initialize
command
013aaa250
Write RAM
content to be
displayed and
enable the
display
STOP
Initiate an
OTP-refresh
Wait 1 ms
START
Power-on
V
DD1
and
V
DD2
at the
same time
Initialize
command
013aaa251
Set VPR
register to
desired V
LCD
value
Wait till
V
LCD
reaches
programmed
value
(2)
Write RAM
content to be
displayed and
enable the
display
(3)
STOP
Apply external
clock signal
to pin CLK;
set OSC bit
logic 1
(1)
(1)
Initiate an
OTP-refresh
Set
multiplication
factor for
charge pump
and enable it
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Product data sheet Rev. 3 — 3 July 2013 20 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.3.3 Recommended power-down sequences
With the following sequences, the PCA9620 can be set to a state of minimum power
consumption, called power-down mode.
Fig 10. Recommended st art-up sequence when using an external supplied VLCD and an
external clock signal
Wait 1 ms
START
Initialize
command
013aaa252
Write RAM
content to be
displayed and
enable the
display
STOP
Apply external
clock signal
to pin CLK;
set OSC bit
logic 1
Power-on
VDD1, VDD2,
and VLCD
at the
same time
Initiate an
OTP-refresh
Fig 11. Recommended power-down sequence for minimum power-down current when
using the internal charge pump and the internal clock sign al
Stop genera-
tion of V
LCD
by setting bit
CPE logic 0
START
Disable dis-
play by setting
bit E logic 0
Disable tem-
perature mea-
surement by
setting bit
TME logic 0
013aaa253
STOP
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Product data sheet Rev. 3 — 3 July 2013 21 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
Fig 12. Recommended power-down sequence when using an external supplied VLCD and
the internal clock signal
Fig 13. Recommended power-down sequence when using the internal charge pump and
an external clock signal
START
Disable dis-
play by setting
bit E logic 0
Disable tem-
perature mea-
surement by
setting bit
TME logic 0
013aaa254
STOP
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Product data sheet Rev. 3 — 3 July 2013 22 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
Remark: It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, car e must be taken that no other signals are pr esent a t the
chip input or output pins when removing the supplies (refer to Section 10 on page 55).
Otherwise it may cause unwanted display artifacts. The PCA9620 will not be damaged by
uncontrolled removal of supply voltages
Remark: Static voltages across the liquid crystal di splay can build up when the external
LCD supply voltage (VLCD) is on while the IC supply voltage (VDD1 or VDD2) is off, or vice
versa. It may cause unwanted display artifacts. To avoid such artifacts, external VLCD,
VDD1, and VDD2 must be applied or removed together.
Remark: A clock signal must always be supplied to the device when the device is active;
removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid
crystal. It is recommended to first disable the display and afterwards to remove the clock
signal.
8.4 LCD voltage
8.4.1 LCD voltage selector
The LCD voltag e selector co-o rdinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
set-bias-mode command (see Table 15 on page 10) and the set-MUX-mode command
(see Table 14 on page 10).
Intermediate LCD biasing voltages are obtained from an internal voltage divider. The
biasing configurations that apply to the preferred modes of operation, together with the
biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are
given in Table 27.
Discrimination is a term which is defined as the ratio of the Von(RMS) and Voff(RMS) across a
segment. It can be thought of as a measurement of contrast.
Fig 14. Recommended power-down sequence when using an external supplied VLCD and
an external clock signal
START
Disable dis-
play by setting
bit E logic 0
Disable tem-
perature mea-
surement by
setting bit
TME logic 0
013aaa256
STOP
Bring pin CLK
to 3-state by
setting bit
OSC and bit
COE logic 0
External
clock may
be switched
off
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60 x 8 LCD high-drive segment driver for automotive and industrial
[1] Determined from Equation 3.
[2] Determined from Equation 2.
[3] In these examples the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a
power saving from a reduction of the LCD voltage VLCD.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold volt age (Vth(off)) , typically when the LCD exhibit s approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3V
th(off).
Bias is calculated by , where the values for a are
a = 1 for 12 bias
a = 2 for 13 bias
a = 3 for 14 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
(1)
where VLCD is the resultant volt age at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 4 for 1:4 multiplex
n = 6 for 1:6 multiplex
n = 8 for 1:8 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
Table 27. LCD drive mod es: summary of characteristics
LCD drive
mode Number of: LCD bias
configuration [1] VLCD[2]
Backplanes Levels
static 1 2 static 0 1 Von(RMS)
1:2 multip l e x 2 3 120.354 0.791 2.236 2.828 Voff(RMS)
1:2 multip l e x 2 4 130.333 0.745 2.236 3.0 Voff(RMS)
1:2 multip l e x [3] 25
140.395 0.729 1.845 2.529 Voff(RMS)
1:4 multip l e x [3] 43
120.433 0.661 1.527 2.309 Voff(RMS)
1:4 multip l e x 4 4 130.333 0.577 1.732 3.0 Voff(RMS)
1:4 multip l e x [3] 45
140.331 0.545 1.646 3.024 Voff(RMS)
1:6 multip l e x [3] 63
120.456 0.612 1.341 2.191 Voff(RMS)
1:6 multip l e x 6 4 130.333 0.509 1.527 3.0 Voff(RMS)
1:6 multip l e x 6 5 140.306 0.467 1.527 3.266 Voff(RMS)
1:8 multip l e x [3] 83
120.467 0.586 1.254 2.138 Voff(RMS)
1:8 multip l e x [3] 84
130.333 0.471 1.414 3.0 Voff(RMS)
1:8 multip l e x 8 5 140.293 0.424 1.447 3.411 Voff(RMS)
Voff RMS
VLCD
-----------------------
Von RMS
VLCD
----------------------
DVon RMS
Voff RMS
-----------------------
=
1
1a+
-------------
Von RMS a22a n++
n1a+
2
------------------------------
VLCD
=
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Product data sheet Rev. 3 — 3 July 2013 24 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is dete rm in ed from Equation 3:
(3)
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
8.4.1.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) an d th e oth e r at 90 % relative transm iss i on (at Vth(on)), see
Figure 15. For a good contrast performance, the following rules should be fol lowed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are af fected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
Voff RMS a22an+
n1a+
2
------------------------------
VLCD
=
Von RMS
Voff RMS
---------------------- a1+
2n1+
a1
2n1+
--------------------------------------------=
Fig 15. Electro-optical characteristic: relative transmission curve of the liquid
Von RMS
Vth on
Voff RMS
Vth off
VRMS [V]
100 %
90 %
10 %
OFF
SEGMENT GREY
SEGMENT ON
SEGMENT
Vth(off) Vth(on)
Relative T ransmission
013aaa494
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Product data sheet Rev. 3 — 3 July 2013 25 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2 LCD drive mode waveforms
8.4.2.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Von(RMS)(t) = VLCD. Voff(RMS)(t) = 0 V.
Fig 16. Static drive mode waveforms (line inversion mode)
013aaa207
V
SS
V
LCD
V
SS
V
LCD
V
SS
V
LCD
V
LCD
V
LCD
V
LCD
V
LCD
state 1 0 V
BP0
Sn
Sn+1
state 2 0 V
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 1
(on) state 2
(off)
T
fr
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Product data sheet Rev. 3 — 3 July 2013 26 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.2 1:2 Multiplex drive mode
When two backpla ne s ar e pr ov ide d in the LCD , the 1:2 multiple x mo d e ap plie s. The
PCA9620 allows the use of 12 bias or 13 bias in this mode as shown in Figure 17 and
Figure 18.
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.791VLCD. Voff(RMS)(t) = 0.354VLCD.
Fig 17. Waveforms for the 1:2 multiplex drive mode with 12 bias (line inversion mode)
013aaa208
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 2
state 1
VSS
VLCD
VLCD/2
VSS
VSS
VLCD
VLCD
VSS
VLCD
VLCD
VLCD
0 V
0 V
VLCD/2
VLCD/2
VLCD/2
VLCD
VLCD
VLCD/2
VLCD/2
Sn
Sn+1
Tfr
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Product data sheet Rev. 3 — 3 July 2013 27 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.745VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 18. Waveforms for the 1:2 multiplex drive mode with 13 bias (line inversion mode)
013aaa209
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
2VLCD/3
VLCD/3
VLCD/3
VLCD
VLCD
0 V
VLCD
2VLCD/3
2VLCD/3
VLCD/3
VLCD/3
Sn
Sn+1
Tfr
VSS
VLCD
2VLCD/3
VLCD/3
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.3 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 19.
Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 19. Waveforms for the 1:4 multiplex drive mode with 13 bias (line inversion mode)
013aaa211
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn+1
Sn+2
Sn+3
Tfr
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
-2VLCD/3
VLCD/3
-VLCD/3
-VLCD
0 V
VLCD
2VLCD/3
-2VLCD/3
VLCD/3
-VLCD/3
-VLCD
VSS
VLCD
2VLCD/3
VLCD/3
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Product data sheet Rev. 3 — 3 July 2013 29 of 81
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.4.2.4 1:6 Multiplex drive mode
When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The
PCA9620 allows the use of 13 bias or 14 bias in this mode as shown in Figure 20 and
Figure 21.
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t).
Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 20. Waveforms for 1:6 multiplex drive mode with 13 bias (line inversion mode)
001aal399
state 1 state 2
LCD segments
Tfr
VLCD
BP0 2VLCD / 3
VLCD / 3
VSS
VLCD
BP1 2VLCD / 3
VLCD / 3
VSS
VLCD
BP2 2VLCD / 3
VLCD / 3
VSS
VLCD
BP3 2VLCD / 3
VLCD / 3
VSS
VLCD
BP4 2VLCD / 3
VLCD / 3
VSS
VLCD
BP5 2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
(a) Waveforms at driver
(b) Resultant waveforms at LCD segment
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn + 1 2VLCD / 3
VLCD / 3
VSS
VLCD
state 1 2VLCD / 3
VLCD / 3
VSS
VLCD
state 2
-VLCD
2VLCD / 3
-2VLCD / 3
VLCD / 3
-VLCD / 3
-VLCD
-2VLCD / 3
-VLCD / 3
VSS
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60 x 8 LCD high-drive segment driver for automotive and industrial
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t).
Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD.
Fig 21. Waveforms for 1:6 multiplex drive mode with 14 bias (line inversion mode)
001aal400
state 1 state 2
LCD segments
VLCD
3VLCD / 4
VLCD / 4
VSS
BP0
VLCD
3VLCD / 4
VLCD / 4
VSS
BP1
VLCD
3VLCD / 4
VLCD / 4
VSS
BP2
VLCD
3VLCD / 4
VLCD / 4
VSS
BP3
VLCD
3VLCD / 4
VLCD / 4
VSS
BP4
VLCD
3VLCD / 4
VLCD / 4
VSS
BP5
VLCD
-VLCD
3VLCD / 4
-3VLCD / 4
VLCD / 4
-VLCD / 4
VLCD / 2
-VLCD / 2
VSS
VLCD
VLCD / 2
VSS
VLCD
VLCD / 2
VSS
state 2
VLCD
-VLCD
3VLCD / 4
-3VLCD / 4
VLCD / 4
-VLCD / 4
VSS
state 1
Sn + 1
Sn
Tfr
(a) Waveforms at driver
(b) Resultant waveforms at LCD segment
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8.4.2.5 1:8 Multiplex drive mode
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
Fig 22. Waveforms for 1:8 multiplex drive mode with 14 bias (line inversion mode)
001aal398
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
Sn
Sn + 1
state 1
state 2
VLCD
3VLCD / 4
state 1 state 2
LCD segments
-VLCD
VLCD / 2
VLCD / 4
VSS
-VLCD / 4
-VLCD / 2
-3VLCD / 4
-VLCD
-3VLCD / 4
-VLCD / 4
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 2
VLCD
VSS
VLCD / 2
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
3LCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD
VSS
VLCD / 4
3VLCD / 4
VLCD Tfr
(a) Waveforms at driver
(b) Resultant waveforms at LCD segment
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60 x 8 LCD high-drive segment driver for automotive and industrial
Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
Fig 23. Waveforms for 1:8 multiplex drive mode with 14 bias (frame inversion mode)
001aam359
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
Sn
Sn + 1
state 1
state 2
state 1
Tfr Tfr
frame n frame n+1
state 2
LCD segments
VLCD
3/4 VLCD
1/4 VLCD
VSS
1/4 VLCD
3/4 VLCD
1/2 VLCD
1/2 VLCD
VLCD
VLCD
3/4 VLCD
1/4 VLCD
VSS
1/4 VLCD
3/4 VLCD
1/2 VLCD
1/2 VLCD
VLCD
VSS
1/2 VLCD
VLCD
VSS
1/2 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
VSS
1/4 VLCD
3/4 VLCD
VLCD
(a) Waveforms at driver
(b) Resultant waveforms at LCD segment
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Product data sheet Rev. 3 — 3 July 2013 33 of 81
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When eight backplanes are provided in the LCD, the 1:8 multiplex dri ve mode applies, as
shown in Figure 22 and Figure 23.
8.4.3 VLCD generation
VLCD can be generated and controlled on the chip by using software commands. When
the internal charge pump is used, the programmed VLCD is available on pin VLCD. The
charge pump generates a VLCD of up to 3 VDD2.
The charge pump can be enabled or disabled with the CPE bit (see Table 9 on page 9).
With bit CPC, the charge pump multiplier setting can be configured.
The final value of VLCD is a combination of the programmed VPR[7:0] value and the output
of the temperature compensation block, VT[7:0]. The system is shown in Figure 24.
In Equation 6 the main parameters are the programmed digital value term and the
compensated temperature term.
(6)
1. VPR[7:0] is the binary value of the programmed voltage.
2. VT[7:0] is the binary value of the temperature compensated voltage. Its value comes
from the temperature compensation block and is a two’s complement which has the
value 0h at 20 C.
3. m and n are fixed values (see Table 28).
Figure 25 shows how VLCD changes with the programmed value of VPR[7:0].
Fig 24. VLCD generation including temperature compensation
013aaa257
TEMPERATURE
READOUT
40 0 +80+20 +50
TEMPERATURE
0 OFFSET
SLA SLB SLC SLD
8
TD
8
VPR[7:0]
8
V
LCD
nm
Table 28. Parameters of VLCD generation
Symbol Value Unit
m3 V
n0.03V
VLCD VPR 7:0VT 7:0+nm+=
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It has to be taken into account that the charge pump has to be configured (via bit CPC)
properly to obtain the desired voltage range. For example, if VDD2 = 3.0 V and CPC is set
to 2 VDD2 (logic 0) then the maximum theoretical valu e that the charge pump can reach
is VLCD = 6.0 V. But in reality, lower values will be reached due to internal resistances, see
Section 8.4.5. So, if the requested value for VLCD = 7.0 V then the charge pump ha s to be
configured with CPC set to 3 VDD2 (logic 1).
Programmable range of VPR[7:0] is from 0h to FFh. This would allow achieving
VLCD > 9.0 V, but the PCA9620 has a built-in automatic limitation of VLCD at 9.0 V.
If VDD2 is higher than 3.0 V, then it is important tha t VPR[7:0] is set to a value such that the
resultant VLCD (including the temperature correction of VT[7:0]) is higher than VDD2.
8.4.4 External VLCD supply
VLCD can be directly supplied to the VLCD pin. In this case, the internal char ge pump must
not be enabled otherwise a high current may occur on pin VDD2 and pin VLCD. When VLCD
is supplied externally, no inter nal temperature compensa tion occurs on this vo ltage even if
bit TCE is set logic 1 (see Section 8.4.8 on page 38). The VLCD voltage which is supplied
externally will be available at the segments and backplanes of the device through the
chosen bias system. Also programming the VPR[7:0] bit field ha s no effect on the VLCD
which is externally supplied.
(1) If VDD2 > 3.0 V then VPR[7:0] must be set so that VLCD > VDD2.
(2) Automatic limitation for VLCD > 9.0 V.
Fig 25. VLCD programming of PCA9620 (assuming VT[7:0] = 0h)
013aaa258
00 01 02
m
VLCD
VPR[7:0]
03 04 05 06 . . . . . . . . . . . . . . . . . . . . . . . . . . . FD FE FF
n
FC
9 V
C8 C9 CA
C7
(1)
(2)
VDD2
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8.4.5 Charge pump driving capability
Figure 26 illustrates the main factor determining how much current the charge pump can
deliver.
The output resist an ce of the char ge pump is specified in Table 36 on page 57. With these
values, it can be calculated how much current the charge pump can drive under certain
conditions.
Example: Assuming that the normal operation point is at 25 C with VLCD = 7.0 V and
VDD2 = 5.0 V and the charge pump is set to 2 VDD2. Then the the oretical value of VLCD is
10.0 V and the desired one is 7.0 V. The difference between the theoretical maximum
value and desired one is 3.0 V. The charge pump resistance is nominally 0.85 k.
Equation 7 shows the possible current that the charge pump could deliver :
(7)
The result of this example is:
In cases where no extreme driving capability is needed, a command is available for
decreasing the charge pump frequency (see Table 23 on page 13) and thus reducing the
total current consumption. If the charge pump frequency is halved, then the driving
capability is halved as well, whereas the output resistance doubles.
8.4.6 Charge pump frequency settings and power efficiency
The PCA9620 offers the possibility to use different frequency settings for the charge
pump. Bit CPF controls th e fre q uen cy at wh ich th e ch ar ge pum p is runn in g (se e Table 23
on page 13). This frequency has a direct influence on the current consumption of the IC
but also on the charge pump driving capability. Using a lower charge pump frequency
decreases the current consumption and the driving capability.
The power efficiency of the charge pump determines in certain applications which
frequency settings to choose for the CPF bit. Concerning the example shown in Figure 27:
The current consumption was measured with
charge pump set to 2 VDD2
VDD2 =3.0V
VPR[7:0] set to maximum to obt ai n the highest possib le VLCD with this setup, which is
close to 6.0 V
The current load on pin VLCD determines the output power delivered by the IC:
Fig 26. Charge pump model (used to characterize the driving strength)
Theoretical V
LCD
value
V
LCD
= 2 × V
DD2
or
V
LCD
= 3 × V
DD2
Output Resistance
R
o(cp)
Regulated desired V
LCD
This supplies the segments
and backplanes
013aaa259
Iload VLCD Rocp
=
Iload 3.0 V 0.85 k 3.5 mA==
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Product data sheet Rev. 3 — 3 July 2013 36 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
(8)
The current consumption on pin VDD2 determines the input power taken by the IC:
(9)
The ratio between these two numbers determines the charge pump power efficiency:
(10)
Loading the charge pump with higher currents decreases the output voltage. Th is
decrease is determined by the charge pump driving capability, respectively by the output
resistance of the charge pump (see Table 36 on page 57).
The power efficiency calculation is only valid when the charge pump is running at its
maximum peak frequency and regulates the generated VLCD voltage with full speed. In
this case, the ripple on the VLCD voltage equals the internal charge pump frequency.
Approximately, this could also be calculated with the parameter of the output resist ance of
the charge pump (see Table 36 on page 57), the load current, a nd the voltage needed to
be provided by using Equation 7 on page 35. This value of Iload is close to the value of the
load current needed for the application.
If the application runs with VDD2 = 3.0 V, the load currents are up to 400 A
(DC measured), and the VLCD generated volt ages are up to 5.0 V, then - concerning
power efficiency - it would be the best to have a charge pump frequency set to half
frequency.
Charge pump set to 2 VDD2; VDD2 =3V.
(1) p, full charge pump frequency.
(2) p, half charge pump frequency.
(3) VLCD, full frequency.
(4) VLCD, half frequency.
Fig 27. Power efficiency of the ch arg e pump
PoIload VLCD
=
PiIDD2 VDD2
=
pPoPi
=
Iload (μA)
0 1000800400 600200
001aan027
50
70
90
ηp
(%)
30
3
5
7
VLCD
(V)
1
(3)
(4)
(1)
(2)
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60 x 8 LCD high-drive segment driver for automotive and industrial
If it is desired to change the charge pump frequency, it is recommended to make a graph
like Figure 27 and understa nd what the application requirement s are. This would basically
imply to find out what would be the maximum VLCD requirements and what would be the
maximum load currents required. Then it can be decided which is the best setting of bit
CPF.
Tuning the charge pump frequency might be a difficult task to do. It requires good
knowledge of the application in which the IC is being used; therefore, NXP is
recommending to keep the CPF bit set logic 0 to have the maximum charge pump
frequency, thus having the ma xim u m dr ivin g str eng th.
8.4.7 Temperature readout
The PCA9620 has a built-in temperature sensor which provides an 8 bit digital value,
TD[7:0], of the ambient temperature. This value can be read through the I2C interface (see
Figure 50 on page 54). The actual temperature is determined from TD[7:0] using
Equation 11:
(11)
The measuremen t needs about 5 ms to complete. it is repeated periodically as soo n as bit
TME is set logic 1 (see Table 10 on page 9). The time between measurements is linked to
the system clock an d he nc e va rie s with ch an ge s in th e cho se n fram e frequ en cy, see
Table 29.
Due to the nature of a temperature sensor, oscillations on the VLCD may occur . To avoid it,
a filter has been implemented in PCA9620. The system is shown in Figure 28.
Like any other filtering, the digital temperature filter (see Figure 28) introduces a certain
delay in the measurement of temperature. This behavior is illustrated in Figure 29.
Table 29. Tempe ratu re measurement update rate
Selected frame frequency Temperature measurement update rate
60 Hz 3.3 s
200 Hz 1 s
300 Hz 0.67 s
Fig 28. Temperature measurement block with digital temperature filter
T (°C) 0.9375 TD 7:040=
TEMPERATURE
MEASUREMENT
BLOCK
DIGITAL
TEMPERATURE
FILTER
TD[7:0]
unfiltered TD[7:0]
filtered
enabled or disabled
by bit TFE
To the readout register
via I
2
C-bus and to
the V
LCD
compensation
block
013aaa260
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This delay may cause undesired effects at start-up when the environment temperature
may be dif feren t than the reset va lue of the PCA9620 which is 20 °C. In this case, it t ake s
up to 30 s until the correct measured temperature value will be available. A control bit,
TFE, is implemented to enable or disable the digital temperature filter. This bit is set
logic 0 by default which means that the filter is disa ble d an d the unfiltered environm e nt
temperature value is available to calculate the desired VLCD.
8.4.8 Temperature compensation of VLCD
Due to the temperature dependency of the liquid crystal viscosity, the LCD controlling
voltage VLCD might have to be adjusted at different temperatures to maintain optimal
contrast. The temperature behavior of the liquid comes from the LCD manufacturer. The
slope has to be set to compensate for the liquid behavior. Internal tempera ture
compensation may be enabled via bit TCE.
The ambient temperature range is split up into four equally sized regions and a different
temperature coefficient can be applied to each (see Figure 30). Each coefficient can be
selected from a choic e of eight di fferent slope s. Each one of these coefficients (see
Table 30) may be independently selected via the temp-comp-SLA to temp-comp-SLD
commands (see Table 5 on page 7).
(1) Environment temperature, T1 (C).
(2) Measured temperature, T2 (C).
(3) Temperature deviation, T=T2T1.
Fig 29. Temperature measurement delay
t (s)
0 1601208040
001aal393
20
30
10
40
50
T
(°C)
0
(3)
(1)
(2)
4
8
0
12
16
ΔT
(°C)(3)
4
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[1] The relationship between the temperature coefficients MA to MD and the slope factor is derived from the
following equation: .
[2] Default value.
The slope factors imply a linear correction, however the implementation is set in steps of
30 mV (parameter n in Table 28 on page 33).
Remark: After reset, VLCD is fixed because the VPR[7:0] bit field is reset logic 0. The
value of VT[7:0] is generated by the reset value of TD[7:0] (40h, representing 20 C).
Temperature compensation is implemented by adding an offset VT[7:0] to the VPR[7:0]
value. VT[7:0] is a two’s complement number that eq uals 0h at 20 C. The final result for
VLCD calculation is an 8-bit positive number (see Equation 6 on page 33).
Remark: Care must be taken that the ranges of VPR[7:0] and VT[7:0] do not cause
clipping and hence undesired results. The device will not permit overflow or underflow and
will clamp results to either end of the range.
Table 30. Temperature coefficients
SLA[2:0] to SLD[2:0] value Correspondin g slope factor
(mV/C) Temperature coefficients
MA, MB, MC, MD[1]
000[2] 00.00
001 40.125
010 80.25
011 16 0.5
100 40 1.25
101 +4 0.125
110 +8 0.25
111 +16 0.5
Fig 30. Example of segmented temperature coefficients
Mx 0.9375
0.03
---------------- slope
1000
--------------
=
Temperature (°C)
40 5010
013aaa261
TD[7:0]
0h 60h20h
V
LCD
with temperature
compensation (V)
zero offset
at 20 °C
7920
7Fh40h
MCMA MDMB
SLA SLB SLC SLD
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The Voffset(LCD) value can be calculated with the equations given in Table 31:
(12)
[1] No temperature compensation is possible above 80 C. Above this value, the system maintains the
compensation value from 80 C.
Example: Assumed that Tamb = 8C; TD[7:0] = 22h; MB = 0.5:
(13)
The VT[7:0] term is calculated using the digital temperature value TD[7:0] which is
provided by the temperature measurement block (Section 8.4.7). Therefore the accuracy
of the temperature measurement block (Tacc, see Table 36 on page 57) will be directly
translated to the LCD voltage deviation VLCD.
Since VT[7:0] = f[T,slope] and Tacc = 6C then , where slope has one
of the possible values specified in Table 30. This term will be added to the total LCD
voltage deviation Voffset(LCD)tot over the temperature range. So the total VLCD offset will
be: .
8.5 Oscillator
The internal logic and LCD drive signals of the PCA9620 are timed by a frequency fclk
which either is the built-in oscillator frequency fosc or equals an external clock frequency.
8.5.1 Internal oscillator
When the internal oscillator is used, it is possible to make the clock signal available on pin
CLK by using the oscillator-ctrl command (see Table 8 on page 8). If this is not intended,
pin CLK should be lef t o pen. At po wer-on th e signa l at pin CLK is d isable d and pin CLK is
in 3-state.
The duty cycle of th e output clock provided o n the CLK pin is not always 50 : 50. Table 18
on page 11 shows the expected duty cycle for each of the chose n frame frequencies.
8.5.2 External clock
In applications where an extern al clock needs to be applied to the PCA9620, bit OSC (see
Table 8 on page 8) must be set logic 1. In this case pin CLK becomes an input.
Table 31. Calculation of the temperature compensated voltage VT
Temperature range TD[7:0] Offset equation for VT
T 40 C0h
40 C T 10 C 0h to 20h
10 C < T 20 C 21h to 40h
20 C < T 50 C 41h to 60h
50 C < T < 80 C 61h to 7Eh
80 C T7Fh
[1]
Voffset LCD
mV
T
=
VT32MA32 MB=
VTTD 7:032MA 32 MB=
VTTD 7:064MB=
VTTD 7:064MC=
VTTD 7:096MD32 MC+=
VT31 MD32+MC=
Voffset LCD
mV
T
mTD[7:0] 64MB 30mV 34 640.5
30mV 300.5 450mV
== = =
=
VTTacc slope=
Voffset LCDtot VLCD VT
+=
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The CLK signal is a signal that is fed into the VDD1 domain so it must have an amplitude
equal to the VDD1 voltage supplied to the chip and be ref er enc e d to V SS.
The clock frequency (fclk) determines the LCD frame frequency ffr.
Remark: If an external clo ck is used then this clock signal must always be supplied to the
device; removing the clock may fr eeze the LCD in a DC st ate, which is not suitable for the
liquid crystal. Removal of the clock is possible when following the correct procedure s. See
Figure 13 on page 21 and Figure 14 on page 22.
8.5.3 Timing and frame frequency
The timing of the PCA9620 organizes the internal data flow of the device. It includes the
transfer of display data from the display RAM to the display segment outputs . The timing
also generates the LCD frame frequency which it derives as an integer division of the
clock frequency. The frame frequency is a fixed division of the internal clock or of the
frequency applied to pin CLK when an external clock is used:
(14)
When the internal clock is used, the clock and frame frequency can be programmed by
software such that the nominal frame frequency can be chosen in steps of 10 Hz in the
range of 60 Hz to 300 Hz (see Table 18 on page 11). Furthermore the nominal frame
frequency is factory-calibrated with an accuracy of 15 %.
When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock
may change when choosing different values for the frame frequency prescaler. Table 18
on page 11 shows the different output duty ratios for each frame frequency prescaler
setting.
8.6 Backplane outputs
The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane
output signals are generated based on the selected LCD multiplex drive mode.
Table 32 describes which outputs are active for each of the multiplex drive modes and
what signal is generated.
[1] These pins may optionally be connected to the display to improve drive strength. Connect only with the
corresponding output pin carrying the same signal. If not required, they can be left open-circuit.
ffr fclk
48
-------
=
Table 32. Mapping of output pins and corresponding output signals with respect to the
multiplex driving mode
Multiplex
drive
mode
Output pin
BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7
Signal
1:8 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7
1:6 BP0 BP1 BP2 BP3 BP4 BP5 BP0[1] BP1[1]
1:4 BP0 BP1 BP2 BP3 BP0[1] BP1[1] BP2[1] BP3[1]
1:2 BP0 BP1 BP0[1] BP1[1] BP0[1] BP1[1] BP0[1] BP1[1]
static BP0 BP0[1] BP0[1] BP0[1] BP0[1] BP0[1] BP0[1] BP0[1]
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60 x 8 LCD high-drive segment driver for automotive and industrial
8.7 Segment outputs
The LCD drive section includes 60 segment outp uts (S0 to S59) which must be conn ected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
60 segment outputs are required, the unused segment outputs must be left open-cir cuit.
8.8 Display register
The display register holds the display data while the corresponding multiplex signals ar e
generated.
8.9 Display RAM
The display RAM i s a st atic 60 8-bit RAM which stores LCD data. Logic 1 in the RAM bit
map indicates the on -state of the corresponding LCD elem en t; simila rly, logic 0 ind icat es
the off-state.
There is a one-to-one correspondence between
the bits in the RAM bitmap and the LCD elements
the RAM columns and the se gm e nt outp u ts
the RAM rows and the backplane outputs.
The display RAM bit map, Figure 31, shows row 0 to row 7 which corr espond with the
backplane outputs BP0 to BP7, and column 0 to column 59 which correspond with the
segment outputs S0 to S59. In multiplexed LCD applications, the data of each row of the
display RAM is time-mu ltiplexed with the corresponding b ackplane (row 0 with BP0, row 1
with BP1, and so on).
When display data is transmitted to the PCA9620, the display bytes received are stored in
the display RAM in ac co rd ance with th e sele ct ed LCD multiplex drive mode. The data is
stored as it arrives and does not wait for the acknowledge cycle as with the commands.
Depending on the current multiplex drive mode, data is stored singularly, in pairs,
quadruples, sextuples or bytes.
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8.9.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. It
allows the loading of an individual display data byte, or a series of display data bytes into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-dat a- pointer command. Following this comma nd, an arriving dat a
byte is stored starting at the display RAM address indicated by the data pointer.
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs, between the bits in a RAM row and the backplane outputs, and between the
RAM rows and banks.
Fig 31. Display RAM bitmap
display RAM columns/segment outputs (S)
display RAM rows/
backplane outputs
(BP)
013aaa262
columns
rows
0
1
2
3
4
5
6
7
01234 55 56 57 58 59
0
1
2
3
4
5
6
7
01234 55 56 57 58 59
0
1
2
3
4
5
6
7
01234 55 56 57 58 59
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
bank 0
bank 2
bank 4
bank 6
bank 0
bank 4
static drive mode
multiplex 1:2 drive mode
multiplex 1:4 drive mode
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The data pointer is automatically incremented in accordance with th e chosen LCD
multiplex drive mode configuration. That is, after each byte is stored, the contents of the
data pointer are incremen ted
by eight (sta tic drive mode)
by four (1:2 multiplex drive mode)
by two (1:4 multiplex drive mode)
by one or two (1:6 multiplex drive mode), see Figure 38 on page 47
by one (1:8 multiplex drive mode)
If the data pointer reaches the end of the RAM row, it is automatically wrapped around to
address 0. This means that it can b e continuously wr itten to or read from the d isplay RAM.
The dat a pointer should always be set to an addr ess where the remaining RAM is divisible
by eight because odd bits will be discarded (see Figure 33). This behavior is only shown
in static drive mode because the 60 RAM cells cannot be divided by eight without
remainder.
If an I2C-bus data access is terminated early, then the state of the data pointer is
unknown. The data pointer must then be re -written before further RAM accesses.
8.9.1.1 RAM filling in static drive mode
In the static drive mode the eight transmitted data bits are placed in eight successive
display RAM columns in row 0 (see Figure 32).
In order to fill the whole RAM row , 8 bytes must be sent to the PCA9620, but the last 4 bits
from the last byte are discarded, and the data pointer is wrapped around to column 0 to
start a possible RAM content update (see Figure 33).
Fig 32. Display RAM filling order in static drive mode
0 1 2 3 4 5 6 7 55 56 57 58 59
b0b1b2b3b4b5b6b7
0
MSB LSB
transmitted data byte
display RAM columns/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
013aaa263
b0b1b2b3b4b5b6b7
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8.9.1.2 RAM filling in 1:2 multiplex drive mode
In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four
successive display RAM columns of two rows (see Figure 34).
In order to fill the whole two RAM rows 15 bytes need to be sent to the PCA9620. After the
last byte sent, the data pointer is wrapped around to column 0 to start a possible RAM
content upda te (se e Figure 35). Even if a data byte is transmitted during the wrappin g of
the data pointer, then all the bits in the byte will be written correctly.
8.9.1.3 RAM filling in 1:4 multiplex drive mode
In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two
successive display RAM columns of four rows (see Figure 36).
Fig 33. Discarde d bits and data pointer wrap around at the end of data transmission
01234567 4849505152
display RAM
data pointer 53 54 55 56 57 58 59
0 a7 a6 a5 a4 a3 a2 a1 a0 f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0
discarded
wrap around
013aaa287
Fig 34. Display RAM filling order in 1:2 multiplex drive mode
Fig 35. Data pointer wrap around in 1:2 multiplex drive mode
01234567 5556575859
b0b1b2b3b4b5b6b7
0
1b7
b6 b5
b4 b3
b2 b1
b0 LSB
MSB
transmitted data byte
013aaa264
display RAM columns/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
01234567 5556575859
0
1b7
b6 b5
b4 b3
b2
b1
b0
display RAM
data pointer
wrap around
013aaa288
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Product data sheet Rev. 3 — 3 July 2013 46 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
In order to fill the whole four RAM rows 30 bytes need to be sent to the PCA9620. After
the last byte sent, th e dat a pointer is wr apped aroun d to column 0 to st art a possible RAM
content upda te (se e Figure 37). Even if a data byte is transmitted during the wrappin g of
the data pointer, all the bits in the byte will be written correctly.
8.9.1.4 RAM filling in 1:6 multiplex drive mode
In the 1:6 multiplex drive mode the RAM is organize d in six rows and 60 columns. The
eight transmitted data bits are placed in such a way, that a column is filled up (see
Figure 38).
Fig 36. Display RAM filling order in 1:4 multiplex drive mode
Fig 37. Data pointer wrap around in 1:4 multiplex drive mode
01234567 5556575859
b0b1b2b3b4b5b6b7
0
MSB LSB
1
2
3
transmitted data byte
b7
b6
b5
b4
b3
b2
b1
b0
display RAM columns/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
013aaa265
01234567 5556575859
0
1
2
3
b7
b6
b5
b4
b3
b2
b1
b0
display RAM columns/segment outputs (S)
columns
display RAM
data pointer
013aaa289
wrap around
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Product data sheet Rev. 3 — 3 July 2013 47 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
The remaining bits are wrapped up into the next column. In order to fill the whole RAM
addresses 45 byte s ne ed to be sent to the PCA9620. After the last byte sent, the data
pointer is wrapped around to column 0 to start a possible RAM content update (see
Figure 39). Even if a data byte is transmitted during the wrapping of the data pointer, all
the bits in the byte will be written correctly.
8.9.1.5 RAM filling in 1:8 multiplex drive mode
In the 1:8 multiplex drive mode the e ight transmitted data bits are placed into eight rows of
one display RAM column (see Figure 40).
Fig 38. Display RAM filling order in 1:6 multiplex drive mode
Fig 39. Data pointer wrap around in 1:6 multiplex drive mode
0 1 2 3 4 5 6 7 5556575859
a0a1a2a3a4a5a6a7
0
MSB LSB
1
2
3
4
5
transmitted data bytes
a7
a6
a5
a4
a3
a2
a1
a0
b0b1b2b3b4b5b6
c0c1c2c3c4c5c6
b7
c7
b7
b6
b5
b4
b3
b2
b1
b0
c7
c6
c5
c4
c3
c2
c1
c0
display RAM columns/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
013aaa266
data pointer
incrementation
0 1 2 3 4 5 6 7 5556575859
0
1
2
3
4
5
a7
a6
a5
a4
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
c7
c6
c5
c4
c3
c2
c1
c0
display RAM
data pointer
013aaa290
wrap around
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Product data sheet Rev. 3 — 3 July 2013 48 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
In order to fill the whole RAM addresses 60 bytes need to be sent to the PCA9620. After
the last byte sent, th e dat a pointer is wr apped aroun d to column 0 to st art a possible RAM
content upda te (se e Figure 41). In this case, there is no situation possible where a
transmitted data byte can be written over the RAM boundary.
8.9.2 Bank selection
A RAM bank can be thought of as a collection of RAM rows. The PCA9620 includes a
RAM bank switching feature in the static, 1:2, and 1:4 multiplex drive modes.
The RAM bank switching gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is complete. Input and output banks
can be set independently from one another with the input-bank-select and the
output-bank-select commands; Figure 42 shows the concept.
Fig 40. Display RAM filling order in 1:8 multiplex drive mode
Fig 41. Data pointer wrap around in 1:8 multiplex drive mode
01234567 5556575859 b0b1b2b3b4b5b6b7
0
MSB LSB
1
2
3
4
5
6
7
transmitted data byte
b7
b6
b5
b4
b3
b2
b1
b0
display RAM columns/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
013aaa267
01234567 5556575859
0
1
2
3
4
5
6
7
b7
b6
b5
b4
b3
b2
b1
b0
display RAM
data pointer
013aaa291
a7
a6
a5
a4
a3
a2
a1
a0
wrap around
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Product data sheet Rev. 3 — 3 July 2013 49 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
In Figure 42 an example is shown for 1:4 multiplex drive mode. The displayed data is read
from the first four rows of the memory (bank 0), while the transmitted data is stored in the
second four rows of the memor y (ban k 4) which is currently not accesse d for the readin g.
Therefore different content can be loaded into the first and second four RAM rows which
will be immediately displayed on the LCD by switching it with the output-bank-select
command (see Figure 43).
8.9.2.1 Input-bank-select
The input-bank-select command (see Table 19 on page 12) loads display data into the
display RAM in accordance with the selected LCD drive configuration.
In static drive mode, an individ ual content can be stored in each RAM ba nk (bank 0 to
bank 7 which corresponds to row 0 to row 7).
In 1:2 multiplex drive mode, individual content for RAM bank 0 (row 0 and row 1),
RAM bank 2 (row 2 and row 3), RAM bank 4 (row 4 and 5) and RAM bank 6 (row 6
and row 7) can be stored.
In 1:4 multiplex drive mode individual content can be stored in RAM bank 0 (row 0 to
row 3) and RAM bank 4 (row 4 to row 7).
The input-bank-select command works independently to the output-bank-select.
Fig 42. Example of bank se le ction in 1:4 multiplex mode
Fig 43. Example of the input-bank-select and the output-bank-select command with
multiplex drive mode 1:4
MICROCONTROLLER DISPLAYRAM
BANK 0
BANK 4
013aaa422
INPUT-BANK-SELECT COMMAND
CONTROLS THE INPUT DATA PATH OUTPUT-BANK-SELECT COMMAND
CONTROLS THE OUTPUT DATA PATH
4
5
6
7
display RAM columns/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
013aaa424
01234567 5556575859
0
1
2
3
to the LCD
output RAM bank
input RAM bank
to the RAM
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Product data sheet Rev. 3 — 3 July 2013 50 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
8.9.2.2 Output-bank-select
The output-bank-select command (see Table 2 0 on page 12) selects the display RAM
transferring it to the display register in accordance with the selected LCD drive
configuration.
In the static drive mode, it is possible to request the content of RAM bank 1 (row 1) to
RAM bank 7 (row 7) for display instead of the default RAM bank 0 (row 0).
In 1:2 multiplex drive mode, the content of RAM bank 2 (row 2 and row 3) or of RAM
bank 4 (row 4 and row 5) or of RAM bank 6 (row 6 and row 7) may be selected
instead of the default RAM bank 0 (row 0 and row 1).
In 1:4 multiplex drive mode, the content of RAM bank 4 (row 4, 5, 6, and 7) may be
selected instead of RAM bank 0 (row 0, 1, 2, and 3).
The output-bank-select command works independently to the input-bank-select.
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Product data sheet Rev. 3 — 3 July 2013 51 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
9. I2C-bus interface characteristics
The I2C-bus is for bidire ctional, two-line communication between dif ferent ICs or modules.
The two lines are a Serial DAt a line (SDA) and a Serial CLock lin e (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data b it is transferred du ring each clock pu lse. The data o n the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 44).
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
A LOW-to-HIGH change of the da ta line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 45.
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 46.
Fig 44. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 45. Definition of START and STOP conditions
mbc622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
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Product data sheet Rev. 3 — 3 July 2013 52 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
9.4 Acknowledge
The number of data bytes tran sf er re d be tween the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not gen erating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 47.
Fig 46. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig 47. Acknowledgement on the I2C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
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Product data sheet Rev. 3 — 3 July 2013 53 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
9.5 I2C-bus controller
The PCA9620 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I 2C-bus master receiver. The only data output from PCA9620 are the
acknowledge signals and the temperature readout byte of the selected device.
9.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
9.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address.
Four different I2C-bus slave addresses can be used to address the PCA9620 (see
Table 33).
The least significant bit of the slave address byte is bit R/W. Bit 1 and bit 2 of the slave
address are defined by connecting the inputs A0 and A1 to either VSS (logic 0) or VDD
(logic 1). Therefore, four instances of PCA9620 can be distinguished on the same
I2C-bus.
9.8 I2C-bus protocol
Table 33. I2C slave address
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
slave address 0 1 1 1 0 A1 A0 R/W
Fig 48. I2C-bus protocol writ e mo de
EXAMPLES
a) transmit two bytes of RAM data
013aaa293
A
0
S01110 0
control byte
slave address RAM/command byte
RAM DATA
M
S
B
L
S
B
AAP
R/W = 0
S01110 0 01
AAAP
RAM DATA A
b) transmit two command bytes
COMMAND
S01110 0 10
AAAP
COMMAND A
A
c) transmit one command byte and two RAM date bytes
COMMAND
S01110 0 10
00
01
AAAP
RAM DATA ARAM DATA A
A
C
OR
S
A
1
A
0
A
1
A
0
A
1
A
0
A
1
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Product data sheet Rev. 3 — 3 July 2013 54 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
The I2C-bus protocol is shown in Figure 48. The sequence is initiated with a START
condition (S) from the I 2C-bus master wh ich is followed b y one of the four PCA9620 slave
addresses available. All PCA9620’ s with the co rresponding A1 and A0 level ac knowledge
in parallel to the slave address, but all PCA9620 with the alternative A1 and A0 levels
ignore the whole I2C-bus transfer.
After acknowledgemen t, a co nt rol byte follows which defines if the next byte is RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data.
In this way it is possible to configure the device and then fill the display RAM with little
overhead.
The display bytes are stored in the display RAM at the address specified by the data
pointer.
The acknowledgement after each byte is made only by the (A0 and A1) addressed
PCA9620. After the last display byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be issued to RESTART an I2C-bus access.
If a temperature readout (byte TD[7:0]) is made the R/W bit must be logic 1 and then the
next data byte following is provided by the PCA9620 as shown in Figure 50.
Table 34. Co ntrol byte description
Bit Symbol Value Description
7CO continue bit
0 last control byte
1 control byt es continue
6RS register selection
0 command register
1 data register
5 to 0 - - not relevant
Fig 49. Control byte format
Fig 50. I2C-bus protocol read mode
mgl753
not relevant
CO
76543210
RS
MSB LSB
013aaa294
A
0
S01110 1
slave address temperature
readout byte
M
S
B
L
S
BAP
R/W = 1
A
1A
acknowledge
from PCA9620 acknowledge
from master
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Product data sheet Rev. 3 — 3 July 2013 55 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
10. Internal circuitry
11. Safety notes
Fig 51. Device protection diagram
A0, A1, T1,
T2, CLK
V
DD1
V
SS
013aaa295
BP0 to BP7,
S0 to S59
V
LCD
V
SS
T3, V
LCD
, SDA,
SCL, V
DD1
, V
DD2
V
SS
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
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Product data sheet Rev. 3 — 3 July 2013 56 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
12. Limiting values
[1] Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114.
[2] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101.
[3] Pass level; latch-up testing according to Ref. 10JESD78 at maximum ambient temperature (Tamb(max)).
[4] According to the store and transport requirements (see Ref. 14 “UM10569) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
Table 35. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD1 supply voltage 1 analog and digital 0.5 +6.5 V
VDD2 supply voltage 2 charge pump 0.5 +6.5 V
IDD1 supply current 1 analog and digital 50 +50 mA
IDD2 supply current 2 charge pump 50 +50 mA
VLCD LCD supply voltage 0.5 +10 V
IDD(LCD) LCD supply current 50 +50 mA
Viinput voltage o n pins CLK,
SDA, SCL, A0,
A1, T1, T2, T 3
0.5 +6.5 V
IIinput current 10 +10 mA
VOoutput voltage on pins S0 to S59,
BP0 to BP7 0.5 +10 V
on pins SDA, CLK 0.5 +6.5 V
IOoutput current 10 +10 mA
ISS ground supply curren t 50 +50 mA
Ptot total power dissipation - 400 mW
P/out power dissipation per
output -100mW
VESD electrostatic discharge
voltage HBM [1] -4000 V
CDM [2] -1500 V
Ilu latch-up current [3] -100mA
Tstg storage temperature [4] 65 +150 C
Tamb ambient temperature operating device 40 +105 C
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Product data sheet Rev. 3 — 3 July 2013 57 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
13. Static characteristics
Table 36 . Static characteristics
VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V ; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb =
40
C to +105
C; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD1 supply voltage 1 2.5 - 5.5 V
VDD2 supply voltage 2 VDD2 VDD1 2.5 - 5.5 V
VLCD LCD supply voltage VLCD VDD2 [1] 2.5 - 9.0 V
VLCD LCD voltage variation VDD1 =V
DD2 =5.0V;
VLCD = 6.99 V [2][3] 0.10 - +0.10 V
IDD(pd) power-down mode supply
current on pin VDD1 [4][5] -1.03.0A
IDD1 supply current 1 [5][6] -100200A
IDD2 supply current 2 fosc = 9.6 kHz
charge pump off; external VLCD [5][6] -0.53.0A
charge pump on; internal VLCD [5][7] -250550A
IDD(LCD) LCD supply current external VLCD [5][8] -125250A
ILCD(pd) power-down LCD current external VLCD [4][5] -1235A
ROoutput resistance of charge pump (driving capabilities)
charge pump set to 2 VDD2;
Iload = 3 mA (on pin VLCD)[9] 0.2 0.85 1.6 k
charge pump set to 3 VDD2;
Iload = 2 mA (on pin VLCD)[10] 2.0 3.2 4.5 k
Tacc temperature accuracy readout temperature error;
VDD1 =5.0V
Tamb =40 C to +105 C6-+6C
Tamb =27C4-+4C
Logic
VIinput voltage VSS 0.5 - VDD + 0.5 V
VIL LOW-level input voltage on pins CLK, A1, A0 - - 0.3VDD V
VIH HIGH-level input voltage on pins CLK, A1, A0 0.7VDD -- V
VOoutput voltage 0.5 - VDD + 0.5 V
VOH HIGH-level output voltage on pin CLK 0.8VDD -- V
VOL LOW-level output voltage on pin CLK - - 0.2VDD V
IOH HIGH-level output current output source current;
VOH =4.6V; V
DD = 5 V; on pin CLK 1-- mA
IOL LOW-level output current output sink current;
VOL = 0.4 V; VDD = 5 V; on pin CLK 1-- mA
VPOR power-on reset voltage [11] --1.6V
ILleakage current Vi=V
DD or VSS; on pins CLK, A1,
A0, T1, T2, T3 [12] -0-A
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Product data sheet Rev. 3 — 3 July 2013 58 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
[1] When supplying external VLCD it must be VLCD VDD2. Also when using the inter nal charge pump to generate a certain VLCD, VPR[7:0]
must be set to a value that the voltage is higher than VDD2 (see Section 8.4.3 on page 33).
[2] Calibrated at testing stage. VLCD temperature compensation is disabled.
[3] According to Equation 6 on page 33: VLCD = 133 0.03 + 3 = 6.99 V.
[4] Display is disabled; I2C-bus inactive; temperature measurement disabled.
[5] The typical value is defined at VDD1 =V
DD2 = 5.0 V, VLCD = 7.0 V and 30 C.
[6] Temperature measurement enabled; 1:8 multiplex drive mode; 14 bias; display enabled; LCD outputs are open circuit; RAM is all written
with logic 1; inputs at VSS or VDD; internal clock with the default prescale factor; I2C-bus inactive.
[7] VDD2 = 5.0 V ; charge pump set to 2 VDD2; VPR[7:0] set for VLCD = 7.0 V ; 1:8 multiplex drive mode; 14 bias; temperature measurement
enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 %
duty factor; I2C-bus inactive.
[8] External supplied VLCD = 7.0 V; 1:8 multiplex drive mode; 14 bias; temperature measurement enabled; display enabled; LCD outputs
are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[9] VDD2 = 5.0 V; charge pump set to 2 VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 23 on page 13) set logic 0.
[10] VDD2 = 4.0 V; charge pump set to 3 VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 23 on page 13) set logic 0.
[11] If VDD1 > V POR then no reset occurs.
[12] In case of an ESD event, the value may increase slightly.
[13] Variation between any 2 backplanes on a given voltage level; static measured.
[14] Variation between any 2 segments on a given voltage level; static measured.
[15] Outputs measured one at a time.
I2C-bus; pins SDA and SCL
VIinput voltage VSS 0.5 - 5.5 V
VIL LOW-level input voltage pins SCL, SDA - - 0.3VDD V
VIH HIGH-level input voltage pins SCL, SDA 0.7VDD -- V
VOoutput voltage pins SCL, SDA 0.5 - 5.5 V
IOL LOW-level output current VOL = 0.4 V; VDD = 5 V; on pin SDA 3 - - mA
ILleakage current VI=V
DD or VSS [12] -0-A
LCD outputs
VOoutput voltage variation on pins BP0 to BP7 [13] 15 - +15 mV
on pins S0 to S59 [14] 15 - +15 mV
ROoutput resistance VLCD = 7 V; on pins BP0 to BP7 [15] 0.3 0.8 1.5 k
VLCD = 7 V ; on pins S0 to S59 [15] 0.6 1.5 3 k
Table 36 . Static characteristics …continued
VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V ; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb =
40
C to +105
C; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 3 — 3 July 2013 59 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
(1) VPR[7:0] = 85h.
(2) VPR[7:0] = 64h.
(3) VPR[7:0] = A4h.
Temperature compensation disabled.
Fig 52. Typical VLCD with respect to temperature
VDD1 =5.0V.
Fig 53. Typical IDD1 with respect to temperature
temperature (°C)
50 150100500
001aan026
6.8
7.3
6.3
7.8
8.3
VLCD
(V)
5.8
(3)
(1)
(2)
001aan023
temperature (°C)
40 12080400
80
100
120
IDD1
(μA)
60
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Product data sheet Rev. 3 — 3 July 2013 60 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
Charge pump set to 2 VDD2; VLCD = 7.0 V; VDD1 =V
DD2 =5.0V.
Fig 54. Typical IDD2 with respect to temperature
VLCD = 7.0 V, external supplied; VDD1 =V
DD2 = 5.0 V; display enabled, but no display attached.
Fig 55. Typical ILCD with respect to temperature
temperature (°C)
40 12080400
001aan024
180
220
140
260
300
IDD2
(μA)
100
001aan025
temperature (°C)
40 12080400
100
120
140
ILCD
(μA)
80
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14. Dynamic characteristics
[1] Internal calibration made with OTP so that the maximum variation is 15 % over whole temperature and voltage range. The typical fosc
generates a typical frame frequency of 200 Hz when the default frequency division factor is used (see Section 8.5.3 on page 41).
[2] The typical value is defined at VDD1 =V
DD2 = 5.0 V and 30 C.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
[4] tVD;DAT = minimum time for valid SDA output following SCL LOW.
[5] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
Table 37. Dynam ic characteristics
VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V ; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb =
40
C to +105
C; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
fosc oscillator frequency on pin CLK; see Table 18 on
page 11 [1][2] 8160 9600 11040 Hz
fclk(ext) external clock frequency 450 - 14500 Hz
tclk(H) HIGH-level clock time external clock source used 33 - - s
tclk(L) LOW-level clock time 33 - - s
Timin g characteristics: I2C-bus[3]
fSCL SCL frequency - - 400 kHz
tBUF bus free time between a
STOP and START condition 1.3 - - s
tHD;STA hold time (repeated) START
condition 0.6 - - s
tSU;STA set-up time for a repeated
START condition 0.6 - - s
tVD;DAT data valid time [4] --0.9s
tVD;ACK data valid acknowledge time [5] --0.9s
tLOW LOW period of the SCL clock 1.3 - - s
tHIGH HIGH period of the SCL clock 0.6 - - s
tffall time of both SDA and SCL signals - - 0.3 s
trrise time of both SDA and SCL signals - - 0.3 s
Cbcapacitive load for each bus
line - - 400 pF
tSU;DAT data set-up time 100 - - ns
tHD;DAT data hold time 0 - - ns
tSU;STO set-up time for STOP
condition 0.6 - - s
tw(spike) spike pulse w idth - - 50 ns
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60 x 8 LCD high-drive segment driver for automotive and industrial
15. Test information
15.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism ba sed stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
Fig 56. Driver timing waveforms
Fig 57. I2C-bus timing waveforms
013aaa296
CLK
t
clk(H)
t
clk(L)
1/f
clk
0.7 V
DD
0.3 V
DD
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
013aaa417
t
SU;STO
protocol START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6) bit 0
(R/W) acknowledge
(A)
STOP
condition
(P)
1
/f
SCL
t
r
t
VD;DAT
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16. Package outline
Fig 58. Package outline SOT315-1 (LQFP80)
UNIT A
max. A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.16
0.04 1.5
1.3 0.25 0.27
0.13 0.18
0.12 12.1
11.9 0.5 14.15
13.85 1.45
1.05 7
0
o
o
0.15 0.10.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.30
SOT315-1 136E15 MS-026 00-01-19
03-02-25
D(1) (1)(1)
12.1
11.9
HD
14.15
13.85
E
Z
1.45
1.05
D
bp
e
θ
EA1
A
Lp
detail X
L
(A )
3
B
20
c
D
H
bp
E
HA2
vMB
D
ZD
A
ZE
e
vMA
X
1
80
61
60 41
40
21
y
pin 1 index
wM
wM
0 5 10 mm
scale
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
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17. Bare die outline
Fig 59. Bare die outline of PCA9620
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
PCA9620U
pca9620u_do
Bare die; 80 bonding pads PCA9620U
detail X
e
X
00y
x
D
E
(1)
A
P2
P1
P4P3
1
20
21 40
41
60
6180
Notes
1. Marking code: PC9620-1
11-09-15
11-09-26
pin 1 index
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[1] Dimension includes saw lane (70 m).
[2] See Table 39.
[3] P1 and P3: pad size.
[4] P2 and P4: passivation opening.
Table 38. Dimensions of PCA9620
Original dimensions are in mm.
Unit
(mm) A D[1] E[1] e[2] P1[3] P2[4] P3[3] P4[4]
max---0.203----
nom 0.38 3.166 3.166 - 0.065 0.056 0.065 0.056
min---0.075----
Table 39. Bondi ng pad description of PCA9620
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see
Figure 59.
Symbol Pad Location Pitch Description
X(m) Y(m) X(m) Y(m)
S20 1 1497.3 1208.7 - - LCD segment output
S21 2 1497.3 1086.3 0 122.4
S22 3 1497.3 963.9 0 122.4
S23 4 1497.3 841.5 0 122.4
S24 5 1497.3 719.1 0 122.4
S25 6 1497.3 568.8 0 150.3
S26 7 1497.3 446.4 0 122.4
S27 8 1497.3 324.0 0 122.4
S28 9 1497.3 201.6 0 122.4
S29 10 1497.3 79.2 0 150.3
S30 11 1497.3 71.1 0 122.4
S31 12 1497.3 193.5 0 122.4
S32 13 1497.3 315.9 0 122.4
S33 14 1497.3 438.3 0 122.4
S34 15 1497.3 560.7 0 122.4
S35 16 1497.3 711.0 0 122.4
S36 17 1497.3 833.4 0 122.4
S37 18 1497.3 955.8 0 122.4
S38 19 1497.3 1078.2 0 122.4
S39 20 1497.3 1200.6 0 122.4
S40 21 1204.2 1497.3 - -
S41 22 1081.8 1497.3 122.4 0
S42 23 959.4 1497.3 122.4 0
S43 24 837.0 1497.3 122.4 0
S44 25 714.6 1497.3 122.4 0
S45 26 564.3 1497.3 150.3 0
S46 27 441.9 1497.3 122.4 0
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S47 28 319.5 1497.3 122 .4 0 LCD segmen t output
S48 29 197.1 1497.3 122.4 0
S49 30 74.7 1497.3 122.4 0
S50 31 75.6 1497.3 150.3 0
S51 32 198.0 1497.3 122.4 0
S52 33 320.4 1497.3 122.4 0
S53 34 442.8 1497.3 122.4 0
S54 35 565.2 1497.3 122.4 0
S55 36 715.5 1497.3 150.3 0
S56 37 837.9 1497.3 122.4 0
S57 38 960.3 1497.3 122.4 0
S58 39 1082.7 1497.3 122.4 0
S59 40 1205.1 1497.3 122.4 0
BP0 41 1497.3 1201.5 - - LCD backplane output
BP1 42 1497.3 1077.3 0 124.2
BP2 43 1497.3 953.1 0 124.2
BP3 44 1497.3 828.9 0 124.2
BP4 45 1497.3 676.8 0 152.1
BP5 46 1497.3 552.6 0 124.2
BP6 47 1497.3 428.4 0 124.2
BP7 48 1497.3 304.2 0 124.2
VLCD 49 1497.3 171.9 0 132.3 LCD supply voltage
VDD2 50 1497.3 47.7 0 124.2 supply voltage 2 (charge pump)
VDD1 51 1497.3 76.5 0 124.2 supply voltage 1 (analog and digital)
VSS 52 1497.3 166.5 0 90 ground supply voltage
T1 53 1497.3 241.2 0 74.7 test pin
T2 54 1497.3 315.9 0 74.7
T3 55 1497.3 430.2 0 114.3
CLK 56 14 97.3 620.1 0 189.9 internal oscillator output, external oscillator input
A0 57 1497.3 729.9 0 109.8 I2C-bus slave address selection bit
A1 58 1497.3 806.4 0 76.5
SCL 59 1497.3 913.5 0 107.1 I2C-bus serial clock
SDA 60 1497.3 1116.9 0 203.4 I2C-bus serial data
S0 61 1205.1 1497.3 - - LCD segment output
S1 62 1082.7 1497.3 122.4 0
S2 63 960.3 1497.3 122.4 0
S3 64 837.9 1497.3 122.4 0
S4 65 715.5 1497.3 122.4 0
Table 39. Bondi ng pad description of PCA9620 …co n tinue d
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see
Figure 59.
Symbol Pad Location Pitch Description
X(m) Y(m) X(m) Y(m)
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[1] The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 60)
with respect to the center (x/y = 0) of the chip; see Figure 59.
[2] The x/y values of the dimensions represent the extensions of the alignment mark in direction of the
coordinate axis (see Figure 60).
S5 66 565.2 1497.3 150.3 0 LCD segment output
S6 67 442.8 1497.3 122.4 0
S7 68 320.4 1497.3 122.4 0
S8 69 198.0 1497.3 122.4 0
S9 70 75.6 1497.3 122.4 0
S10 71 74.7 1497.3 150.3 0
S11 72 197.1 1497.3 122.4 0
S12 73 319.5 1497.3 122.4 0
S13 74 441.9 1497.3 122.4 0
S14 75 564.3 1497.3 122.4 0
S15 76 714.6 1497.3 150.3 0
S16 77 837.0 1497.3 122.4 0
S17 78 959.4 1497.3 122.4 0
S18 79 1081.8 1497.3 122.4 0
S19 80 1204.2 1497.3 122.4 0
Table 39. Bondi ng pad description of PCA9620 …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see
Figure 59.
Symbol Pad Location Pitch Description
X(m) Y(m) X(m) Y(m)
Table 40. Alignment mark dimension and location of all PCA9620 types
Coordinates
X (m) Y (m)
Location[1]
1495.8 1395.0
Dimension[2]
52.5 63.72
Fig 60. Alignment mark
013aaa511
REF
y
x
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18. Packing information
18.1 Wafer information
Wafer thickness, see Table 41.
Fig 61. Wafer layout of PCA9620
X
Saw lane
detail X
Marking code
Straight edge
of the wafer
013aaa512
Pin 1
18 µm
70 µm
Seal ring plus gap to
active circuit ~18 mm
18 µm
70 µm
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60 x 8 LCD high-drive segment driver for automotive and industrial
Table 41. PCA9620 wafer information
Type number Wafer thickness Wafer diameter Marking of ba d die
PCA9620/5GA/Q1 0.687 mm 6 inch wafer mapping
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19. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred whe n through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circui t board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
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19.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 62) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 42 and 43
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 62.
Table 42. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperatu re (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 43. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperatu re (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 3 — 3 July 2013 72 of 81
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For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
MSL: Moisture Sensitivity Level
Fig 62. Temperature profiles for large and small component s
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
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20. Abbreviations
Table 44. Abbreviations
Acronym Description
AEC Automotive Electronics Council
CDM Charged-Device Model
DC Direct Current
EPROM Erasable Programmable Read-Only Memory
ESD ElectroStatic Discharge
HBM Human Body Model
I2C Inter-Integrated Circuit bus
IC Integrated Circuit
LCD L iquid Crystal Display
LSB Least Significant Bit
MSB Most Significant Bit
MSL Moisture Sensitivity Level
MUX Multiplexer
OTP One Time Programmable
PCB Printed-Circuit Board
POR Power-On Reset
RC Resistance-Capacitance
RAM Random Access Memory
RMS Root Mean S qu a re
SCL Serial CLock line
SDA Serial DAta line
SMD Surface Mount Device
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21. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10706 — Handling bare die
[3] AN10853 — ESD and EMC sensitivity of IC
[4] AN11267EMC and system level ESD design guidelines for LCD drivers
[5] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[6] IEC 61340-5 — Prot ection of electronic devices from electrostatic phenomena
[7] IPC/JEDEC J-STD-020DMoisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[8] JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Te sting Human Body
Model (HBM)
[9] JESD22-C10 1 Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[10] JESD78 — IC Latch-Up Test
[11] JESD62 5 -A Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[12] SNV-FA-01-02 — Marking Formats Integrated Circuits
[13] UM10204 — I2C-bus specificati on and user manual
[14] UM10569 — Store and transp ort requirements
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22. Revision history
Table 45. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9620 v.3 20130703 Produ ct data sheet - PCA9620 v.2
Modifications: Changed VLCD specification (Table 36)
PCA9620 v.2 2011110 8 Produ ct data sheet - PCA9620 v.1
PCA9620 v.1 20101209 Product data sheet - -
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23. Legal information
23.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full da ta sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
23.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their application s
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associa ted with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cu stomer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 July 2013 77 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (transla ted) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English version s.
Bare die — All die are tested on compliance with their r elated technical
specifications as sta ted in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the dat a sheet. There are no post-pa cking tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditione d upon and sub ject to the custo mer enter ing into a
written die sale agreement with NXP Semiconductors through its legal
department.
23.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP B.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 July 2013 78 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
25. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 5. Commands of PCA9620 . . . . . . . . . . . . . . . . . .7
Table 6. Initialize - initialize command bit description . . .8
Table 7. OTP-refresh - OTP-refresh command bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 8. Oscilla tor-ctrl - oscillator control command
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 9. Charge-pump-ctrl - charge pump control
command bit description . . . . . . . . . . . . . . . . . .9
Table 10. Temp-msr-ctrl - temperature measurement
control command bit description . . . . . . . . . . . .9
Table 11. Set-VPR-MSB - set VPR MSB command
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 12. Set-VPR-LSB - set VPR LSB command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 13. Di splay-enable - display enable command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 14. Set-MUX-mode - set multipl ex drive mode
command bit description . . . . . . . . . . . . . . . . .10
Table 15. Set-bia s -mode - set bias mode command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 16. Lo ad-data-pointer - load data pointer
command bit description . . . . . . . . . . . . . . . . .11
Table 17. Fr ame frequency - frame frequency and output
clock frequency command bit description . . . .11
Table 18. Frame frequency values . . . . . . . . . . . . . . . . .11
Table 19. Input-bank-select - input bank select
command bit description[1] . . . . . . . . . . . . . . . .12
Table 20. Output-bank-select - output bank select
command bit description[1] . . . . . . . . . . . . . . . .12
Table 21. Write-RAM-data - write RAM data command
bit descripti on[1] . . . . . . . . . . . . . . . . . . . . . . . .1 3
Table 22. Temp-read - temperature readout command
bit descripti on[1] . . . . . . . . . . . . . . . . . . . . . . . .13
Table 23. Invmode _CPF_ctrl - inversion mode and
charge pump frequency prescaler command
bit description . . . . . . . . . . . . . . . . . . . . . . . . .13
Tabl e 24 . Temp-filte r - dig ital temperature filt er
command bit description . . . . . . . . . . . . . . . . .14
Table 25. Selecti on of possible display configurations. . .15
Table 26. Reset states . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 27. LC D drive modes: summary of characteristics.23
Table 28. Para meters of VLCD generation . . . . . . . . . . . .33
Table 29. Temperature measurement update rate . . . . .37
Table 30. Temperature coefficients. . . . . . . . . . . . . . . . . .39
Table 31. Calculation of the temperature compensated
voltage VT. . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 32. Map ping of output pins and corresponding
output signals with respect to the multiplex
driving mode . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 33. I2C slave address . . . . . . . . . . . . . . . . . . . . . . .53
Table 34. Control byte description . . . . . . . . . . . . . . . . . .54
Table 35. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 36. Static characteristics . . . . . . . . . . . . . . . . . . . . 57
Table 37. Dynamic characteristics . . . . . . . . . . . . . . . . . 61
Table 38. Dimensions of PCA9620 . . . . . . . . . . . . . . . . . 65
Table 39. Bonding pad description of PCA9620 . . . . . . . 65
Table 40. Alignment mark dimension and location of all
PCA9620 types . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 41. PCA9 620 wafer information. . . . . . . . . . . . . . . 69
Table 42. SnPb eutectic process (from J-STD -0 2 0D) . . . 71
Table 43. L ead-free process (from J-STD-020D) . . . . . . 71
Table 44. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 45. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 75
PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 July 2013 79 of 81
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
26. Figures
Fig 1. Block diagram of PCA9620 . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration for LQFP80 (PCA96 20H). . . . . .4
Fig 3. Pin configuration for PCA9620U (b are die) . . . . . .5
Fig 4. Example of displays suitable for PCA9620 . . . . .15
Fig 5. Typical system configuration when using the
internal VLCD generation . . . . . . . . . . . . . . . . . . .15
Fig 6. Typical system configuration when using
an external VLCD . . . . . . . . . . . . . . . . . . . . . . . . .1 6
Fig 7. Recommended start-up sequence when using
the internal charge pump and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Fig 8. Recommended start-up sequence when using
an external supplied VLCD and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 9. Recommended start-up sequence when using
the internal charge pump and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Fig 10. Recommended start-up sequence when using
an external supplied VLCD and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 11. Recommended power-down sequence for minimum
power-down current when using the internal charge
pump and the internal clock signal . . . . . . . . . . .20
Fig 12. Recommended power-down sequence when using
an external supplied VLCD and the internal
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 13. Recommended power-down sequence when using
the internal charge pump and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 14. Recommended power-down sequence when using
an external supplied VLCD and an external
clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 15. Electro-optical characteristic: relative transmission
curve of the liquid . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 16. Static drive mode waveforms
(line inversion mode) . . . . . . . . . . . . . . . . . . . . . .25
Fig 17. Waveforms for the 1:2 multiplex drive mode
with 12 bias (line inversion mode) . . . . . . . . . . . .26
Fig 18. Waveforms for the 1:2 multiplex drive mode
with 13 bias (line inversion mode) . . . . . . . . . . . .27
Fig 19. Waveforms for the 1:4 multiplex drive mode
with 13 bias (line inversion mode) . . . . . . . . . . . .28
Fig 20. Waveforms for 1:6 multiplex drive mode
with 13 bias (line inversion mode) . . . . . . . . . . . .29
Fig 21. Waveforms for 1:6 multiplex drive mode
with 14 bias (line inversion mode) . . . . . . . . . . . .30
Fig 22. Waveforms for 1:8 multiplex drive mode
with 14 bias (line inversion mode) . . . . . . . . . . . .31
Fig 23. Waveforms for 1:8 multiplex drive mode
with 14 bias (frame inversion mode) . . . . . . . . . .32
Fig 24. VLCD generation including temperature
compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Fig 25. VLCD programming of PCA9620 (assuming
VT[7:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Fig 26. Charge pump model (used to characterize the
driving strength). . . . . . . . . . . . . . . . . . . . . . . . . .35
Fig 27. Power efficiency of the charge pump . . . . . . . . . 36
Fig 28. Temperature measurement block with digital
temperature filter. . . . . . . . . . . . . . . . . . . . . . . . . 37
Fig 29. Temperature measurement delay . . . . . . . . . . . . 38
Fig 30. Example of segmented temperature coefficients 39
Fig 31. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . 43
Fig 32. Display RAM filling order in static drive mode. . . 44
Fig 33. Discarded bits and data pointer wrap around
at the end of data transmission. . . . . . . . . . . . . . 45
Fig 34. Display RAM filling order in 1:2 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Fig 35. Data pointer wrap around in 1:2 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Fig 36. Display RAM filling order in 1:4 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Fig 37. Data pointer wrap around in 1:4 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Fig 38. Display RAM filling order in 1:6 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fig 39. Data pointer wrap around in 1:6 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fig 40. Display RAM filling order in 1:8 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fig 41. Data pointer wrap around in 1:8 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Fig 42. Example of bank selection in 1:4 multiplex
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig 43. Example of the input-bank-select and the
output-bank-select command with multiplex
drive mode 1:4 . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig 44. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Fig 45. Definition of START and STOP conditions . . . . . 51
Fig 46. System configuration. . . . . . . . . . . . . . . . . . . . . . 52
Fig 47. Acknowledgement on the I2C-bus. . . . . . . . . . . . 52
Fig 48. I2C-bus protocol write mo de . . . . . . . . . . . . . . . . 53
Fig 49. Control byte format . . . . . . . . . . . . . . . . . . . . . . . 54
Fig 50. I2C-bus protocol read mode . . . . . . . . . . . . . . . . 54
Fig 51. Device protection diagram . . . . . . . . . . . . . . . . . 55
Fig 52. Typical VLCD with respect to temperature . . . . . . 59
Fig 53. Typical IDD1 with respect to temperature. . . . . . . 59
Fig 54. Typical IDD2 with respect to temperature. . . . . . . 60
Fig 55. Typical ILCD with respect to temperature. . . . . . . 60
Fig 56. Driver timing waveforms . . . . . . . . . . . . . . . . . . . 62
Fig 57. I2C-bus timing waveforms. . . . . . . . . . . . . . . . . . 62
Fig 58. Package outlin e SOT315-1 (LQFP8 0) . . . . . . . . 63
Fig 59. Bare die outline of PCA9620. . . . . . . . . . . . . . . . 64
Fig 60. Alignment mark. . . . . . . . . . . . . . . . . . . . . . . . . . 67
Fig 61. Wafer layout of PCA9620 . . . . . . . . . . . . . . . . . . 68
Fig 62. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PCA9620 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 3 July 2013 80 of 81
continued >>
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
27. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Functional description . . . . . . . . . . . . . . . . . . . 7
8.1 Commands of PCA9620. . . . . . . . . . . . . . . . . . 7
8.1.1 Command: initialize . . . . . . . . . . . . . . . . . . . . . 7
8.1.2 Command: OTP-refresh . . . . . . . . . . . . . . . . . . 8
8.1.3 Command: osci llator-ctrl. . . . . . . . . . . . . . . . . . 8
8.1.4 Command: charge-pump-ctrl . . . . . . . . . . . . . . 9
8.1.5 Command: temp-msr-ctrl . . . . . . . . . . . . . . . . . 9
8.1.6 Command: set-VPR-MSB and set-VPR-LSB . . 9
8.1.7 Command: display-enable . . . . . . . . . . . . . . . 10
8.1.8 Command: set-MUX-mode. . . . . . . . . . . . . . . 10
8.1.9 Command: set-bias-mode . . . . . . . . . . . . . . . 10
8.1.10 Command: load-data-pointer . . . . . . . . . . . . . 10
8.1.11 Command: frame-frequency. . . . . . . . . . . . . . 11
8.1.12 Bank select commands . . . . . . . . . . . . . . . . . 12
8.1.12.1 Command: input-bank-select . . . . . . . . . . . . . 12
8.1.12.2 Command: output-bank-select . . . . . . . . . . . . 12
8.1.13 Command: write-RAM-data . . . . . . . . . . . . . . 13
8.1.14 Command: temp-read . . . . . . . . . . . . . . . . . . . 13
8.1.15 Command: invmode_CPF_ctrl . . . . . . . . . . . . 13
8.1.16 Command: temp-filter. . . . . . . . . . . . . . . . . . . 14
8.2 Possible display configurations . . . . . . . . . . . 14
8.3 Start-up and shut-down. . . . . . . . . . . . . . . . . . 16
8.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 16
8.3.2 Recommended start-up sequences . . . . . . . . 18
8.3.3 Recommended power-down sequences . . . . 20
8.4 LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.4.1 LCD voltage selector . . . . . . . . . . . . . . . . . . . 22
8.4.1.1 Electro-optical performance . . . . . . . . . . . . . . 24
8.4.2 LCD drive mode waveforms . . . . . . . . . . . . . . 25
8.4.2.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 25
8.4.2.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 26
8.4.2.3 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 28
8.4.2.4 1:6 Multiplex drive mode. . . . . . . . . . . . . . . . . 29
8.4.2.5 1:8 Multiplex drive mode. . . . . . . . . . . . . . . . . 31
8.4.3 VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 33
8.4.4 External VLCD supply . . . . . . . . . . . . . . . . . . . 34
8.4.5 Charge pump driving capability . . . . . . . . . . . 35
8.4.6 Charge pump frequency settings and power
efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4.7 Temperature readout . . . . . . . . . . . . . . . . . . . 37
8.4.8 Temperature compensation of VLCD. . . . . . . . 38
8.5 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5.1 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . 40
8.5.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5.3 Timing and frame frequency . . . . . . . . . . . . . 41
8.6 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 41
8.7 Segment outputs . . . . . . . . . . . . . . . . . . . . . . 42
8.8 Display register . . . . . . . . . . . . . . . . . . . . . . . 42
8.9 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.9.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.9.1.1 RAM filling in static drive mode . . . . . . . . . . . 44
8.9.1.2 RAM filling in 1:2 multiplex drive mode . . . . . 45
8.9.1.3 RAM filling in 1:4 multiplex drive mode . . . . . 45
8.9.1.4 RAM filling in 1:6 multiplex drive mode . . . . . 46
8.9.1.5 RAM filling in 1:8 multiplex drive mode . . . . . 47
8.9.2 Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.2.1 Input-bank-select . . . . . . . . . . . . . . . . . . . . . . 49
8.9.2.2 Output-bank-select. . . . . . . . . . . . . . . . . . . . . 50
9 I2C-bus interface characteristics. . . . . . . . . . 51
9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.2 START and STOP conditions. . . . . . . . . . . . . 51
9.3 System configuration . . . . . . . . . . . . . . . . . . . 51
9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.5 I2C-bus controller. . . . . . . . . . . . . . . . . . . . . . 53
9.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.7 I2C-bus slave address . . . . . . . . . . . . . . . . . . 53
9.8 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 53
10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 55
11 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 56
13 Static characteristics . . . . . . . . . . . . . . . . . . . 57
14 Dynamic characteristics. . . . . . . . . . . . . . . . . 61
15 Test information . . . . . . . . . . . . . . . . . . . . . . . 62
15.1 Quality information. . . . . . . . . . . . . . . . . . . . . 62
16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 63
17 Bare die outline. . . . . . . . . . . . . . . . . . . . . . . . 64
18 Packing information . . . . . . . . . . . . . . . . . . . . 68
18.1 Wafer information. . . . . . . . . . . . . . . . . . . . . . 68
19 Soldering of SMD packages. . . . . . . . . . . . . . 70
19.1 Introduction to soldering. . . . . . . . . . . . . . . . . 70
19.2 Wave and reflow soldering. . . . . . . . . . . . . . . 70
19.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 70
NXP Semiconductors PCA9620
60 x 8 LCD high-drive segment driver for automotive and industrial
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 July 2013
Document identifier: PCA9620
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 71
20 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 73
21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
22 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 75
23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 76
23.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 76
23.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
23.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 76
23.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 77
24 Contact information. . . . . . . . . . . . . . . . . . . . . 77
25 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
26 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80