ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 1 -
GENERAL DESCRIPTION
The AK4122 is a digital sample rate converter (SRC) with the digital audio receiver (DIR). The input
sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. By
using the AK4 122, the system can take very simple configuration because the AK4122 has an inte rnal
PLL and does not need any master clock at slave mode. Then the AK4122 is suitable for the appli cation
interfacing to different sample rates like Car Audio, DVD recorder, etc.
FEATURES
1. SRC
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi) : 8kHz ∼ 96kHz
• Output Sample Rate (fso) : 32kHz, 44.1kHz, 48kHz, 96kHz
• Input to Output Sample Rate Ratio : 0.33 to 6
• THD+N : −113dB
• I/F format : MSB justified, LSB justified (16/24bit) and I2S compatible
• Clock for Master mode : 256/384/512/768fs
• SRC Bypass mode
• Soft Mute Function
2. DIR • 4-Channel Inputs Selector & 1-Channel Through Output
• AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatib le
• Low Jitter Analog PLL
• PLL Lock Range : 32kHz ∼ 96kHz
• Auto detection
- Non-PCM Bit Stream
- DTS-CD Bit Stream
- Validity Flag
- Sampling F r equency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz)
- Unlock & Parity Error
- DAT Start ID
• 40-bit Channel Status Buffer
• Burst Preamble bit Pc, Pd Buffer for Non-PCM bit streams
• Q-subcode Buffer for CD bit streams
3. 4-w ire Serial µP Interface
4. Power Supply
• AVDD: 3.0 ∼ 3.6V (typ. 3.3V)
• DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
5. Ta = −10 ∼ 70°C
6. Package : 48pin LQFP
24-Bit 96kHz SRC with DIR
AK4122
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 2 -
Block Diagram
RX2
RX2
PDN
RX1 RX1
IPS1-0
Serial
Audio
I/F
LRCK1
SDTI
LRCK1
SDTI
BICK1 BICK1
Serial
Audio
I/F
LRCK2
SDTIO
LRCK2
SDTIO
BICK2 BICK2
MCLK2
LRCK
BICK
SDTO
LRCK
BICK
SDTO
OMCLK
SMUTE
Control Register
CDTO CDTI CCLK CSNAVDD AVSS DVDD DVSS
M/S2
M/S3
SRC
PLL
Serial
Audio
I/F
De-em
Filter
PORT1
PORT2
PORT3
RX3
RX3 RX4
RX4
DIR
TX TX
ISEL1-0
OSEL
BYPS
INT0 INT1 RFILTINT2
OPS1-0
Block diagram
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 3 -
Ordering Guide
AK4122VQ −10 ∼ +70°C 48pin LQFP (0.5mm pitch)
AKD4122 Evaluation Board for AK4122
Pin Layout
CDTI
CCLK
48 47
146 45 44 43 42 41 40 39 38 36
35
34
33
32
31
30
29
28
27
26
2322212019181716151413
2
3
4
5
6
7
8
9
10
11
AK4122VQ
Top View
CDTO
TST1
INT2
TST2
TST3
M/S2
M/S3
SMUTE
TST4
TST5 AVSS
PDN
LRCK1
BICK1
SDTI
DVSS
DVDD
MCLK2
LRCK2
BICK2
SDTIO
CSN
BVSS
DVDD
DVSS
OMCLK
LRCK
BICK
SDTO
TX
INT1
12FILT 24 25 R
37
INT0
TST6
AVDD
AVSS
RX1
TST7
RX2
TST8
RX3
TST9
RX4
TST10
TST11
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 4 -
PIN/FUNCTION
No. Pin Name I/O Function
1 CDTI I Control Data Input Pin
2 CDTO O Control Data Output Pin
3 TST1 O Test 1 Pin
4 INT2 O Interrupt 2 Pin
5 TST2 O Test 2 Pin
6 TST3 I Test 3 Pin
This pin should be connected to DVSS.
7 M/S2 I Master / Slave Mode Pin for PORT2
“H” : Master mode, “L” : Slave Mode
8 M/S3 I Master / Slave Mode Pin for PORT3
“H” : Master mode, “L” : Slave Mode
9 SMUTE I Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
10 TST4 I Test 4 Pin
This pin should be connected to AVSS.
11 TST5 I Test 5 Pin
This pin should be connected to AVSS.
12 FILT O PLL Loop Filter Pin
470Ω±5% resistor and 2.2µF±50% ceramic capacitor in parall el with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
13 AVSS - Analog Ground Pin
14 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V
15 TST6 I Test 6 Pin
This pin should be connected to AVSS.
16 RX1 I Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biase d Pin)
17 TST7 I Test 7 Pin
This pin should be connected to AVSS.
18 RX2 I Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
19 TST8 I Test 8 Pin
This pin should be connected to AVSS.
20 RX3 I Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biase d Pin)
21 TST9 I Test 9 Pin
This pin should be connected to AVSS.
22 RX4 I Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
23 TST10 I Test 10 Pin
This pin should be connected to AVSS.
24 TST11 O Test 11 Pin
Note: All input pins except internal biased pins should not be left floating.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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25 R - External Resistor Pin
12kΩ±5% resistor should be connected to AVSS externally.
26 AVSS - Analog Ground Pin
27 PDN I Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
28 LRCK1 I Input Channel Clock Pin
29 BICK1 I Audio Serial Data Clock Pin
30 SDTI I Audio Serial Data Input Pin
31 DVSS - Digital Ground Pin
32 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
33 MCLK2 I Master Clock Input Pin
34 LRCK2 I/O Input / Output Channel Clock Pin
35 BICK2 I/O Audio Serial Data Clock Pin
36 SDTIO I/O Audio Serial Data Input / Output Pin
37 INT0 O Interrupt 0 Pin
38 INT1 O Interrupt 1 Pin
39 TX O Transmitter Output Pin
40 SDTO O Audio Serial Data Output Pin
41 BICK I/O Audio Serial Data Clock Pin
42 LRCK I/O Output Channel Clock Pin
43 OMCLK I Master Clock Input Pin
44 DVSS - Digital Ground Pin
45 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
46 BVSS - Substrate Ground Pin
This pin should be connected to AVSS.
47 CSN I Chip Select Pin
48 CCLK I Control Data Clock Pin
Note: All input pins except internal biased pins should not be left floating.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below.
Classification Pin Name Setting
PORT1 BICK1, LRCK1, SDTI These pins should be connected to DVSS.
MCLK2 This pin should be connected to DVSS.
BICK2, LRCK2 These pins should be connected to DVSS in slave mode
or
open in master mode.
SDTIO This pin should be connected to DVSS.
PORT2
M/S2 This pin should be connected to DVDD or DVSS.
OMCLK This pin should be connected to DVSS.
BICK, LRCK These pins should be connected to DVSS in slave mode
or open in master m ode.
SDTO This pin should be open.
PORT3
M/S3 This pin should be connected to DVDD or DVSS.
RX1, RX2, RX3, RX4 These pins should be open.
DIR INT0, INT1, INT2, TX These pins should be open.
CSN, CCLK, CDTI These pins should be connected to DVSS.
Control PORT CDTO This pin should be open.
Other SMUTE This pin should be connected to DVSS.
TST1, TST2, TST11 These pins should be open.
TST3 This pin should be connected to DVSS.
TEST TST4, TST5, TST6, TST7,
TST8, TST9, TST10 These pins should be connected to AVSS.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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ABSOLUTE MAXIMUM RATINGS
(AVSS, BVSS, D VS S=0 V ; Note 1 )
Parameter Symbol min max Units
Power Supplies:
Analog
Digital
|BVSS − DVSS| (Note 2)
AVDD
DVDD
∆GND
−0.3
−0.3
-
4.6
4.6
0.3
V
V
V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage 1 (Except RX1-4 pins) VIND1 −0.3 DVDD+0.3 V
Digital Input Voltage 2 (RX1-4 pins) VIND2 −0.3 AVDD+0.3 V
Ambient Temperature (Power applied) Ta −10 70 °C
Storage Temperature Tstg −65 150 °C
Note 1. All voltages with respect to ground.
Note 2. AVSS, BVSS and DVSS m ust be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDE D OPER ATING CONDITIONS
(AVSS, BV SS, DVSS=0V; Note 1 )
Parameter Symbol min typ max Units
Power Supplies
(Note 3) Analog
Digital AVDD
DVDD 3.0
3.0 3.3
3.3 3.6
AVDD V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD and DVDD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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SRC CHARAC TERIST I CS
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=BVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2;
unless otherwise specified.)
Parameter Symbol min typ max Units
SRC Characteristics:
Resolution (Note 4) 24 Bits
Input Sample Rate FSI 8 96 kHz
Output Sample Rate FSO 32 96 kHz
THD+N (Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 32kHz/48kHz
FSO/FSI = 96kHz/32kHz
Worst Case (FSO/FSI = 48kHz/8kHz)
-
-
-
-
-
−113
−113
−114
−111
-
-
-
-
-
−103
dB
dB
dB
dB
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 32kHz/48kHz
FSO/FSI = 96kHz/32kHz
Worst Case (FSO/FSI = 32kHz/44.1kHz)
Dynami c R ange (Input = 1kHz, −60dBFS, A-weighted, Note 5)
FSO/FSI = 44.1kHz/48kHz
-
-
-
-
112
-
114
115
115
116
-
117
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Ratio between Input and Output Sample Rate (Note 6) FSO/FSI 0.33 6 -
Note 4. Input data for SRC corresponds to 24bit data. When LSB 4bit data is input, the AK4122 calculates as “0” data
because SRC is 20bit calculation. Therefore, SRC outputs “0” data.
Note 5. Measured by ROHDE & SCHWARZ UPD04, Rejection Filt er = wide, 8192point FFT.
Note 6. The “0.33” is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz. The “6” is the ratio of FSO/FSI
when FSI is 8kHz and FSO is 48kHz.
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
Input Resistance Zin - 10 - kΩ
Input Voltage VTH 200 mVpp
Input Sample Frequency fs 32 - 96 kHz
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; DEM=OFF)
Parameter Symbol min typ max Units
Digital Filter 0.985 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz
0.905 ≤ FSO/FSI < 0.985 PB 0 0.4167FSI kHz
0.714 ≤ FSO/FSI < 0.905 PB 0 0.3195FSI kHz
0.656 ≤ FSO/FSI < 0.714 PB 0 0.2852FSI kHz
0.536 ≤ FSO/FSI < 0.656 PB 0 0.2245FSI kHz
0.492 ≤ FSO/FSI < 0.536 PB 0 0.2003FSI kHz
0.452 ≤ FSO/FSI < 0.492 PB 0 0.1781FSI kHz
Passband −0.001dB
0.333 ≤ FSO/FSI < 0.452 PB 0 0.1092FSI kHz
0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz
0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz
0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz
0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz
0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz
0.492 ≤ FSO/FSI < 0.536 SB 0.2732FSI kHz
0.452 ≤ FSO/FSI < 0.492 SB 0.2510FSI kHz
Stopband
0.333 ≤ FSO/FSI < 0.452 SB 0.1822FSI kHz
Passband Ripple PR ±0.01 dB
Stopband Attenuation SA 96 dB
Group Delay (Note 7) GD - 58.5 - 1/fs
Note 7. This value is t he time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output,
when LRCK for Output data corresponds with LRCK for Input.
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 70%DVDD
- -
- -
30%DVDD V
V
High-Level Output Voltage (Iout=−400µA)
Low-Level Output Voltage (Iout=400µA) VOH
VOL DVDD−0.4
- -
- -
0.4 V
V
Input Leakage Current Iin - - ±10 µA
Parameter min typ max Units
Power Supply Current
Normal operation (PDN pin = “H”) (Note 8)
FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V
FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.3V
FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.6V
Power down (PDN pin = “L”) (Note 9)
AVDD+DVDD
15
29
-
10
-
-
45
100
mA
mA
mA
µA
Note 8. Typ and max values are the value of AVDD+DVDD in each power supply voltage.
Power supply current of each path@Slave Mode, AVDD= DVDD=3.3V, FSI=FSO=48kHz
1. PORT1 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ)
2. PORT2 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ)
3. DIR → SRC → PORT3: AVDD=6mA(typ), DVDD=9mA(typ)
Note 9. All digital input pins are held DVSS .
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
8.192
0.4/fCLK
0.4/fCLK
36.864
MHz
ns
ns
LRCK for Input data (LRCK1, LRCK2)
Frequency
Duty Cycle
fs
Duty
8
48
50
96
52
kHz
%
LRCK for Output data (LRCK, LRCK2)
Frequency (Note 10)
Duty Cycle Slave Mode
Master Mode
fs
Duty
Duty
32
48
50
50
96
52
kHz
%
%
S/PDIF Clock Recover Frequ e ncy fPLL 32 96 kHz
Audio Interface Timing
Input for PORT1
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑” (Note 11)
BICK1 “↑” to LRCK1 Edge (Note 11)
SDTI Hold Time from BICK1 “↑”
SDTI Setup Time to BICK1 “↑”
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Input for PORT2 (Slave mode)
BICK2 Period
BICK2 Pulse Width Low
Pulse Width High
LRCK2 Edge to BICK2 “↑” (Note 11)
BICK2 “↑” to LRCK2 Edge (Note 11)
SDTIO Hold Time from BICK2 “↑”
SDTIO Setup Time to BICK2 “↑”
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Output for PORT2 (Slave mode)
BICK2 Period
BICK2 Pulse Width Low
Pulse Width High
LRCK2 Edge to BICK2 “↑” (Note 11)
BICK2 “↑” to LRCK2 Edge (Note 11)
LRCK2 to SDTIO (MSB) (Except I2S mode)
BICK2 “↓” to SDTIO
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Note 10. Min value is 8kHz at BYPASS mode.
Note 11. BICK1 rising edge must not occur at the same time as LRC K1 edge.
BICK2 rising edge must not occur at the same ti me as LRCK2 edge.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Parameter Symbol min typ max Units
Output for PORT3 (Slave mode)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BI CK “↑” (Note 11)
BICK “↑” to LRCK Edge (Note 11)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fs
65
65
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
Output for PORT2 (Mast er mode)
BICK2 Frequency
BICK2 Duty
BICK2 “↓” to LRCK2
BICK2 “↓” to SDTIO
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
30
Hz
%
ns
ns
Output for PORT3 (Mast er mode)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
30
Hz
%
ns
ns
Contr o l Interfac e Tim in g
CCLK Period (Note 12)
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
1000
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 13)
tPD
150
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. In case of using INT2. When INT2 is not used, the max value is not limited.
Note 13. The AK4122 can be reset by bringing the PDN pin = “L”.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Timing Diagram
1/fCLK
MCLK
tCLKH tCLKL
VIH
VIL
1/fs
LRCK VIH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
Clock Timing
LRCK VIH
VIL
tBLR
BICK VIH
VIL
tLRS
SDTO 50%DVDD
tLRB
tBSD
tSDS
SDTI VIL
tSDH
VIH
Audio Interface Timing (Slave mode)
Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK show s LRCK1 of PORT1,
LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as
input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as out put port.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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LRCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI VIL
tSDH
VIH
tMBLR dBCK
50%DVDD
Audio Interface Timing (Master mode)
Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK show s LRCK1 of PORT1,
LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as
input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as out put port.
CSN VIH
VIL
tCSS
CCLK
tCDS
VIH
VIL
CDTI VIH
tCCKHtCCKL
tCDH
VIL
C1 C0 R/W
CDTO Hi-Z
WRITE/READ Command Input Timing
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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CSN VIH
VIL
tCSH
CCLK VIH
VIL
CDTI VIH
tCSW
VIL
D1 D0
CDTO Hi-Z
D2
WRITE Data Input Tim ing
CSN VIH
VIL
CCLK VIH
VIL
CDTI VIH
VIL
A0
CDTO
A1
50%DVDD
tDCD
D7 D6
Hi-Z
READ Data Output Timing 1
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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CSN VIH
VIL
tCSH
CCLK VIH
VIL
CDTI VIH
tCSW
VIL
CDTO 50%DVDDD2 D1 D0
tCCZ
Hi-Z
READ Data Output Timing 2
tPD
PDN VIL
Power Down & Reset Timing
ASAHI KASEI [AK4122]
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OPERATION OVERVIEW
Internal Signal Path
The input source of the SRC can be switched bet ween the outputs of the DIR, PORT1 or PORT2. The input source of t he
PORT2 and PORT3 can be switched between the outputs of the SRC or BYPASS. When PORT2 is used as input port,
PORT2 cannot use as output port. The signal path should be controlled during PWN bit = “0”. The Switch Names
(ISEL1-0 bits etc) in Figure 1 correspond to the register bits that control the switch function. Refer to Table 1.
Serial
Audio
I/F
Serial
Audio
I/F
PORT1
PORT2
DIR
ISEL1-0 SRC
PLL
Serial
Audio
I/F
De-em
Filter
PORT3
OSEL
BYPS
Figure 1. Connection Input Source & Output Source
Input PORT SRC / Bypass Output PORT
Mode ISEL1-0 bit BYPS bit OSEL bit Path
0 00 : PORT1 PORT1 → SRC → PO RT3
1 01 : PORT2 PORT2 → SRC → PO RT3
2 10 : DIR 0 : SRC DIR → SRC → PORT3
3 00 : PORT1 PORT1 → PORT3
4 01 : PORT2 PORT2 → PORT3
5 10 : DIR 1 : Bypass
0 : PORT3
(Note 1)
DIR → PORT3
6 00 : PORT1 PORT1 → SRC → PO RT2
7 10 : DIR 0 : SRC DIR → SRC → PORT2
8 00 : PORT1 PORT1 → PORT2
9 10 : DIR 1 : Bypass
1 : PORT2
(Note 2) DIR → PORT2
Table 1. Path Select
Default is Mode 0. (Pat h : PORT1 → SRC → PORT3)
After PDN pin = “L” → “H”, SDTIO pin of PORT2 is the input pin.
The DIF1-0 bits of the PORT1 should be set a value except “10” (I2S Compatible) when the DIR is
selected as an input port.
Refer to Table 6 and 7 for Master/Slave mode setting.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Note 1. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately
by Table 2.
M/S2 pin Mode Unused pin Pin I/O Setting
MCLK2 I This pin should be connected to DVSS.
BICK2 I This pin should be connected to DVSS.
LRCK2 I This pin should be connected to DVSS.
L Slave
SDTIO I This pin should be connected to DVSS.
MCLK2 I This pin should be connected to DVSS.
BICK2 O This pin should be open.
LRCK2 O This pin should be open.
H Master
SDTIO I This pin should be connected to DVSS.
Table 2. Pin Sett ing for PORT2
Note 2. In this case, PORT3 is output port. If PORT 3 is unused, the digital I/O pins should be processed appropriately
by Table 3.
M/S3 pin Mode Unused pin Pin I/O Setting
OMCLK I This pin should be connected to DVSS.
BICK I This pin should be connected to DVSS.
LRCK I This pin should be connected to DVSS.
L Slave
SDTO O This pin should be open.
OMCLK I This pin should be connected to DVSS.
BICK O This pin should be open.
LRCK O This pin should be open.
H Master
SDTO O This pin should be open.
Table 3. Pin Sett ing for PORT3
System Clock
PORT1 can be operated in slave mode only. PORT2 and PORT3 work in master mode and slave mode. Internal system
clock is created by internal PLL using LRCK1, LRCK2 or LRCK of DIR. The MCLK is not needed when PORT2 and
PORT3 are in slave mode and then please set MCLK2 pin and OMCLK pin to DVSS. However, when PORT2 and
PORT3 are used in mast er mode, MCLK2 pin and OMCLK pin should be supplied to MCLK. The M/S2 pin and M/S3
pin select between ma ster and slave mode. Table 4 and 5 show set ting of MCLK frequency that PORT2 and PORT3 are
master m ode. In case of detecti ng the sampling frequency by MCLK when DIR is use d, MCLK (MCLK2 or OMCLK) of
selected output port (PORT2 or PORT3) should be input.
MCLK2
ICKS1 ICKS0
32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0 0 256fs 256fs
0 1 384fs 384fs
1 0 512fs N/A
1 1 768fs N/A
Default
Table 4. MCLK2 frequency se lect for Master mode
OMCLK
OCKS1 OCKS0 32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0 0 256fs 256fs
0 1 384fs 384fs
1 0 512fs N/A
1 1 768fs N/A
Default
Table 5. OMCLK frequency sel ect for Master mode
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 18 -
Master Mode and Slave Mo de
When PORT2 and PORT3 are used as out put port , the M / S2 pin and M / S3 pin select ei ther master or slave m ode. “H” is
master mode, “L” is slave mode. In master mode, MCLK should be input and the AK4122 outputs BICK and LRCK. In
slave mode, BICK and LRCK are input externally and MCLK is not needed. If PORT2 is used as input port, M/ S2 pin
should be set “H” or “L”.
M/S2 pin BYPS bit Data I/O Mode BICK, LRCK
L 0 I/O Slave, SRC
Input Available
L 1
Output Not Available Input
H 0 I/O Master, SRC
H 1 I/O Master, Bypass Output
Table 6. Master mode/Slave mode for PORT2
M/S3 pin BYPS bit Data I/ O Mode BICK, LRCK
L 0 Output Slave, SRC
L 1 Output Not Available
Input
H 0 Output Master, SRC
H 1 Output Master, Bypass Output
Table 7. Master mode/Slave mode for PORT3
Audio Interface Format
The audio i nte rfa ce should be controll ed during PWN bi t = “0”. When i n B YPASS mode, BICK1, B ICK2 a nd B IC K are
fixed to 64fs.
(1) PORT1
Four kinds of data form ats can be chosen with t he DIF1-0 bits (Table 8). In all modes, the serial data is in MSB first, 2’s
compliment format. The SDTI is latched on the rising edge of BICK1. PORT1 corresponds to slave mode only.
Mode DIF1 DIF0 Input Format LRCK BICK
0 0 0 16bit, LSB justified H/L
≥ 32fs
1 0 1 24bit, MSB justified H/L
≥ 48fs
2 1 0 24bit, I2S Compatible L/H ≥ 48fs
3 1 1 24bit, LSB justified H/L
≥ 48fs
Default
Table 8. Audio Interface Format for PORT1
Note: The DIF1-0 bits of the PORT1 should be set a v alue except “10” (I 2S Compatib le) when the DIR is
selected as an input port.
LRCK
BICK(32fs) 01102 3 9 11121314150 123 10109 1112131415
SDTI(i) Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
SDTI-15:MSB, 0:LSB
SDTI(i) 15 14 13 7654321015 14 13 1576543210
BICK(64fs) 01182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 2. Mode 0 Timing
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 19 -
LRCK
BICK(64fs) 01220212431012 102220 21 312422 23 23
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 231234
Figure 3. Mode 1 Timing
LRCK
BICK(64fs) 0122521 24 0 12 1022 2521 2422 23 233
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
432123 22 23 22 1234
Figure 4. Mode 2 Timing
LRCK
BICK(64fs) 0 1 22431012 10312489 89
SDTI(i) Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 5. Mode 3 Timing
(2) PORT2
Four kinds of data format s can be chosen with the IDIF1-0 bit s (Table 9). In all modes, the serial data is in MSB first, 2’s
compliment format. If PORT 2 is selected the output port , the SDTIO is clocked out on the falling edge of BICK2, and if
PORT2 is selected the input port, the SDTIO is latched on the rising edge of BICK2. The audio interface supports both
master a nd slave m ode s. In m aste r mode, BICK 2 and LRC K2 are output wi th t he BICK2 freque ncy fixed t o 64fs and the
LRCK2 frequency fi xed to 1fs.
Mode IDIF1 IDIF0 Output Format Input Format LRCK BICK
0 0 0 24bit, MSB justified 16bit, LSB justified H/L ≥ 32fs
1 0 1 24bit, MSB justified 24bit, MSB justified H/L ≥ 48fs
2 1 0 24bit, I2S Compatible 24bit, I2S Compatible L/H ≥ 48fs
3 1 1 24bit, MSB justified 24bit, LSB justified H/L ≥ 48fs
Default
Table 9. Audio Interface Format for PORT2
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 20 -
LRCK
BICK(32fs)
SDTIO(o)
SDTIO(i)
0
23 22
15 14
110
21
13
23
15
76543210
14 13 12 11 9810
9 11121314150 123
23 22 21
15 14 13
15 14 13 12 11 9810
10
23
1576543210
109 1112131415
BICK(64fs) 011823 1920 310123 1018 19 20 31
SDTIO(o)
SDTIO(i)
23 22 21
Don't Care 10
7 23 22 21
15 14 13
23
210
17
6543
15 14 13 12
76543
17
12Don't Care
SDTIO-23:MSB, 0:LSB
SDTIO-15:MSB, 0:LSB
Lch Data Rch Data
Figure 6. Mode 0 Timing
LRCK
BICK(64fs)
SDTIO(o)
SDTIO(i)
0
23 22
Don't Care
12
4
0
0
20 21 24 31 0 12
23 22 0
10
23
0
2220 21 31
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
24
321
432123 22
22 23
23 22 23
23
1234
1234
Figure 7. Mode 1 Timing
LRCK
BICK(64fs)
SDTIO(o)
SDTIO(i)
0
23 22
Don't Care
12
4
0
0
2521 24 0 12
23 22 0
10
0
22 2521
23:MSB, 0:LSB
Lch Data Rch Data
Don't Care
24
321
432123 22
22 23
23 22
23
1234
1234
3
Figure 8. Mode 2 Timing
LRCK
BICK(64fs)
SDTIO(o)
SDTIO(i)
0
23 22
Don't Care
12
16
0
15 0
24 31 0 12
23 22 16 15 0
10
23
810
31
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 23
2489
1
89
Figure 9. Mode 3 Timing
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 21 -
(3) PORT3
Two kinds of data formats can be chosen with the ODIF bit (Table 10). In both modes, t he seri al data is in MSB first, 2’s
complim ent form at. The SDTO is clocked out on the fal ling edge of BIC K. The a udio inte rface supports both m ast er and
slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode ODIF Output Format LRCK BICK
0 0 24bit, MSB justified H/L ≥ 48fs
1 1 24bit, I2S Compat ib le L/H ≥ 48fs
Default
Table 10. Audio Interface Format for PORT3
LRCK
BICK(64fs) 01182 3 19 20 31 0 1 2 3 1018 19 20 31
SDTO(o) 23 22 21 7 23 22 21 23
17
6543 76543
17
SDTO-23:MSB, 0:LSB
Lch Data Rch Data
Figure 10. Mode 0 Timing
LRCK
BICK(64fs)
SDTO(o)
0
23 22
12
4 0
2521 24 0 12
23 22 0
1022 2521 24
321
22 23 23
1234
3
23:MSB, 0:LSB
Lch Data Rch Data
Figure 11. Mode 1 Timing
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Soft Mute Operation
Soft mute operation is performed in the digital domain of the SRC output. S oft mute can be controlled by SMUTE bit or
SMUTE pin. The SMUTE bit and SMUTE pin are ORed between pin and register. When SMUTE bit goes “1” or
SMUTE pin goes “H”, the S RC output data is attenuate d by −∞ within 1024 LRCK cycl es. When the SMUTE bit returned
“0” and SMUTE pin goes “L” the mut e is cancelled and the output attenuation gradually changes to 0dB during 1024
LRCK cycl es. If the soft m ute is cancel led before mut e state after starting of t he operation, the attenuation is discontinued
and returned to 0dB by the same cy cles. The soft mute is effective for changing the signal source.
SMUTE
A
ttenuation
DA TT Level
-∞GD GD
(1)
(2)
(3)
SDTIO / SDT O
Figure 12. Soft Mute Function
(1) The output data is attenuated by −∞ during 1024 LRCK cycles (1024/fs).
(2) Digital output delay from the digital input is called the group delay (GD).
(3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuat ion is discontinued and
returned to 0dB by the same number of clock cycles.
ASAHI KASEI [AK4122]
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De-emphasis Filter Control
The AK4122 includes the digi tal de-emphasis filter (t c=50/15µs) by IIR filter corresponding to three sampling
frequencies (32kHz, 44.1kHz and 48kHz).
(1) When input port is DIR
When the input port is DIR and DEAU bit = “1”, the de-emphasis filter is enabled automatically by sampling frequency
(FS3-0 bit) and pre- emphasis information in the channel status. DEM1-0 bits can control the de-emphasis filter when
DEAU bit = “0”. When the de-emphasis filter is OFF, the internal de-emphasis filter is bypassed. When PEM bit = “0”,
the internal de-emphasis filter is always bypassed.
PEM FS3 FS2 FS1 FS0 Mode
1 0 0 0 0 44.1kHz
1 0 0 1 0 48kHz
1 0 0 1 1 32kHz
1 (Others) OFF
0 x x x x OFF
Table 11. De-emphasis Auto Control (DEAU bit = “1”)
PEM DEM1 DEM0 Mode
1 0 0 44.1kHz
1 0 1 OFF Default
1 1 0 48kHz
1 1 1 32kHz
Table 12. De-emphasis Manual Control (DEAU bit = “0”)
(2) When input port is PORT1 or PORT2
When PORT1 or PORT2 is sele cted as input port, DEM1-0 bit s can control the de-em phasis filter even if DEAU bi t = “0”
or DEAU bit = “1” . In thi s ca se, the de -emphasis filter cannot enabl e a utomatically. When the de -emphasis filter is OFF,
the internal de-emphasis filter is bypassed.
DEM1 DEM0 Mode
0 0 44.1kHz
0 1 OFF Default
1 0 48kHz
1 1 32kHz
Table 13. De-emphasis Manual Control
System Reset and Power-Down
The AK4122 has a full power-down mode for a ll circuits that i s activated by the PDN pi n, and a partial power-down m ode
activated by the PWN bit. The AK4122 should be reset once at power-up by bringing PDN pin = “L”.
PDN pin:
All analog and digit a l circuits are placed in power-down and reset modes by bringing PDN pin = “L”. All the
registers are initialized and clocks are stopped. Read/Write operations to the registers are disabled.
PWN bit (Address 00H; D0):
Unlike the PDN pin operation described above, internal registers and mode settings are not initialized. Read/Write
operations to the registers are enabled.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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System Reset
Bringing the PDN pin = “L” sets the AK4122 power-down mode and initializ es th e di gita l fi lte r. When P DN p in = “L ”,
the SDTO output is “L”. The AK4122 should be reset once by bringing PDN pin = “L” upon power-up. The SDTO is
valid from less than 100ms after the rising of PDN after clocks are supplied, and until then, outputs “L”. After the rising
of PDN pin, the SDTIO pin is input pin.
External clocks
(input / output port)
SDTO
(internal state)
PDN
don’t care (stable) don’t care
Power-down normal operat ion
PLL lock time & fs detection
“0” dat a
< 100msec
normal data
Power-down
“0” dat a
Figure 13. System Reset
Sequence of ch anging clocks
The recommended sequence of changing clocks is shown as Figure 14. The internal reset is executed when the input or
the output clocks are changed. The SDTO is placed “0” during reset. Within 100ms, the SDTO outputs normal data.
When the frequency transition occurs gradually without the phase change, the output data may have large distortion for
several seconds. Then, to out put norm al data wit hin 100m s, a reset by PDN pin = “L” or PWN bit = “0” is recomm ended
when clocks are changed.
PLL locktime
& fs detec t ion
Po we r do wn
External clocks
(input port
or output port)
state 1 (44.1kHz)
SDTIO / SDTO
(internal state) normal operation normal operation
state 2 (48kHz)
(unknown)
< 100msec
SMU TE (Note2,
recommended) 1024/fso
A
tt.Level 0dB
-∞dB
normal data normal data
1024/fso
PDN pin or
PWN bit
Note1
Figure 14. Sequence of changing clocks
Note 1. The data on SDTO may cause click noise. If SDTI or SDTIO is “0” from GD before PDN pin goes “L”,
the data on SDTO keeps “0” then no unknown data is output.
Note 2. SMUTE can remove the unknown data.
ASAHI KASEI [AK4122]
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96kHz Clock Recovery
The on-chip, low jitter PLL of DIR has a wide lock range of 32kHz to 96kHz and a lock time of less than 20ms. The
AK4122 has a sampling frequency detect function (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) that uses either clock
comparison against the MCLK2 or OMCLK frequency or the channel status information. The PLL loses lock when the
received sync interval is incorrect.
Biphase Input
Four receiver inputs (RX1-4) of DIR are available. Each input includes an amplifier for unbalance loads that can accept
200mVpp or greater signa l. The IPS1-0 bits select the receiver channe l (Table 14).
IPS1 IPS0 Input Data
0 0 RX1
0 1 RX2
1 0 RX3
1 1 RX4
Default
Table 14. Recovery Data Select
Biphase Output
The AK4122 can output the through data from the digital receiver inputs (RX1-4) to th e TX pin. The OPS1-0 bits can
select the source of the output from the TX pin. TX output can be stopped by TXE bit. AK4122 does not have the TX
output buffer (Line Driver), the TX pin cannot drive the 75Ω coaxial ca b le directly.
OPS1 OPS0 Output Data
0 0 RX1
0 1 RX2
1 0 RX3
1 1 RX4
Default
Table 15. Output Data Select for TX
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Biphase signal input circuit
RX
AK4122
0.1uF
75Ω
Coax 75
Ω
Figure 15. Consumer Input Circui t (Coaxial Input)
Note 1: Coax input only : if a coupling level to this input from the next RX input line pattern exceeds 50mV,
an incorrect operation may occur. In this case, it is possible to lower the coupling level by adding this
decoupling capacitor.
Note 2: Ground of the RCA connector and terminator should be connected to AVSS of the AK4122 with low
impedance on PC board.
RX
AK4122
470
O/E
Optical Receiver
Optical
Fiber
3.3V
Figure 16. Consumer Input Circuit (Optical Input, Using 3.3V Optical Receiver)
When using coaxial input, the input level of the RX line is small. Care must be take n to reduce, crosstalk am ong RX input
lines by inserting a shield pattern between them.
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Sampling Frequency and Pre-emphasis Detection
The AK4122 has two methods for detecting the sampling frequency. The sampling frequency is detected by comparing
the recovered clock t o the MCLK2 or OMC LK frequency , and t he det ected fre quency is reporte d on FS3-0 bit s. XTL1-0
bits, ICKS1-0 bits and OCKS1-0 bits can select reference MCLK2 and OMCLK (Table 16). When XTL1-0 bits = “11”,
the sampling frequency is detected by the channel status sampling frequency information. The detected frequency is
reported on FS3-0 bits. The default values of FS3-0 bits are “0001”. In case of detecting t he sampling frequency by
MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of selected output port (PORT2 or PORT3) should be input.
MCLK2 or OMCLK
XTL1 XTL0 ICKS1 / OCKS1 ICKS0 / OCKS0 MCLK Frequency
0 0 11.2896MHz
0 1 22.5792MHz
1 0 16.9344MHz
0 0
1 1 33.8688MHz
0 0 12.288MHz
0 1 24.576MHz
1 0 18.432MHz
0 1
1 1 36.864MHz
0 0 24.576MHz
0 1 N/A
1 0 36.864MHz
1 0
1 1 N/A
1 1 - - Use channel status Default
Table 16. Reference MC LK Freque ncy
Except XTL1-0 bit = “11” XTL1-0 bit = “11”
Register Output Consumer Mode
(Note 2) Professional Mode
FS3 FS2 FS1 FS0
fs Clock comparison
(Note 1) Byte3
Bit3,2,1,0 Byte0
Bit7,6 Byte4
Bit6,5,4,3
0 0 0 0 44.1kHz ± 3% 0000 01 0000
0 0 0 1 Reserved - 0001 (others) 0000
0 0 1 0 48kHz ± 3% 0010 10 0000
0 0 1 1 32kHz ± 3% 0011 11 0000
1 0 0 0 88.2kHz ± 3% (1000) 00 1010
1 0 1 0 96kHz ± 3% (1010) 00 0010
Table 17. fs Information
Note 1. At least ±3% range is id entified as the value in the Table 17. In case of an intermediate frequency of these two,
FS3-0 bits indicate the nearer value. When the frequency i s much larger t han 96kHz or much sma ller than 32kHz,
FS3-0 bits may indicate “1100”, “1110” or “0001”.
Note 2. In consumer mode, Byte3 Bit3-0 are copied to FS3-0.
The pre-emphasis information is detected and reported on the PEM bit. This information is extracted from channel 1 by
default (CS12 bit = “0”). It can be switched to channel 2 by changing the CS12 bit in the control register.
Consumer mode Professional mode
PEM bit Pre-emphasis Byte0
Bit3,4,5 Byte0
Bit2,3,4
0 OFF ≠ 0X100 ≠ 100
1 ON 0X100 100
Table 18. PEM Information
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Interrupt Handling for DIR
There are nine events that cause the INT2-0 pins to go “H”.
1. UNLCK: PLL unlock state detection
“1” when the PLL loses lock. The AK4122 loses lock when the distance between two preamb les is
not correct or when those preambles are not correct.
2. PAR: Parity error or biphase coding error detection
“1” when parity error or biphase coding error is detected, updated every sub-frame cycle.
3. AUTO: Non-PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is output to the AUTO bit.
4. V: Validity flag detection
“1” when validity flag is detected. Updated every sub-frame cy cle.
5. AUDN: Non-audio detection
“1” when the “AUDN” bit in recover ed c hannel status indicates “1”. Updated every block cycle.
6. STC: Sampling frequency or pre-emphasis information change detection
“1” when FS3-0 or PEM bit changes. Reading 07H registe r resets it.
7. QINT: U bit (Q-subcode) sync fla g
“1” when the Q-subcode differs from old one, and stays “1” until this register is read. Updated every
sync code cycle for Q-subcode. Reading 07H register resets it.
8. CINT: Ch annel status sync flag
“1” when receive d C bit s differ from old ones, and sta ys “1” unti l this regist er is rea d. Updated e very
block cycle. Reading 07H register resets it.
9. DAT: DAT Start ID detection
When the category code shows DAT, “1” when the Start ID of DAT is detecte d. Reading 08H register
resets it.
INT1-0 pins output an OR’ed si gnal based on t he above nine int errupt events. When m asked, the interrupt e vent does not
affect the operation of the INT1-0 pins (the masks do not affect the registers (UNLCK, PAR, etc.) themselves). Once
INT0 pin goes to “H”, it maintai ns “H” for 1024 cycles (t his value can be change d by the EFH1-0 bits) afte r all events not
masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared.
INT2 pin output a state change on the above 1 ∼ 5 and an OR’ed signal based on the above 6 ∼ 9. It stays “H” until 07H
and 08H registers are read. Mask bits are shared with INT0.
UNLCK, AUTO, V and AUDN bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or
CINT and DAT bit goes to “1”, it stays “1” until the register is read.
When the AK4122 loses lock, the channel status bits a re initializ ed. In this initial st ate, INT0 and INT2 outputs the OR’ed
signal between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDN. INT2-0 pins are “L”
when the DI R is no t se le cte d.
When DIR is used as input port and the PLL loses lock (unlock state), the output data is muted automatically . When
AMUTE bit = “1”, SDTIO and SDTO are muted automatically when the AK4122 detects unlock, Non-Audio or
Non- PC M/DTS-CD. After the in te rrupt ev en ts are cleared, mute is cancelled automatically. W h e n AMUTE bit = “0”,
SDTIO and SDTO outputs “L” whe n the PLL loses lock (unloc k state), and outputs data when ot her errors (PAR, AUTO
etc.).
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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(1) UNLCK, PAR, AUTO, V and AUDN bits
Hold “1”
Interrupt
(UNLCK, PAR, AUTO, V, AUDN)
INT0 pin
INT1 pin
INT2 pin
Register 07H
Read 07H
“0”
Hold Tim e (max:4096/fs)
“0”
Hold Time = 0
BICK, LRCK (UNLCK)
BICK, LRCK (except UNLCK)
SDTIO / SDTO (AMUTE = “1”)
(UNLCK, AUTO, V, AUDN)
SDTIO / SDTO (AMUTE = “0”)
(AUTO, V, AUDN)
SDTI O / SDTO (P AR e rror)
Free Run
fs : around 20kHz
SDTIO / SDTO (AMUTE = “0”)
(UNLCK)
Mute
“L” Output
Previous Data
: Normal Operation
Figure 17. INT2-0 Timing (UNLCK, PAR, AUTO, V, AUDN bits)
ASAHI KASEI [AK4122]
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(2) STC, CINT and QINT bits
Interrupt
(STC, CINT , Q INT)
INT0 pin
INT1 pin
INT2 pin
Register 07H
Read 07H
BICK, L R C
K
SDTIO / SDTO
Interrupt
(FS3-0, PEM, C-bit, Q-sub)
“0”
Hold “1”“0”
(1)
(2)
: Normal Operation
Hold “1” “0”
(1)
(2)
Figure 18. INT2-0 Timing (STC, CINT, QINT bits)
(1) Hold Time : max. 4096/fs
(2) Hold Time = 0
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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(3) DAT bit
Interrupt
(DAT)
INT0 pin
INT1 pin
INT2 pin
Register 08H
Read 08H
BICK, L R C
K
SDTIO / SDTO
“0”
Hold “1”“0”
(1)
(2)
: Normal Operation
Hold “1” “0”
(1)
(2)
Figure 19. INT2-0 Timing (DAT bit)
(1) Hold Time : max. 4096/fs
(2) Hold Tim e = 0
ASAHI KASEI [AK4122]
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INT0/1 pin ="H"
No
Yes
Yes
Initialize
PD pin ="L" to "H"
Read 07H, 08H
Mute SDTIO / SDTO
Read 07H , 08H
No
(Each Error Handling)
Read 07H, 08H
(Resets registers)
INT0/1 pin ="H"
Release
Muting
Figure 20. Interrupt Handling Sequence Example 1
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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INT1 pin ="H"
No
Yes
Initialize
PD pin ="L " to "H"
Read 07H
Read 07H
and
Detect QSUB= “1”
No
(Read Q-buffer)
New data
is valid
INT 1 pin ="L"
QCRC = “0”
Yes
Yes
New data
is invalid
No
Figure 21. Interrupt Handling Sequence Example 2
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
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Q-subcode buffers
The DIR of the AK4122 has a Q-subcode buffer for CD application. The AK4122 takes Q-subcode into registers under
the following conditions:
1) The sync word (S0, S1) consists of at least 16 “0”s.
2) The start bit is “1”.
3) Those 7-bits Q-W follows to the start bit.
4) The distance between two start bits is 8-16 bits.
The QINT bit in the control register goes “1” when the new Q-subcode differs from old one, and goes “0” when QINT bit
is read.
1 2 3 4 5 6 7 8 *
S0 0 0 0 0 0 0 0 0 0…
S1 0 0 0 0 0 0 0 0 0…
S2 1 Q2 R2 S2 T2 U2 V2 W2 0…
S3 1 Q3 R3 S3 T3 U3 V3 W3 0…
: : : : : : : : : :
S97 1 Q97 R97 S97 T97 U97 V97 W97 0…
S0 0 0 0 0 0 0 0 0 0…
S1 0 0 0 0 0 0 0 0 0…
S2 1 Q2 R2 S2 T2 U2 V2 W2 0…
S3 1 Q3 R3 S3 T3 U3 V3 W3 0…
: : : : : : : : : :
(*) number of “0” : min=0; max=8.
Figure 22. Configuration of U-bit(CD)
Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
CTRL ADRS TRACK NUMBER INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE SECOND FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO ABSOLUTE MINUTE ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME CRC
G(x)=x
16+x12+x5+1
Figure 23. Q-subcode
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
13H Q-subcode Address / Control Q9 Q8 · · · · · · · · · · · · Q3 Q2
14H Q-subcode Track Q17 Q16 · · · · · · · · · · · · Q11 Q10
15H Q-subcode Index · · · · · · · · · · · · · · · · · · · · · · · ·
16H Q-subcode Minute · · · · · · · · · · · · · · · · · · · · · · · ·
17H Q-subcode Second · · · · · · · · · · · · · · · · · · · · · · · ·
18H Q-subcode Frame · · · · · · · · · · · · · · · · · · · · · · · ·
19H Q-subcode Zero · · · · · · · · · · · · · · · · · · · · · · · ·
1AH Q-subcode ABS Minute · · · · · · · · · · · · · · · · · · · · · · · ·
1BH Q-subcode ABS Second · · · · · · · · · · · · · · · · · · · · · · · ·
1CH Q-subcode ABS Frame Q81 Q80 · · · · · · · · · · · · Q75 Q74
Figure 24. Q-subcode register map
↑
Q
ASAHI KASEI [AK4122]
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Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The DIR of the AK4122 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PC M preamble
based on Dolby “AC-3 Data Stre am in IEC 60958 Interfac e” is detec ted, the NPCM bit goes to “1”. The 96-bit sync code
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM to “1”.
Once the NPCM i s set to “1”, it will re main “1” until 4096 fram es pass through the chip without an additiona l sync pattern
being detected (Timing diagram: Figure 27 and Figure 28). When those preambles are detected, the burst preambles Pc
and Pd (Pc: burst i nformati on, Pd: length code; Refer to Tabl e 22, 23) that follow t hose sync codes are stored to registers.
The AK4122 also has a DTS-CD bitstream auto-det ection function. When AK4122 detects DTS-CD bitstream , the
DTSCD bit goes to “1”. If the next sync code does not occur within 4096 frames, the DTSCD bit goes to “0” until either
the AK4122 detects the stream again. OR’ed value of the NPCM and DTSCD bits are output to the AUTO bit. The
AK4122 detect s 14bit sy nc word and 16bit sync word of a DT S-C D bits tream , the dete ction functi on can be set ON/OFF
by DTS14 and DTS16 bit.
Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interfac e pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C1 /0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes to high impeda nce after a low-to-high
transition of CSN. The maximum speed of CCLK is 5MHz. The chi p address is fixed to “00”. The access to the chip
address except for “00” is invalid. PDN pin = “L” resets the registers to their default values. Read/Write can be access
without MCLK, BI CK and , LRCK.
CSN
CCLK
CDTI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CDTO Hi-Z
Write
CDTI C1 C0 R/W A4 A3 A2 A1 A0
CDTO Hi-Z
Read
D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z
C1 - C0 : Chip Address (Fixed to "00")
R/W : READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 25. Control I/F Timing
ASAHI KASEI [AK4122]
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Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H PDN & Mode Control XTL1 XTL0 TXE SMUTE DEAU DEM1 DEM0 PWN
01H Selector & Clock Control BYPS OSEL ISEL1 ISEL0 ICKS1 ICKS0 OCKS1 OCKS0
02H Audio Interface Format 0 0 0 ODIF IDIF1 IDIF0 DIF1 DIF0
03H DIR Control CS12 AMUTE EFH1 EFH0 IPS1 IPS0 OPS1 OPS0
04H INT0 Mask MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0
05H INT1 Mask MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1
06H DAT Mask & DTS Detect 0 0 0 0 DTS16 DTS14 MDAT1 MDAT0
07H Receiver Status 0 UNLCK PAR AUTO V AUDN STC CINT QINT
08H Receiver Status 1 DAT DTSCD NPCM PEM FS3 FS2 FS1 FS0
09H Receiver Status 2 0 0 0 0 0 0 CCRC QCRC
0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
0BH RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
0CH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
0DH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24
0EH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32
0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
13H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2
14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10
15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18
16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26
17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34
18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42
19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50
1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58
1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66
1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
PDN pin = “L” resets the registe rs to their default values.
When PORT1 or PORT2 are selected as input port, the status registers (07H ∼ 1CH) are init ialized.
Note. Unused bits must contain a “0” value.
Note. For addresses from 1DH ∼ 1FH, data must not be written.
ASAHI KASEI [AK4122]
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Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H PDN & Mode Control XTL1 XTL0 TXE SMUTE DEAU DEM1 DEM0 PWN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 0 0 0 1 1
PWN: Power Down Control
0 : Power down
1 : Normal operation (Default)
“0” powers down all sections. The contents of all register are not initialized and enabled to write to the
registers. The internal registers (00H ∼ 06H) are not initialized, however, the status registers (07H ∼ 1CH)
are initialized. Read/Write operations to the registers are enabled.
DEM1-0: De-emphasis Control (Table 12, 13)
Initial values are “01”.
DEAU: De-emphasis Auto Control
0 : Disable (Default)
1 : Enable
When DEAU bit = “1”, the de-emphasis filter is enabled automatically by sampling frequency and
pre-emphasis information in the channel status.
SMUTE: Soft Mute Control
0 : Normal operation (Default)
1 : SDTIO and SDTO soft mute
When SMUTE bit = “1”, SDTO and SDTIO outputs “L”.
TXE: TX Output enable
0 : Disable, TX outputs “L”.
1 : Enable (Default)
XTL1-0: Reference MCLK Frequency Select (Table 16)
Initial v a lu es are “11” .
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Selector & Clock Control BYPS OSEL ISEL1 ISEL0 ICKS1 ICKS0 OCKS1 OCKS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 1 0 1 0
OCKS1-0: OM CLK Frequency Select for Master mode (Table 5)
Initial v a lu es are “10” .
ICKS1-0: MCLK2 Frequency Select for Master mode (Table 4)
Initial v a lu es are “10” .
ISEL1-0: Input Port Select
Initial v a lu es are “00” .
ISEL1 ISEL0 Input PORT
0 0 PORT1
0 1 PORT2
1 0 DIR
1 1 N/A
Default
Table 19. Input PORT Select
OSEL: Outpu t Por t Select
Initial v a lues are “0 ” .
OSEL Output PORT
0 PORT3
1 PORT2
Default
Table 20. Output PORT Select
BYPS: Select Bypass mode
0 : SRC mode (Default)
1 : Bypass mode
When BYPS bit = “1”, the AK4122 outputs the clocks (BICK, LRCK) and data that is input by input port
without SRC.
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Audio Interface Format 0 0 0 ODIF IDIF1 IDIF0 DIF1 DIF0
R/W RD RD RD R/W R/W R/W R/W R/W
Default 0 0 0 0 0 1 0 1
DIF1-0: Audio Interface Format for PORT1 (Table 8)
Initial v a lu es are “01” .
IDIF1-0: Audio Interface Format for PORT2 (Table 9)
Initial v a lu es are “01” .
ODIF: Audio Interface Format for PORT3 (Table 10)
Initial v a lues are “0 ” .
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H DIR Control CS12 AMUTE EFH1 EFH0 IPS1 IPS0 OPS1 OPS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 1 0 1 0 0 0 0
OPS1-0: Output Through Data Select for TX (Table 15)
Initial v a lu es are “00” .
IPS1-0: Input Recovery Data Select (Table 14)
Initial v a lu es are “00” .
EFH1-0: Interrupt 0 pin Hold Count Select
Initial v a lu es are “01” .
LRCK of Table 21 is DIR’s LRCK, the hold time scales with 1/fs.
EFH1 EFH0 Hold Count
0 0 512LRCK
0 1 1024LRCK
1 0 2048LRCK
1 1 4096LRCK
Default
Table 21. Hold count sel ect
AMUTE: Auto Mute Control
0 : Normal operation
1 : Auto Mute (Default)
When AMUTE bit = “1”, SDTIO and SDTO are muted automatically when the AK4122 detects unlock,
Non-Audio or Non-PCM/DTS-CD.
CS12: Channel Status select
0 : Channel 1 (Default)
1 : Channel 2
This bit selects that channel status is used to derive C-bit buffers, AUDN, PEM, FS3-0, Pc, Pd and CRC.
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H INT0 Mask MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 1 1 1 1 1 1
MQIT0: Mask enable for QINT bit
0 : Mask disable
1 : Mask enable
MCIT0: Mask enable for CINT bit
0 : Mask disable
1 : Mask enable
MSTC0: Mask enable for STC bit
0 : Mask disable
1 : Mask enable
MAUD0: Mask enable for AUDN b it
0 : Mask disable
1 : Mask enable
MV0: Mask enable for V bit
0 : Mask disable
1 : Mask enable
MAUT0: Mask enable for AUTO bit
0 : Mask disable
1 : Mask enable
MPAR0: Mask enable for PAR bit
0 : Mask disable
1 : Mask enable
MULK0: Mask enable for UNLCK bit
0 : Mask disable
1 : Mask enable
The factor which mask bit is set to “0” affects INT0 and INT2 pins operation.
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
05H INT1 Mask MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 0 0 0 1 1 1
MQIT1: Mask enable for QINT bit
0 : Mask disable
1 : Mask enable
MCIT1: Mask enable for CINT bit
0 : Mask disable
1 : Mask enable
MSTC1: Mask enable for STC bit
0 : Mask disable
1 : Mask enable
MAUD1: Mask enable for AUDN b it
0 : Mask disable
1 : Mask enable
MV1: Mask enable for V bit
0 : Mask disable
1 : Mask enable
MAUT1: Mask enable for AUTO bit
0 : Mask disable
1 : Mask enable
MPAR1: Mask enable for PAR bit
0 : Mask disable
1 : Mask enable
MULK1: Mask enable for UNLCK bit
0 : Mask disable
1 : Mask enable
The factor which mask bit is set to “0” affects INT1 pin operation.
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
06H DAT Mask & DTS Detect 0 0 0 0 DTS16 DTS14 MDAT1 MDAT0
R/W RD RD RD RD R/W R/W R/W R/W
Default 0 0 0 0 1 1 1 1
MDAT0: Mask enable for DAT bit
0 : Mask disable
1 : Mask enable
The factor which mask bit is set to “0” affects INT0 and INT2 pins operation.
MDAT1: Mask enable for DAT bit
0 : Mask disable
1 : Mask enable
The factor which mask bit is set to “0” affects INT1 pin operation.
DTS14: DTS-CD 14bit Sync Word Detect
0 : No detect
1 : Detect (Default)
DTS16: DST-CD 16bit Sync Word Detect
0 : No detect
1 : Detect (Default)
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
07H Receiver Status 0 UNLCK PAR AUTO V AUDN STC CINT QINT
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 0
QINT: Q-subcode Buffer Interrupt
0 : No change
1 : Changed
This bit goes to “1” when Q-subcode stored in register addresses 13H to 1CH is updated.
CINT: Channe l Status Buffer Interrupt
0 : No change
1 : Changed
This bit goes to “1” when C-bit stored in register addresses 0AH to 0EH changes.
STC: Sampling Frequency or Pre-emphasis Informati on Change Detection
0 : No detect
1 : Detect
This bit goes to “1” when either the FS3-0 or PEM bit changes.
AUDN: Audio Bit Output
0 : Audio
1 : Non audio
This bit is made by encoding channel status bits.
V: Validity Bit
0 : Valid
1 : Invalid
AUTO: Non-PCM or DTS-CD Bit Steam Auto Detection
0 : No detect
1 : Detect
This bit outputs the OR’ed value of NPCM and DTSCD bits.
PAR: Parity Error or Bi-phase Error Status
0 : No error
1 : Error
This bit goes to “1” if a parity error or biphase error is detected in the sub-frame.
UNLCK: PLL Lock Status
0 : Lock
1 : Unlock
QINT, CINT and STC bits are initialized when 07H is read.
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
08H Receiver Status 1 DAT DTSCD NPCM PEM FS3 FS2 FS1 FS0
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 1
FS3-0: Sampling Frequency Detection (Table 17)
PEM: Pre-emphasis Detect (Table 18)
0 : OFF
1 : ON
This bit is made by encoding the channel st atus bits.
NPCM: Non-PCM Bit Stream Auto Detection
0 : No detect
1 : Detect
DTSCD: DTS-CD Bit Stream Auto Detect
0 : No detect
1 : Detect
DAT: DAT Start ID Detect
0 : No detect
1 : Detect
When the category code shows DAT, “1” when the Start ID of DAT is detected. Reading 08H register
resets it.
DAT bit is initial iz ed when 08 H is re ad .
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
09H Receiver Status 2 0 0 0 0 0 0 CCRC QCRC
R/W RD RD RD RD RD RD RD RD
Default 0 0 0 0 0 0 0 0
QCRC: Cyclic Redundancy Check for Q-subcode
0 : No error
1 : Error
CCRC: Cycli c Redundancy Check for Channel Status
0 : No error
1 : Error
This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
ASAHI KASEI [AK4122]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
0BH RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
0CH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16
0DH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24
0EH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32
R/W RD
Default Not initialized
CR39-0: Receiver Channel Status Byte 4-0
All 40 bits are updated at the same time every block (192 frames) cycle.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
R/W RD
Default Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst Preamble Pd Byte 0 and 1
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
13H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2
14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10
15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18
16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26
17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34
18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42
19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50
1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58
1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66
1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74
R/W RD
Default Not initialized
Q81-2: Q-subcode
All 80 bits are updated at the same time every sync code cycle for Q-subcode.
ASAHI KASEI [AK4122]
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Burst Preambles in Non-PCM Bitstreams
0
16 bits of bitstream
34 781112 27 28 29 30 31
preamble Aux. LSB MSB V U C P
sub-frame of IEC60958
015
Pa Pb Pc Pd Burst_payload stuffing
repetition time of the burst
Figure 26. Data Structure of IEC60958
Preamble word Length of field Contents Value
Pa 16 bits sync word 1 0xF872
Pb 16 bits sync word 2 0x4E1F
Pc 16 bits Burst info see Table 23
Pd 16 bits Length code numbers of bits
Table 22. Burst Preamble Word
ASAHI KASEI [AK4122]
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Bits of Pc Value Contents Repetition time of burst
in IEC60958 frames
0-4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without e xtension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
≤ 4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
5, 6 0 reserved, shall be set to “0”
7 0
1
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
8-12 data type dependent info
13-15 0 bit stream number, shall be set to “0”
Table 23. Field of Burst Information Pc
ASAHI KASEI [AK4122]
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Non-PCM Bitstream Timing
(1) When Non-PCM preamble does not arrive within 4096 frames
Pd3
Pc3
Pa Pc1Pd1
Pb Pa Pc2Pd2
Pb Pa Pc3Pd3
Pb
“0” Pc1Pc2
“0” Pd1Pd2
PDN pin
Bit stream
A
UTO bit
Pc Register
Pd Registe
r
Repetition time >4096 frames
Figure 27. Timing example 1
(2) When Non-PCM bitstream stops (when MULK0=0)
Pdn
Pcn
Pa Pc1Pd1
Pb Stop Pa PcnPdn
Pb
Pc0Pc1
Pd0Pd1
INT0 pin
Bit stream
A
UTO bi
t
Pc Register
Pd Registe
r
INT0 hold time
2~3 Syncs (B,M or W)
<20 mS (Lock time)
<Repetition time
Figure 28. Timing example 2
ASAHI KASEI [AK4122]
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SYSTEM DESIGN
Figure 29 shows the typical syste m connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
• PORT2, PORT3 : Slave Mode
Shield Shield
0.1µ10µ
10µ
0.1µ
Analog Supply
3.0 ~ 3.6V
470Ω
2.2n
0.1µ
10µ
Digital Supply
3.0 ~ 3.6V DSP3
CDTI1
2
3
4
5
6
7
8
9
10
11
12
CDTO
TST1
INT2
TST2
TST3
M/S2
M/S3
SMUTE
TST4
TST5
FILT
Top View
AVSS
13
AVDD
14
TST6
15
RX1
16
TST7
17
RX2
18
TST8
19
RX3
20
TST9
21
RX4
22
TST10
23
TST11
24
S/PDIF
sources
36
35
34
33
32
31
30
29
28
27
26
25
SDTIO
BICK2
LRCK2
MCLK2
DVDD
DVSS
SDTI
BICK1
LRCK1
PDN
AVSS
R
CCLK
48 47 46
CSN
BVSS
45 44 42 4143 39 3840 37
DVDD
DVSS
OMCLK
LRCK
BICK
SDTO
TX
INT1
INT0
Shield Shield Shield
uP & DSP
fso
2.2µ
12kΩ
Reset
Digital Supply
3.0 ~ 3.6V
DSP1
fsi
DSP2
fsi
Note:
- AVSS, BVSS and DVSS of the AK4122 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 29. Typical Connection Diagram
ASAHI KASEI [AK4122]
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1. Grounding and Power Supply Decoupling
The AK4122 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not critical. AV SS, BVSS and DVSS of the AK4122 must be
connected to analog ground plane . System analog ground and digital ground should be connected together near to where
the supplies are brought ont o the printed circui t board. Decoupling capac itors should be as near to the AK4122 as possible,
with the small v alue ceramic capacitor b e in g the nea r e s t.
2. PLL Loop-Filter
The C1 (2.2µF) and R1 (470Ω) shoul d be connected i n series and att ached between FILT pin and AVSS i n parallel with C2
(2.2nF). Please be careful the noise onto the FILT pin.
AK4122
C1
R1
FILT
VSS
C2
Parameter Recommended value Accuracy
R1 470Ω −5% ∼ +5 %
C1 2.2µF −50% ∼ +50%
C2 2.2nF
−50% ∼ +50%
Note: The accuracy includes temperature dependence.
Figure 30. Loop Filter for SRC
The R2 (12kΩ) should be connected in serie s and attached between R pin and AVSS. Please be careful the noise onto the R
pin.
AK4122
R2
R
VSS
Parameter Recommended value Accuracy
R2 12kΩ −5% ∼ +5 %
Note: The accuracy includes temperature dependence.
Figure 31. Loop Filter for DIR
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 51 -
3. Jitter Tol erance
Figure 32 shows the jitt er tolerance to ILRCK for AK4122. The jitter frequency and the jitte r amplitude shown in Figure 32
define the jitt er quantity. When the jitter am plitude is 0.01Uipp or less, the AK4122 ope rate normally regardless of the jitt er
frequency.
AK4122 Jit t er Toler ance
0.00
0.01
0.10
1.00
10.00
1 10 100 1000 10000
Fr equency [Hz]
Amplitude [UIpp
]
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It ma y degrade up to about −50dB.)
(3) There is a possibility that the output data is lost.
Note:
- The jitter amplitude is for ILRCK and 1UI (Unit Interval) is one cycle of ILRCK. W hen FSI = 48kHz, 1UI is
1/48kHz = 20.8µs.
Figure 32. Jitter Tolerance
(3)
(2)
(1)
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 52 -
PACKAGE
112
48 13
7.0
9.0 ± 0.2
7.0
9.0 ± 0.2
0.22 ± 0.08
48pin LQFP(Unit: mm)
0.10
37 24
2536
0.16
±
0.07
1.40
±
0.05
0.13
±
0.13
1.70Max
0° ∼ 10°
0.10
0.5
±
0.2
0.5 M
Material & Lead finis h
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 53 -
MARKING
1
AKM
AK4122VQ
XXXXXXX
XXXXXXXX: Date code identifier
ASAHI KASEI [AK4122]
MS0267-E-03 2004/08
- 54 -
Revision History
Date (YY/MM/DD) Revision Reason Page Contents
03/10/03 00 First Edition
04/01/27 01 Spec Change 10, 11 SWITCHING CHARACTER ISTICS
Audio Interface Timing
BICK1/BICK2/BICK Period@Slave mode:
min 160ns → 1/64/fs
Add Spec 9 Add FILTER CHARACTERISTICS 04/07/23 02
Add Spec 16, 18 Add a sentence:
“The DIF1-0 bits of the PORT1 should be set a
value except “10” (I2S Compatible) when the DIR
is selected as an input port.”
04/8/16 03 Add Spec 51 Add Jitter Tolerance
IMPORTANT NOTICE
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here:
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