CY74FCT16543CTPVC - Cypress Semiconductor

16-Bit Latched Transceivers

ax id: 7042

CY74FCT16543T

CY74FCT162543T

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

ust 1994 – Revised Oct ober 30

1997

543T

Features

• Low pow er, pin- com pati ble replacement for ABT

functions

• FCT-E speed at 3.4 ns

• Power-off disable outputs permits live insertion

• Edge-rate contr ol circuit ry for significantl y improved

noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6 -mil pit ch) and SSOP (25- mil pi tch)

packages

• Industrial temperature range of −40°C to +85°C

•V

CC = 5V ± 10%

CY74FCT16543T Features:

• 64 mA sink current , 32 mA source current

• Typical VOLP (ground bounce) <1.0V at VCC = 5V,

TA = 25°C

CY74FCT162543T Features:

• Balanced 24 mA output drivers

• Red uced system switching noise

• Typical VOLP (ground bounce) <0.6V at VCC = 5V,

TA= 25° C

Functional Descripti on

The CY74FCT16543T and CY74FCT162543T are 16-bit,

high-speed, low power latched transceivers that are organized as two

independent 8-bit D-type latched transceivers containing two sets of

eight D-type latches with separate Latch Enable (LEAB, LEAB) and

Output Enable (OEAB, OEAB) controls for each set to permit

independent contro l of inputting and outputting in either direction of

data flow. For data flow from A to B, for exam ple, the A-to-B input

Enable (CEAB) must be LOW in order to enter data from A or to take

data from B as indicated in the truth table. With CAEB LO W , a LOW

signal on the A-to-B Latch Enable (LEAB) makes the A-to-B latches

transparent; a subsequent LOW-to-HIGH transition of the LEAB

signal puts the A latches in the storage mode and t heir outputs no

longer change with the A inputs. With CEAB and OEAB both LOW,

the three-state B output buffers are active and reflect the data present

at the output of the A lat ches. Control of data from B to A is similar,

but uses CEAB, LEAB, and OEAB inputs flow-through pinout and

smal l shrin k packaging and in simpl ifying board de sign . The out put

buffers are designed with a power-off disable feature to allow live

insertion of boards.

The CY74FCT16543T is ideally suited for driving

high-capacitance loads and low-impedance backplanes.

The CY74FCT162543T has 24-mA balanced output drivers

with current limiting resistors in the outputs. This reduces the

need for external terminating resistors and provides for

minimal undershoot and reduced ground bounce. The

CY74FCT162543T is ideal for driving tr ansmission lines.

Logic Block Diagrams PinConfiguration

1OEAB

SSOP/TSSOP

Top Vie w

GND

VCC

FCT16543T-1

FCT16543T-2

TO 7 OTHER CHANNELS

1B1

1OEBA

1A1

1CEBA

1LEAB

1OEAB

1LEBA

1CEAB

2B1

2OEBA

2A1

2CEBA

2OEAB

2LEBA

2CEAB

1LEAB

1CEAB

1A1

VCC

GND

2LEAB

1A2

1A3

1A5

1A4

1A6

1A7

1A8

GND

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2A8

GND

2OEAB

2CEAB

2LEAB

1OEBA

GND

VCC

1LEBA

1CEBA

1B1

VCC

GND

1B2

1B3

1B5

1B4

1B6

1B7

1B8

GND

2B1

2B2

2B3

2B4

2B6

2B7

2B8

GND

2OEBA

2CEBA

2LEBA

2B5

FCT16543T-3

TO 7 OTHERCHANNELS

CY74FCT16543T

CY74FCT162543T

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user

guidelines, not tested.)

Sto ra g e Temp e ra tur e ...... ..... ..... .....Co m ’ l −55°C to +125°C

Ambient Temperature with

Power Applied.................................Com’l −55°C to +125°C

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

(Maximum Si nk Curr ent/Pin)...........................−60 to +120 mA

Power Dissipation.......................................................... 1.0W

Static Discharge Voltage ...........................................>2001V

(per MIL- STD-883, Method 3015 )

Pin Description

Name Description

OEAB A-to-B Outp ut Enable Inp ut (Active LOW)

OEBA B-to-A Outp ut Enable Inp ut (Active LOW)

CEAB A-to-B Enable Input (Active LOW)

CEBA B-to-A Enable Input (Active LOW)

LEAB A-to-B Latch Enab le Input (Active LOW )

LEBA B-to-A Latch Enab le Input (Active LOW )

AA-to -B Data Inputs or B-to- A Three-St ate Output s

BB-to -A Data Inputs or A-to- B Three-St ate Output s

Function Table[1]

Inputs Latch

Status Output

Buffers

CEAB LEAB OEAB A to B B

H X X Storing High Z

X H X Storing X

X X H X High Z

LLLTransparent Curr ent A

Inputs

L H L Storing Previous A

Inputs[2]

Operating Range

Range Ambient

Temperature VCC

Industrial −40°C to +85°C 5V ± 10%

Electrical Characteristics Ov er the Operating Range

Parameter Description T est Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Volta ge 0.8 V

VHInput Hystere sis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V

IIH Input HIGH Current VCC= M a x ., V I=VCC ±1µA

IIL Input LOW Current VCC= M a x ., V I=GND ±1µA

IOZH High Impedance Output Cur-

rent (Three-State Output pins) VCC= M a x ., VOUT=2.7V ±1µA

IOZL High Impedance Output Cur-

rent (Three-State Output pins) VCC= M a x ., VOUT=0.5V ±1µA

IOS Short Circuit Current[7] VCC=M a x ., VOUT=GND −80 −140 −200 mA

IOOutput Drive Current[7] VCC=M a x ., VOUT=2.5V −50 −180 mA

IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[8] ±1µA

Notes:

1. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.

2. Data prior to LEAB LOW-to-HIGH Transition

H = HIGH Voltage Level. L = LOW Voltage Level.

X = Don’t Care. Z = High Impedance.

3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature

range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

5. Typical values are at VCC= 5.0V, TA= +25°C ambient.

6. This parameter is guaranteed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, IOS tests should be performed last.

8. Tested at +25°C.

CY74FCT16543T

CY74FCT162543T

Output Drive Characteristics for CY 74FCT16543T

Parameter Description Test Conditi ons Min. Typ.[5] Max. Unit

VOH Output HIGH Voltage VCC=Mi n ., IOH=−3 mA 2.5 3.5 V

VCC=Mi n ., IOH=−15 m A 2.4 3.5

VCC=Mi n ., IOH=−32 m A 2.0 3.0

VOL Ou tp ut LOW Vo l tag e VCC=Mi n ., IOL=64 mA 0.2 0.55 V

Output Drive Characteristics for CY 74FCT162543T

Parameter Description Test Conditi ons Min. Typ.[5] Max. Unit

IODL Output LOW Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA

IODH Output HIGH Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA

VOH Output HIGH Voltage VCC=Mi n ., IOH=−24 m A 2.4 3.3 V

VOL Ou tp ut LOW Vo l tag e VCC=Mi n ., IOL=24 mA 0.3 0.55 V

Capacitance[6] (TA = +25°C, f = 1.0 MHz)

Parameter Description Test Conditions Typ.[5] Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6.0 pF

COUT Output Capacitance VOUT = 0V 5.5 8.0 pF

Pow er Supply Characteri stic s

Parameter Description Test Conditi ons Typ.[5] Max. Unit

ICC Quiesc ent P ower Supply Cur rent VCC=Max. VIN≤0.2V,

VIN≥VCC−0.2V 5500 µA

∆ICC Quiescent Power Supply Current

(TTL inputs HIGH) VCC=Max. VIN=3.4V[9] 0.5 1.5 mA

ICCD Dynamic Power Supply

Current[10] VCC=M ax., One Input

Toggli ng, 50% Dut y Cycl e,

Out puts Op en, OE=GND

VIN=VCC or

VIN=GND 60 100 µA/MHz

ICTotal Power Supply Current[11] VCC=Max., f1=10 MHz,

50% Duty Cycle, Outputs

Open, One Bit Toggling,

OE=GND

VIN=VCC or

VIN=GND 0.6 1.5 mA

VIN=3.4V or

VIN=GND 0.9 2.3 mA

VCC=Max., f1=2.5 MHz,

50% Duty Cycle, Outputs

Open, Sixteen Bits Toggling,

OE=GND

VIN=VCC or

VIN=GND 2.4 4.5[12] mA

VIN=3.4V or

VIN=GND 6.4 16.5[12] mA

Notes:

9. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

11. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input levels

∆ICC = Power Supply Current for a TTL HIGH input

(VIN=3.4V)

DH = Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair

(HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

12. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

CY74FCT16543T

CY74FCT162543T

Swi tch i ng C h ara cter i sti cs Over the Operating Range[13]

CY74FCT16543T

CY74FCT162543T CY74FCT16543AT

CY74FCT162543AT Fig.

No.[14]

Parameter Description Min. Max. Min. Max. Unit

tPLH

tPHL Propagation Delay

Transparent Mode

A to B or B to A

1.5 8.5 1.5 6.5 ns 1, 3

tPLH

tPHL Propagation Delay

LEBA to A, LEAB to B 1.5 12.5 1.5 8.0 ns 1, 5

tPZH

tPZL Outpu t Enable Time

OEBA or OEAB to A or B

CEBA or CEAB to A or B

1.5 12.0 1.5 9.0 ns 1, 7, 8

tPHZ

tPLZ O ut put Disa ble Ti m e

OEBA or OEAB to A or B

CEBA or CEAB to A or B

1.5 9.0 1.5 7.5 ns 1, 7, 8

tSU Set-up Time HIGH or LOW

A or B to LEAB or LEBA 2.0 —2.0 —ns 4

tHHold Time HIGH or LOW

A or B to LEAB or LEBA 2.0 —2.0 —ns 4

tWLEBA or LEAB Pulse Widt h LOW 4.0 —4.0 —ns 5

tSK(O) Output Skew[15] —0.5 —0.5 ns —

CY74FCT16543CT

CY74FCT162543CT CY74FCT16543ET

CY74FCT162543ET Fig.

No.[14]

Parameter Description Min. Max. Min. Max. Unit

tPLH

tPHL Propagation Delay

Transparent Mode

A to B or B to A

1.5 5.1 1.5 3.4 ns 1, 3

tPLH

tPHL Propagation Delay

LEBA to A, LEAB to B 1.5 5.6 1.5 3.7 ns 1, 5

tPZH

tPZL Outpu t Enable Time

OEBA or OEAB to A or B

CEBA or CEAB to A or B

1.5 7.8 1.5 4.8 ns 1, 7, 8

tPHZ

tPLZ O ut put Disa ble Ti m e

OEBA or OEAB to A or B

CEBA or CEAB to A or B

1.5 6.5 1.5 4.0 ns 1, 7, 8

tSU Set-up Time HIGH or LOW

A or B to LEAB or LEBA 2.0 —1.0 —ns 4

tHHold Time HIGH or LOW

A or B to LEAB or LEBA 2.0 —1.0 —ns 4

tWLEBA or LEAB Pulse Widt h LOW 4.0 —3.0 —ns 5

tSK(O) Output Skew[15] —0.5 —0.5 ns —

Notes:

13. Minimum limits are guaranteed but not tested on Propagation Delays.

14. See “Parameter Measurement Information” in the General Information section.

15. Skew between any two outputs of the same package switching in the same directional. This parameter is guaranteed by design.

CY74FCT16543T

CY74FCT162543T

Document #: 38-00388-C

Ordering Information CY 74FCT16543

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

3.4 CY74FCT16543ETPAC Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT16543ETPVC O56 56-Lead (300-Mil ) SSOP

5.1 CY74FCT16543CTPAC Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT16543CTPVC O56 56-Lead (300-Mil ) SSOP

6.5 CY74FCT16543ATPA C Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT16543ATPVC O56 56-Lead (300-Mil) SSOP

8.5 CY74FCT16543TPAC Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT16543TPVC O56 56-Lead (300-Mil) SSOP

Ordering Information CY 74FCT162543

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

3.4 CY74FCT162543ETPAC Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162543ETPVC O56 56-Lead (300-Mil) SSOP

5.1 CY74FCT162543CTPAC Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162543CTPVC O56 56-Lead (300-Mil) SSOP

6.5 CY74FCT162543ATPAC Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162543ATPVC O56 56-Lead (300-Mil) SSOP

8.5 CY74FCT162543TPAC Z56 56-Lead (240-Mi l) TSSOP Industrial

CY74FCT162543TPVC O56 56-Lead (300-Mil) SSOP

CY74FCT16543T

CY74FCT162543T

of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not author ize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer ass umes all risk of such use and in doing so i ndemnifies Cypress Semiconductor against all charges.

Package Di ag ra ms

56-Lead Shrunk Small OutlinePackage O56

56-Lead Thin Shrunk Small Outline Package Z56