Rev.1.00, Aug.01.2003, page 1 of 13
R1LP0408C-I Series
Wide Temperature Range Version
4 M SRAM (512-kword × 8-bit)
REJ03C0067-0100Z
Rev. 1.00
Aug.01.2003
Description
The R1LP0408C-I is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LP0408C-I Series has realized
higher density, higher performance and low power consumption by employing CMOS process technology
(6-transistor memory cell). The R1LP0408C-I Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin TSOP II.
Features
• Single 5 V supply: 5 V ± 10%
• Access time: 55/70 ns (max)
• Power dissipation:
Active: 10 mW/MHz (typ)
Standby: 4 µW (typ)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Directly TTL compatible.
All inputs and outputs
• Battery backup operation.
• Operating temperature: −40 to +85°C
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 2 of 13
Ordering Information
Type No. Access time Package
R1LP0408CSP-5SI 55 ns 525-mil 32-pin plastic SOP (32P2M-A)
R1LP0408CSP-7LI 70 ns
R1LP0408CSB-5SI 55 ns 400-mil 32-pin plastic TSOP II (32P3Y-H)
R1LP0408CSB-7LI 70 ns
R1LP0408CSC-5SI 55 ns 400-mil 32-pin plastic TSOP II reverse (32P3Y-J)
R1LP0408CSC-7LI 70 ns
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 3 of 13
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
V
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top view)
32-pin SOP
32-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
V
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
CC
(Top view)
32-pin TSOP (reverse)
Pin Description
Pin name Function
A0 to A18 Address input
I/O0 to I/O7 Data input/output
CS# (CS) Chip select
OE# (OE) Output enable
WE# (WE) Write enable
VCC Power supply
VSS Ground
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 4 of 13
Block Diagram
•
•
•
•
•
•
••
•
•
•
I/O0
I/O7
CS#
WE#
OE#
A3A2A1A0 A6A5
V
V
CC
SS
Row
Decoder
Memory Matrix
2,048 2,048
Column I/O
Column Decoder
Input
Data
Control
×
Timing Pulse Generator
Read/Write Control
A4 A7
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
LSB
MSB
LSB
MSB
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 5 of 13
Operation Table
WE# CS# OE# Mode VCC current I/O0 to I/O7 Ref. cycle
× H × Not selected ISB, ISB1 High-Z
H L H Output disable ICC High-Z
H L L Read ICC Dout Read cycle
L L H Write ICC Din Write cycle (1)
L L L Write ICC Din Write cycle (2)
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS V
CC −0.5 to +7.0 V
Terminal voltage on any pin relative to VSS V
T −0.5*1 to VCC + 0.3*2 V
Power dissipation PT 0.7 W
Operating temperature Topr −40 to +85 °C
Storage temperature range Tstg −65 to +150 °C
Storage temperature range under bias Tbias −40 to +85 °C
Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +7.0 V.
DC Operating Conditions
(Ta = −40 to +85°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
V
SS 0 0 0 V
Input high voltage VIH 2.2 V
CC + 0.3 V
Input low voltage VIL −0.3*1 0.8 V
Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns.
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 6 of 13
DC Characteristics
Parameter Symbol Min Typ*1 Max Unit Test conditions
Input leakage current |ILI| 1 µA Vin = VSS to VCC
Output leakage current |ILO| 1 µA CS# = VIH or OE# = VIH or
WE# = VIL or V I/O = VSS to VCC
Operating current ICC 1.5 3 mA CS# = VIL,
Others = VIH/ VIL, II/O = 0 mA
Average operating current ICC1 8 25 mA Min. cycle, duty = 100%,
CS# = VIL, Others = VIH/VIL
II/O = 0 mA
I
CC2 2 5 mA Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS# ≤ 0.2 V,
VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V
Standby current ISB 0.1 0.5 mA CS# = VIH
Standby current to +85°C ISB1 20*2 µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V
10*3 µA
to +40°C ISB1 1.0*2 10*2 µA
1.0*3 3*3 µA
−20°C to +25°C ISB1 0.8*2 10*2 µA
0.8*3 3*3 µA
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH 2.4 V IOH = −1.0 mA
V
OH2 2.6 V IOH = −0.1 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. L version. (−7LI)
3. SL version. (−5SI)
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin 8 pF Vin = 0 V 1
Input/output capacitance CI/O 10 pF VI/O = 0 V 1
Note: 1. This parameter is sampled and not 100% tested.
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 7 of 13
AC Characteristics
(Ta = −40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Condit ions
• Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
• Input rise and fall time: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate + CL (50 pF) (R1LP0408C-5I)
1 TTL Gate + CL (100 pF) (R1LP0408C-7I)
(Including scope and jig)
Read Cycle
R1LP0408C-I
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 55 70 ns
Address access time tAA 55 70 ns
Chip select access time tCO 55 70 ns
Output enable to output valid tOE 25 35 ns
Chip select to output in low-Z tLZ 10 10 ns 2
Output enable to output in low-Z tOLZ 5 5 ns 2
Chip deselect to output in high-Z tHZ 0 20 0 25 ns 1, 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2
Output hold from address change tOH 10 10 ns
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 8 of 13
Write Cycle
R1LP0408C-I
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 55 70 ns
Chip selection to end of write tCW 50 60 ns 4
Address setup time tAS 0 0 ns 5
Address valid to end of write tAW 50 60 ns
Write pulse width tWP 40 50 ns 3, 12
Write recovery time tWR 0 0 ns 6
Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2, 7
Data to write time overlap tDW 25 30 ns
Data hold from write time tDH 0 0 ns
Output active from end of write tOW 5 5 ns 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS# going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem
of data bus contention. tWP ≥ tDW min + tWHZ max
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 9 of 13
Timing Waveform
Read Timing Waveform (WE# = VIH)
t
AA
t
CO
t
RC
t
LZ
t
OE
t
OLZ
t
HZ
t
OHZ
Valid data
Valid address
High impedance
Address
CS#
OE#
Dout
t
OH
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 10 of 13
Write Timing Waveform (1) (OE# Clock)
tWC
tCW
tWP
tAS
tOHZ
tDW tDH
tAW tWR
*8
Address
OE#
CS#
WE#
Dout
Din Valid data
Valid address
High impedance
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 11 of 13
Write Timing Waveform (2) (OE# Low Fixed)
Address
CS#
WE#
Dout
Din
tWC
tCW tWR
tAW tWP
tAS tWHZ tOW
tOH
tDW tDH
*11
*9 *10
*8
Valid data
Valid address
High impedance
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 12 of 13
Low VCC Data Retention Characteristics
(Ta = −40 to +85°C)
Parameter Symbol Min Typ*4 Max Unit Test conditions*3
VCC for data retention VDR 2 V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V
Data retention
current to +85°C ICCDR*1 20 µA VCC = 3.0 V, Vin ≥ 0 V
CS# ≥ VCC − 0.2 V
I
CCDR*2 10
to +40°C ICCDR*1 1.0 10 µA
I
CCDR*2 1.0 3
−20°C to +25°C ICCDR*1 0.8 10 µA
I
CCDR*2 0.8 3
Chip deselect to data retention time tCDR 0 ns See retention waveform
Operation recovery time tR t
RC*5 ns
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for SL version.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. tRC = read cycle time.
Low VCC Da ta Retention Timing Wavefo rm (CS# Controlled)
VCC
4.5 V
2.4 V
0 V
CS#
tCDR tR
CS# ≥ VCC – 0.2 V
VDR
Data retention mode
R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 13 of 13
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
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programs, algorithms, or circuit application examples contained in these materials.
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R1LP0408C-I Series
Rev.1.00, Aug.01.2003, page 14 of 13
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
1.00 Aug. 01, 2003 Initial issue
