Product Brief, Revision 1 May 31, 2005 LCK4012 Programmable High-Speed Clock Generator Features Flexible programming allows for output frequencies from 3.13 MHz to 800 MHz. Twenty-one programmable output clocks at various voltage levels, including: 1.2 V, 1.5 V, 2.5 V, and 3.3 V. High-speed differential clocks with divide-by-24 framing pulse. Limited support for 1.5 V differential outputs. I2C slave interface to allow for programmability. Low-power sleep mode: -- Clocks are individually programmed to stop or supply the reference clock. -- Unused clock output buffers need not be powered. -- Sleep mode power as low as 0.45 mW. Overview Agere Systems' LCK4012 is a programmable timing system that provides up to 21 programmable output clocks and three programmable frame-synchronizing pulses generated from a single external clock reference source. There are three 1.5 V differential output clocks (HCLK_0, 1, 2) and one 1.5 V differential output clock (VCLK), each programmable up to 800 MHz. Complementing these output clocks are three divide-by-24 frame sync outputs (HSYNC_0, 1 and NBSYNC), each with a single-ended 1.2 V level. In addition, the three HCLK clocks and the three frame syncs support individual programmable delays ranging from tens of pico seconds to 7 ns in 128 steps. Period jitter performance: -- 200 ps max at 300 MHz VCO frequency. There are two 3.3 V (GPCLK33_0, 1) and two 2.5 V (GPCLK25_0, 1) single-ended output clocks that can be optioned to accept up to four preprogrammed frequency references. Two 1.2 V (HTBEN_0, 1) single-ended, programmable output clocks have an added feature that enables them to be stopped high as well as low. There are five 3.3 V (PCLK33_0, 1, 2, 3, 4) output clocks, two 2.5 V (PCLK25_0, 1) output clocks, one 1.5 V (PCLK15) output clock, and one 1.2 V (PCLK12) output clock; all can be optioned to accept either of two preprogrammed frequency references. Package and processing: -- 100-pin FSBGA package, 10 mm x 10 mm, 0.8 mm pitch. -- 0.14 m process. There are two dedicated 2.5 V (REFCLK_0, 1) single-ended output clocks that are optioned to distribute the external crystal frequency reference. This reference may be distributed to other frequency generation systems on the same circuit board. Programmable delay matching to compensate for system signal skew. 10 MHz to 40 MHz input reference clock or crystal range. 50 ps max skew between any two differential clocks. Applications PC motherboard clock source. Hand-held device, PDA. PC peripherals. Printers, copiers, faxes, etc. SAN (storage area network). Storage media devices. HBA (host bus adapter). The device features four cascaded PLL synthesizers that can be programmed to create a variety of output frequencies and phases. One of the PLL synthesizers uses an external crystal reference to establish a system timing reference that is distributed to the other three PLLs. Subsequently, each of these PLL synthesizers manipulate this system timing reference through feed-forward and feedback dividers, controlled via user programmable registers. The LCK4012 is programmable via a standard two-wire I2C interface. The fast mode (up to 400 kHz) of the I2C bus specification 2.1 is supported. The slave address of the device is selectable to allow for two devices on the same I2C bus. Product Brief, Revision 1 May 31, 2005 LCK4012 Programmable High-Speed Clock Generator PLL4 200 MHz--800 MHz /5 to 130 /1 PD REFCLK_0 VCO REFCLK_1 /5 to 130 /1 to 8 VCLK HTBEN_0 10 to 40 MHz Oscillator XTAL/REFCLK PLL1 360 MHz--720 MHz /1 PD HTBEN_1 /10 to 64 even Programmable Delay HCLK_0 VCO /2 to 257 /9 or 6 to 20 even HCLK_1 HCLK_2 /1 to 8 PLL2 200 MHz--800 MHz /5 to 130 /1 PD HSYNC_0 VCO HSYNC_1 /5 to 130 NBSYNC /10 to 64 even PLL3 200 MHz--800 MHz /5 to 130 /1 /9 or 6 to 20 even GPCLK25_0 /10 to 64 even VCO /10 to 64 even /5 to 130 /10 to 64 even PD GPCLK25_1 /10 to 64 even GPCLK33_0 /10 to 64 even /10 to 64 even GPCLK33_1 /10 to 64 even PCLK12 PCLK15 PCLK25_0 PCLK25_1 SDATA ADDSEL SCLK PCLK33_0 I2C Interface To all PLLs Control & Status Registers To all Prog Div and Delay PCLK33_1 PCLK33_2 To all Output MUX Arrays PCLK33_3 RESET_N PD PCLK33_4 Power Manager ERROR_N Figure 1. LCK4012 Functional Block Diagram 2 Agere Systems Inc. Product Brief, Revision 1 May 31, 2005 LCK4012 Programmable High-Speed Clock Generator Functional Description The LCK4012 has four individually programmable clock multiplier/clock divider PLLs. Numerous output frequency combinations are attainable. There are six primary functions required for full functionality of the LCK4012 as follows: I2C interface: -- Provides access to the control/status registers where the parameters that control the PLLs are stored. PLLs: -- Four VCO-based PLLs generate all of the required output clock signals from a single crystal input: PLL1 synthesizes output clocks and is the reference clock to the other three PLLs. PLL2 synthesizes single-ended and differential output clocks and has phase delay capability. PLL3 synthesizes output clocks. PLL4 synthesizes a single differential output clock. Power manager (PowMan): -- Ensures that the LCK4012 is powered up and down gracefully. It also performs the operation of entering the LCK4012 into low-power mode by shutting down all output clocks and stopping the PLLs. PowMan also ensures that the LCK4012 wakes up from this low power mode without any glitches on the output clocks. Output multiplexer: -- Provides flexibility in routing the divided PLL outputs to the output buffers. The outputs may be reconfigured on-the-fly. Output buffers: -- Include both single-ended and differential output formats. The outputs support 3.3 V, 2.5 V, 1.5 V, and 1.2 V for single-ended outputs, and 1.5 V for differential outputs. -- Power pins associated with unused clock buffers can be left unconnected and floating in order to minimize power dissipation. Control/status registers: -- The LCK4012 supports flexible modes of operation through the use of individual control/status registers. These registers control all operational aspects of the device. Custom Buffers The LCK4012 contains two custom buffers that were designed to meet the I2C bus electrical characteristics for the SCLK and SDATA pins. These buffers are bidirectional open drain buffers with hysteresis in order to meet the standard and the fast mode specifications. External pull-up resistors should be connected to the same VDD (3.3 V or 2.5 V) used to supply voltage to the I/O buffers. A complete detailed description of the I2C interface and transfer is described in the I2C -Bus Specification, Version 2.1, January 2000. (See website: www.semiconductors.philips.com/markets/mms/protocols/I2c/) Special Features Differential clocking: -- The LCK4012 provides four differential output clocks. Three of these outputs are generated by PLL2 and the fourth is generated by PLL4. These differential clocks allow for clock frequencies of up to 800 MHz. Each output clock can be individually enabled, three of the output clocks generated from PLL2 have programmable delay elements to allow for skew matching in various system topologies. Synchronization framing pulses: -- Synchronization framing pulses are associated with the three differential clocks from PLL2. Each synchronization pulse is one clock cycle wide and occurs on every 24th clock cycle. These framing pulses also have individual programmable delay elements to allow for skew matching with the high-speed differential clocks in various system topologies. Programmable delay: -- The phase of all outputs from PLL2 may individually be delayed with respect to the other PLL outputs. Individual programmable delays range from tens of picoseconds to 7 ns in 128 steps. Agere Systems Inc. 3 LCK4012 Programmable High-Speed Clock Generator Product Brief, Revision 1 May 31, 2005 Ordering Information Table 1. Ordering Information Device Package Type Comcode LCK4012-DB L-LCK4012-DB 100-Pin FSBGA Package 700074645 700081372 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: Home: http://www.agere.com Sales: http://www.agere.com/sales E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Copyright (c) 2005 Agere Systems Inc. All Rights Reserved May 31, 2005 PB05-013LCK-1 (Replaces PB05-013LCK)