LCK4012-DB - Agere Systems, Inc.

Product Brief, Revision 1

May 31, 2005

LCK4012 Programmable High-Speed Clock Generator

Features

Flexible programming allows for output frequencies from

3.13 MHz to 800 MHz.

Twenty-one programmable output clocks at various volt-

age levels, including: 1.2 V, 1.5 V, 2.5 V, and 3.3 V.

High-speed differential clocks with divide-by-24 framing

pulse.

Limited support for 1.5 V differential ou tputs.

I2C slave interface to allow for programmability.

Low-power sleep mode:

—Clocks are individually programmed to stop or supply

the referenc e cloc k.

—Unused clock output buffers need not be powered.

—Sleep mode power as low as 0.45 mW.

Programmable delay matching to compensate for system

signal skew.

10 MHz to 40 MHz input reference clock or crystal range.

50 ps max skew between any two differential clocks.

Period jitter perfor mance:

—200 ps max at 300 MHz VCO frequency.

Package and processing:

—100-pin FS BGA package, 10 mm x 10 mm,

0.8 mm pitch.

—0.14 µm process.

Applications

PC motherboard clock source.

Hand-held device, PDA.

PC peripherals.

Printers, copiers, faxes, etc.

SAN (storage area network).

Storage media devices.

HBA (host bus adapter).

Overview

Agere Systems’ LCK4012 is a programmable timing system

that provides up to 21 programmable output clocks and

three programmable frame-synchronizing pulses generated

from a single external clock reference source.

There are three 1.5 V differential outpu t clocks (HCLK_0, 1,

2) and one 1.5 V differential output clock (VCLK), e ach pro-

grammable up to 800 MHz. Complementing these output

clocks are three divide-by-24 frame sync outputs

(HSYNC_0, 1 and NBSYNC), each with a single-ended

1.2 V level. In addition, the three HCLK clocks and the three

frame syncs support individual programmable delays rang-

ing from tens of pico seconds to 7 ns in 128 steps.

There are two 3.3 V (GPCLK33_0, 1) a nd two 2.5 V

(GPCLK25_0, 1) single-ende d output clocks that can be op-

tioned to accept up to fou r preprogr ammed freque ncy refe r-

ences. Two 1.2 V (HTBEN_0, 1) single-ended,

programmable o utput clocks have an added feature that en-

ables them to be stoppe d high as well as low . There ar e five

3.3 V (PCLK33_0, 1, 2, 3, 4) output clocks, two 2.5 V

(PCLK25_0, 1) output clocks, o ne 1.5 V (PCLK15) output

clock, and one 1.2 V (PCLK12) output clock; all can be op-

tioned to accept either of two preprogrammed frequency ref-

erences.

There are two dedicated 2.5 V (REFCLK_0, 1) single-ended

output clocks that are optioned to distribute the external

crystal frequency reference. This reference may be distrib-

uted to other frequency generation systems on the same cir-

cuit board.

The device features four cascaded PLL synthesizers that

can be programmed to create a variety of output frequen-

cies and phases. One of the PLL synthesizers uses an ex-

ternal crystal reference to establish a system timing

reference that is distributed to the othe r three PLLs. Su bse-

quently, each of these PLL synthesizers manipulate this

system timing reference through feed-forward and feed-

back dividers, controlled via user programmable registers.

The LCK4012 is progra mmable via a standard two-wire I2C

interface. The fast mode (up to 400 kHz) of the I2C bus

specification 2.1 is supported. The slave address of the de-

vice is selectable to allow for two devices on the same I2C

bus.

Product Brief, Revision 1

LCK4012 Programmable High-Speed Clock Generator May 31, 2005

22 Agere Systems Inc.

Figure 1. LCK4012 Functional Block Diagram

1 to 8

10 to 64 even

PLL4

200 MHz—800 M Hz

XTAL/REFCLK

SDATA I

Interface

Power

Manager

Control &

Status

Registers

ADDSEL

SCLK

RESET_N

REFCLK_0

REFCLK_1

HTBEN_0

HTBEN_1

GPCLK25_1

PCLK12

PCLK33_1

PCLK33_2

PCLK33_4

PCLK25_0

VCLK

HCLK_0

HCLK_1

HCLK_2

HSYNC_0

HSYNC_1

NBSYNC

ERROR_N

GPCLK33_1

To all PLLs

To all Prog Div and Delay

To all Output MUX Arrays

5 to 130

PLL1

360 MHz—720 MH z

VCO

2 to 257

PLL3

200 MHz—800 M Hz

5 to 130

PLL2

200 MHz—800 M Hz

VCO

5 to 130

PCLK15

PCLK33_0

10 to 64 even

PCLK33_3

GPCLK33_0

GPCLK25_0

PCLK25_1

Oscillator

10 to 64 even

1 to 8

9 or 6 to 20 even

5 to 130

1PD VCO

PD VCO

10 to 40 MHz

5 to 130

Programmable Delay

Product Brief, Revision 1

May 31, 2005 LCK4012 Programmable High-Speed Clock Generator

Agere Systems Inc . 3

Functional Description

The LCK4012 has four individually progra mmable clock multiplier/clock divider PL Ls. Numerous output fr equency combina-

tions are attainable. There ar e six primary functions required for full functionality of the LCK4012 as follows:

I2C interface:

—Provides access to the control/status registers where the parameters that control the PLLs are stored.

PLLs:

—Four VCO-based PLLs generate all of the required output clock signals from a single crystal input:

 PLL1 synthesizes output clocks and is the reference clock to the other three PLLs.

 PLL2 synthesizes single-ended and differential output clocks and has phase dela y capability.

 PLL3 synthesizes output clocks.

 PLL4 synthesizes a single differential output clock.

Power manager (PowMan):

—Ensures that the LCK4012 is po wered u p and down gracefully. It also performs the operation of entering the LCK4012

into low-power mode by shutting down all output clocks and stopping the PLLs. PowM an also ensur es that the

LCK4012 wakes up from this low power mode without any glitches on the output clocks.

Output multiplexer:

—Provides flexibility in routing the divided PLL outputs to the output buffers. The output s may be reconfigured on-the-fly.

Output buffers:

—Include both sin gle -e nd e d and different ial ou tp ut fo rmats. The outputs support 3.3 V, 2.5 V, 1.5 V, and 1.2 V

for single-ended outputs, and 1.5 V for differential outputs.

—Power pins associated with unused clock buffers can be left unconnected and floating in order to minimize power d is-

sipation.

Control/st atus registers:

—The LCK4012 supports flexible modes of operation through the use of individual control/status registers. These regis-

ters control all operational aspects of the device.

Custom Buffers

The LCK4012 contains two custom buffers that were designed to meet the I2C bus electrical characteristics for the SCLK

and SDATA pins. These buffers are bidirectional open drain buffe rs with hysteresis in order to meet the standard and the

fast mode specifications. External pull-up resistors should be connected to the same VDD (3.3 V or 2.5 V) used to supply

voltage to the I/O buffers.

A complete detailed description of the I2C interface and transfer is described in the I2C -Bus Specification, Version 2.1, Jan-

uary 2000. (See website: www.semiconductors.philips.com/markets/mms/protocols/I2c/)

Special Features

Differential clocking:

—The LCK4012 provides four differential output clocks. Three of these outputs are generated by PLL2 and the fourth is

generated by PLL4. These differential clocks allow for clock frequen cies of up to 800 MHz. Each output clock can be

individually enabled, three of the output clocks generated from PLL2 ha ve programmable delay elements to allow for

skew matching in various system topologies.

Synchronization framing pulses:

—Synchronization framing pulses are associated with the three differential clocks from PLL2. Each synchronization

pulse is one clock cycle wide and occurs on every 24th clock cycle. These framing pulses also have individual pro-

grammable delay elements to allow for skew matching with the high-speed differential clocks in various system topol-

ogies.

Programmable delay:

—The phase of all outputs from PLL2 may individually be delayed with respect to the other PLL outputs. Individual pro-

grammable delays range from tens of picoseconds to 7 ns in 128 steps.

May 31, 2005

PB05-013LCK-1 (Replaces PB05-013LCK)

Product Brief, Revision 1

LCK4012 Programmable High-Speed Clock Generator May 31, 2005

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc.

For additional information, contact your A gere Systems Account Manager or the following:

INTERNET: Home: http://www.agere.com Sales: http://www.agere.com/sales

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610- 712-4106)

ASIA: CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-160 0 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741- 9855, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 1344 296 400

Ordering Information

Table 1. Ordering Information

Device Package Type Comcode

LCK4012-DB 100-Pin FSBGA Package 700074645

L-LCK4012-DB 700081372