1
1
2
3
4
5
6
7
14
13
12
11
8
10
9
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
VREFH1
VREFH2
VOUT1
VOUT2
VREFL2
VREFL1
GND
1
2
3
4
5
6
7
14
13
12
11
8
10
9
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
VREFH1
VREFH2
VOUT1
VOUT2
VREFL2
VREFL1
GND
CAT522
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
FEATURES
■ Two 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
■ Independent reference inputs
■Non-volatile NVRAM memory wiper storage
■Output voltage range includes both supply rails
■2 independently addressable buffered
output wipers
■1 LSB accuracy, high resolution
■Serial Microwire-like interface
■Single supply operation: 2.7V - 5.5V
■Setting read-back without effecting outputs
APPLICATIONS
■Automated product calibration.
■Remote control adjustment of equipment
■Offset, gain and zero adjustments in self-
calibrating and adaptive control systems.
■Tamper-proof calibrations.
■DAC (with memory) substitute.
DESCRIPTION
The CAT522 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The CAT522 offers two independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail opamps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically
reinstated when power is returned. Each wiper can be
FUNCTIONAL DIAGRAM PIN CONFIGURATION
dithered to test new output values without effecting the
stored settings and stored settings can be read back
without disturbing the DPP's output.
The CAT522 is controlled with a simple 3-wire, microwire-
like serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT522 Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT522 is available in the 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges. Both 14-pin plastic DIP and surface mount
packages are available.
DIP Package (P, L) SOIC Package (J, W)
CAT522
© 2004 by Catalyst Semiconductor, Inc. Doc. No. 2004, Rev. D
Characteristics subject to change without notice
CAT522
CAT522
RDY/BSY
PROG PROGRAM
CONTROL
DI
CS
CLK SERIAL
CONTROL
SERIAL
DATA
OUTPUT
REGISTER
GND
VDD
14
7
5
2
4
V
13
12 OU
T1
OUT2
V
6DO
89
31
+
+
28kΩ
28KΩ
WIPER
CONTROL
REGISTERS
AND
NVRAM
11
10
VREFH1 VREFH2
VREFL1 VREFL2
H
A
L
O
G
E
N
F
R
E
E
TM
L
E
A
D
F
R
E
E
CAT522
2
Doc. No. 2004, Rev. D
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND............................ -0.5V to VDD +0.5V
CS to GND.............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND......................... -0.5V to VDD +0.5V
Outputs
D0 to GND............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND................... -0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µAV
DD -0.3 — — V
VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD ——10µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V
POWER SUPPLY
LOGIC OUTPUTS
CAT522
3Doc. No. 2004, Rev. D
Symbol Parameter Conditions Min Typ Max Units
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
tDIH DI Hold Time 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKHMinimum CLK High Time 500 — — ns
tCLKLMinimum CLK Low Time 300 — — ns
fCClock Frequency DC — 1 MHz
tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs
CLOAD = 10 pF, VDD = +3V — 6 10 µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
CL=100pF,
see note 1
Digital
Analog
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance 28 kΩ
RPOT to RPOT Match — +0.5 +1 %
Pot Resistance Tolerance +20 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin OV VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC ppm/˚C
RISO Isolation Resistance Ω
VNNoise nV/√Hz
CH/CLPotentiometer Capacitances 8/8 pF
fc Frequency Response Passive Attenuator MHz
CAT522
4
Doc. No. 2004, Rev. D
to1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK
t L
CLKtCSH
tCSS
tCSMIN
tDIS
tDIH
tDO0
tLZ
tDO1tHZ
RDY/BSY
tPROG
tPS
to1 2 3 4 5
tBUSY
A. C. TIMING DIAGRAM
CAT522
5Doc. No. 2004, Rev. D
PIN DESCRIPTION
Pin Name Function
1V
DD Power supply positive
2 CLK Clock input pin
3 RDY/BSY Ready/Busy output
4 CS Chip select
5 DI Serial data input pin
6 DO Serial data output pin
7 PROG EEPROM Programming Enable
Input
8 GND Power supply ground
9V
REFL1 Minimum DPP 1 output voltage
10 VREFL2 Minimum DPP 2 output voltage
11 VOUT2 DPP 2 output
12 VOUT1 DPP 1 output
13 VREFH2 Maximum DPP 2 output voltage
14 VREFH1 Maximum DPP 1 output voltage
DEVICE OPERATION
The CAT522 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost when
power is removed from the chip. Upon power up the
DPPs return to the settings stored in non-volatile memory.
Each DPP can be written to and read from independently
without effecting the output voltage during the read or
write cycle. Each output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
DIGITAL INTERFACE
The CAT522 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT522’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT522’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT522’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
DPP addressing is as follows:
DPP OUTPUT A0 A1
VOUT1 01
VOUT2 11
CAT522
6
Doc. No. 2004, Rev. D
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the configured DPP’s Zero to Full Scale output
range where VREFL = Zero and VREFH = Full Scale. VREF
can span the full power supply range or just a fraction of
it. In typical applications VREFH &VREFL are connected
across the power supply rails. When using less than the
full supply voltage be mindful of the limits placed on
VREFL and VREFL as specified in the References section
of DC Electrical Characteristics.
READY/BUSYBUSY
BUSYBUSY
BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT522 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT522, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 522s to share a
single serial data line and simplifies interfacing multiple
522s to a microprocessor.
WRITING TO MEMORY
Programming the CAT522’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programming voltage for data transfer to the non-volatile
cells. The CAT522’s non-volatile memory cells will
endure over 1,000,000 write cycles and will retain data
for a minimum of 100 years without being refreshed.
READING DATA
Each time data is transferred into a DPP control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register. Since this value is the
Figure 1. Writing to Memory Figure 2. Reading from Memory
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
CURRENT
DPP VALUE
NON-VOLATILE
DPP
OUTPUT
PROG
DO
DI
CS
NEW
DPP VALUE
VOLATILE
NEW
DPP VALUE
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
RDY/BSY
A0 A11
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DPP VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
RDY/BSY
CAT522
7Doc. No. 2004, Rev. D
Figure 3. Temporary Change in Output
same as that which had been there previously no change
in the DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then a change would occur at the read
cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT522 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the two DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all two DPPs will
return to the output values stored in non-volatile memory.
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT522’s internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
Amplified DPP Output
APPLICATION CIRCUITS
Bipolar DPP Output
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DPP VALUE
NON-VOLATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOLATILE
RDY/BSY
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF REF
IF
V = 5V
REF
255
255 OUT
DPP INPUT DPP OUTPUT ANALOG
R = R
OUTPUT
REF REF REF OUT
128
255
127
255 REF REF REF OUT
1
255 REF REF REF OUT
REF REF REF OUT
0
255
V = 0.99 V
FS REF
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DPP CODE
255 FS ZERO ZERO
CAT522
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
RR
IF
V = (1 + –––) V
OUT DPP
RF
RI
CAT522
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
V = ( ) -V
OUT RF
R +
i
-15V
+15V
+5V
RR
iF
Ri
i
RF
VDPP
For R =
iRF
V = 2V -V
OUT iDPP
Vi
VOUT
CAT522
8
Doc. No. 2004, Rev. D
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V VREF
R = —————
C 256 1 µA
VREF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
VREF
2
OFFSET
VOFFSET
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V +V
REF
-V
-V
REF
Ro
R = ———————————
C 1 µA
OFFSET
VOFFSET
REF
(+V ) - (V )
R = ———————————
o 1 µA
OFFSETREF
(-V ) + (V )
+
+
CAT522
CAT522
CAT522
LT 1029
I > 2 mA
V+
GND
VDD V = 5.000V
REF
V
REFH
V
REFL
CONTROL
& DATA
CAT522
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
15K 10 µF
5.1V
10K
4.02 K
1.00K 10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
CAT522
9Doc. No. 2004, Rev. D
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
CAT522
CAT522
Current Source with 4 Decades of Resolution
GND V
REFL
VDD V
REFH
+5V
DPP
+
–
CONTROL
& DATA
DPP
+
–
5M 5M 39 1W
39 1W
5M 5M 3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K 10K
+15V
TIP 29
BS170P
BS170P
51K
Ω
Ω
GND V
REFL
VDD V
REFH
+5V
DPP
+
–
CONTROL
& DATA
DPP
+
–
10K 10K 39 1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K 10K
TIP 30
39 1W
5M 5M 3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 µA
1 mA steps
2.2K
Ω
Ω
CAT522
10
Doc. No. 2004, Rev. D
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT522JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
522 J
Product
Number
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
-TE13
Tape & Reel
TE13:
Package
P: PDIP
J: SOIC 2000/Reel
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
CAT522
11 Doc. No. 2004, Rev. D
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2004
Revison: D
Issue date: 3/16/04
Type: Final
REVISION HISTORY
Date Rev. Reason
3/16/2004 D Updated Potentiometer Characteristics
