MediaClock™
for LCD Projectors
CY24126
PRELIMINARY
Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600
Document #: 38-07326 Rev. *A Revised December 14, 2002
1CY2295
Features Benefits
• Integrated phase-locked loop High-performance PLL tailored for projector applications
• Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs
• 3.3V operation Enables application compatibility
• 8-pin SOIC package Industry standard package saves on board space
Part Number Outputs Input Frequency Output Frequenci es
CY24126 2 24 MHz 24 MHz, 48.00 MHz/120.00 MHz (selectable)
Logic Block Diagram
XIN
XOUT OUTPUT
DIVIDERS
PLL
OSC
S0
Q
P
VCO
VDD VSS
Φ
CLK
S1
8-pin SOIC
CY24126
Pin Configurations
1
2
3
4
XOUT
XIN
S0
CLK
VSS
S1
REF
5
6
7
8
VDD Note:
1. X = don’t care.
Table 1.
XIN (MHz) S1[1] S0 CLK (MHz) Note
24.00 L L 120.00 x5
24.00 H L 48.00 x2
24.00 X H disable -
REF
CY24126
PRELIMINARY
Document #: 38-07326 Rev. *A Page 2 of 5
Pin Summ ar y
Name Pin Numbe r Description
XIN 1Reference Input (24-MHz crystal or external input)
VDD 23.3V Voltage Supply
S0 3CLK Select Line, see Table 1
VSS 4Ground
CLK 548.00 MHz/120.00 MHz (frequency selectable). See Table 1
REF 6Reference output
S1 7Clock select line, see Table 1
XOUT[2] 8Driv es an extern al crys tal
Absolute Maximum Conditions
Parameter Description Min. Max. Unit
VDD Supply Voltage –0.5 7.0 V
TSStorage Temperature[3] –65 125 °C
TJJunction Temperature 125 °C
Digital Inputs VSS – 0.3 VDD + 0.3 V
Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V
Electro-Static Discharge 2 kV
Recommended Operating Conditions
Parameter Description Min. Typ. Max. Unit
VDD Operating Voltage 3.14 3.3 3.47 V
TAAmbient Temperature 0 –70 °C
CLOAD Max. Load Capacitance ––15 pF
fREF Referen ce Freq uen cy –24 –MHz
tPU Power-up time for all VDD's to
reach minimum sp ecified vol tage
(power ramps must be m ono ton ic ) 0.05 500 ms
DC Electrical Characteristics
Parameter Name Description Min. Typ. Max. Unit
IOH Out put High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 –mA
IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 –mA
CIN Input Capacitance ––7pF
IIZ Input Leakage Current –5–µA
IDD Supply Current No output load ––35 mA
AC Electrical Characteristics (VDD = 3.3V)
Parameter[4] Name Description Min Typ Max Unit
DC Output Duty Cycle Duty Cycle is defined in Figure 1 , 50% of VDD 45 50 55 %
t3Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 –V/ns
t4Falling Edge Slew Rat e Output Cl ock Fall Time, 80% - 20% of VDD 0.8 1.4 –V/ns
t9Clock Jitter Peak to Peak period jitter ––350 ps
t10 PLL Lock Time ––3ms
CY24126
PRELIMINARY
Document #: 38-07326 Rev. *A Page 3 of 5
Notes:
2. Float XOUT if XIN is externally driven.
3. Rated for 10 years.
4. Not 10 0% tested.
MediaClock is a trademark of Cypress Semiconductor Corporation. All p roducts and comp any names mentione d in this docu ment
may be the trademarks of their respective holders.
Test Circuit
Ordering Information
Ordering Code Package Name Package Type Operating Range Operating Voltage
CY24126SC S8 8-Pin SOIC Commercial 3.3V
0.1 µF
VDD CLK out
CLOAD
GND
OUTPUTS
t1
t2
CLK 50% 50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
CY24126
PRELIMINARY
Document #: 38-07326 Rev. *A Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram 8-Lead (150-Mil) SOIC S8
51-85066-A
CY24126
PRELIMINARY
Document #: 38-07326 Rev. *A Page 5 of 5
Document Title: CY24126 MediaClock™ for LCD Projectors
Document Number: 38-07326
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 111595 03/01/02 CKN New data sheet
*A 121889 12/14/02 RBI Power up requirements added to Operating Conditions Information
