ICS9148yF-17-T - Integrated Circuit Systems, Inc.

Integrated

Circuit

Systems, Inc.

General Description Features

ICS9148-17

Block Diagram

Pentium is a trademark of Intel Corporation

I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/ProTM

9148-17 Rev G 4/27/00

Pin Configuration

 3.3V outputs: SDRAM, AGP, PCI, REF, 48/24 MHz

 2.5V or 3.3V outputs: CPU

 20 ohm CPU clock output impedance

 20 ohm PCI clock output impedance

 CPU to PCI skew = 2 to 6ns

 No external load cap for CL=18pF crystals

 250 ps max CPU, PCI clock skew

 Smooth CPU frequency transition among all CPU

frequencies.

I

2C interface for programming

 2ms power up clock stable time

 Clock duty cycle 45-55%.

 48 pin 300 mil SSOP package

 3.3V operation, 5V tolerant inputs.

48-Pin SSOP

Power Groups

VDD1 = REF (0:1), X1, X2

VDD2 = PCICLK_F, PCICLK(0:5)

VDD3 = SDRAM (0:11), supply for PLL core,

24 MHz, 48MHz

VDD4 = AGP (0:1)

VDDL = CPUCLK (0:3)

* Internal Pull-up Resistor of

240K to 3.3V on indicated inputs

The ICS9148-17 generates all clocks required for high speed

RISC or CISC microprocessor systems such as Intel PentiumPro

or Cyrix. Eight different reference frequency multiplying factors

are externally selectable with smooth frequency transitions.

Features include four CPU, six PCI, two AGP (=2xPCI) and

Twelve SDRAM clocks. Two reference outputs are available

equal to the crystal frequency. One 48 MHz for USB, and one

24 MHz clock for Super IO. Built in ±1.5%, 0.6% center or down

spread spectrum modulation to reduce EMI. Serial

programming I2C interface allows changing functions, stop

clock programing and frequency selection. Additionally, the

device meets the Pentium power-up stabilization, which

requires that CPU and PCI clocks be stable within 2ms after

power-up.

High drive PCICLK and SDRAM outputs typically provide

greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs

typically provide better than 1V/ns slew rate into 20pF loads

while maintaining 50±5% duty cycle. The REF and 24 and 48

MHz clock outputs typically provide better than 0.5V/ns slew

rates.

CPU_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

24MHz

REF (0:1)

CPUCLK (0:3)

SDRAM (0:11)

PCICLK (0:4)

PCICLK_F

XTAL

OSC

PCI

CLOCK

DIVDER

STOP

SDATA

SCLK

FS(0:2)

MODE

CPU3.3#_2.5

Control

Logic

Config.

Reg.

AGP(0:1)

LATCH

POR

PCI_STOP

CPU_STOP

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9148-17

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

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ICS9148-17

Functionality

VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C

Crystal (X1, X2) = 14.31818MHz

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CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

Power Management Functionality

Mode Pin - Power Management Input Control

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100 572346813.41

011 575.7357813.41

010 5.8652.435.86813.41

001 8.664.338.66813.41

000 060306813.41

ICS9148-17

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte

has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those

two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.

 Controller (host) sends the write address D2 (H)

 ICS clock will acknowledge

 Controller (host) sends a dummy command code

 ICS clock will acknowledge

 Controller (host) sends a dummy byte count

 ICS clock will acknowledge

 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.

 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.

 Controller (host) sends the read address D3 (H)

 ICS clock will acknowledge

 ICS clock will send the byte count

 Controller (host) acknowledges

 ICS clock sends first byte (Byte 0) through byte 5

 Controller (host) will need to acknowledge each byte

 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D3(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D2(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

ACK

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

ICS9148-17

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

I2C is a trademark of Philips Corporation

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ICP

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PGA

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1tiB lamroN-0 delbanEmurtcepSdaerpS-1 0

0tiB gninnuR-0 stuptuollaetatsirT-1 0

Note 1. Default at Power-up will be for latched logic inputs

to define frequency. Bits 4, 5, 6 are default to 000,

and if bit 3 is written to a 1 to use bits 6:4, then

these should be defined to desired frequency at same

write cycle.

Note: PWD = Power-Up Default

ICS9148-17

Byte 3: SDRAM Active/Inactive Register

(1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB821 )tcanI/tcA(7MARDS

6tiB921 )tcanI/tcA(6MARDS

5tiB131 )tcanI/tcA(5MARDS

4tiB231 )tcanI/tcA(4MARDS

3tiB431 )tcanI/tcA(3MARDS

2tiB531 )tcanI/tcA(2MARDS

1tiB731 )tcanI/tcA(1MARDS

0tiB831 )tcanI/tcA(0MARDS

Byte 4: SDRAM Active/Inactive Register

(1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register

(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency selects will be Inverted logic level of

the input frequency select pin conditions.

tiB#niPDWPnoitpircseD

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5tiB-1 )devreseR(

4tiB-1 )devreseR(

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2tiB811 )tcanI/tcA(01MARDS )ylnOedoMpotkseD(

1tiB021 )tcanI/tcA(9MARDS

0tiB121 )tcanI/tcA(8MARDS

tiB#niPDWPnoitpircseD

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6tiB-1 )devreseR(

5tiB-1 )devreseR(

4tiB741 )tcanI/tcA(1PGA

3tiB-1 )devreseR(

2tiB-1 )devreseR(

1tiB641 )tcanI/tcA(1FER

0tiB21 )tcanI/tcA(0FER

Byte 1: CPU, Active/Inactive Register

(1 = enable, 0 = disable)

Byte 2: PCI Active/Inactive Register

(1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

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6tiB-1 )devreseR(

5tiB-1 )devreseR(

4tiB-1 )devreseR(

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2tiB141 )tcanI/tcA(2KLCUPC

1tiB341 )tcanI/tcA(1KLCUPC

0tiB441 )tcanI/tcA(0KLCUPC

tiB#niPDWPnoitpircseD

7tiB-- #1SFdehctaL

6tiB71 )tcanI/tcA(F_KLCICP

5tiB511 )tcanI/tcA(0PGA

4tiB411 )tcanI/tcA(4KLCICP

3tiB211 )tcanI/tcA(3KLCICP

2tiB111 )tcanI/tcA(2KLCICP

1tiB011 )tcanI/tcA(1KLCICP

0tiB81 )tcanI/tcA(0KLCICP

ICS9148-17

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.

CPU_STOP# is synchronized by the ICS9148-17. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100

CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in

a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4

CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:

1. All timing is referenced to the internal CPU clock.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized

to the CPU clocks inside the ICS9148-17.

3. All other clocks except CPU and AGP clocks continue to run undisturbed.

ICS9148-17

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9148-17. It is used to turn off the PCICLK (0:5) clocks for low power operation.

PCI_STOP# is synchronized by the ICS9148-17 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#

high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse

width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-running)

CPU_STOP#

(High)

PCICLK

(External)

PCI_STOP#

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the ICS9148.

3. All other clocks continue to run undisturbed.

ICS9148-17

Fig. 1

Shared Pin Operation -

Input/Output Pins

The I/O pins designated by (input/output) on the ICS9148-17

serve as dual signal functions to the device. During initial

power-up, they act as input pins. The logic level (voltage)

that is present on these pins at this time is read and stored

into a 5-bit internal data latch. At the end of Power-On reset,

(see AC characteristics for timing values), the device changes

the mode of operations for these pins to an output function.

In this mode the pins produce the specified buffered clocks

to external loads.

To program (load) the internal configuration register for these

pins, a resistor is connected to either the VDD (logic 1) power

supply or the GND (logic 0) voltage potential. A 10 Kilohm

(10K) resistor is used to provide both the solid CMOS

programming voltage needed during the power-up

programming period and to provide an insignificant load on

the output clock during the subsequent operating period.

Via to

VDD

Clock trace to load

Series Term. Res.

Programming

Header

Via to Gnd

Device

Pad

2K W

8.2K W

Figure 1 shows a means of implementing this function when

a switch or 2 pin header is used. With no jumper is installed

the pin will be pulled high. With the jumper in place the pin

will be pulled low. If programmability is not necessary, than

only a single resistor is necessary. The programming resistors

should be located close to the series termination resistor to

minimize the current loop area. It is more important to locate

the series termination resistor close to the driver than the

programming resistor.

ICS9148-17

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage VIH 2V

DD+0.3 V

Input Low Voltage VIL VSS-0.3 0.8 V

Input High Current IIH VIN = VDD 0.1 5 µA

Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 2.0 µA

Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 -100 µA

Operating IDD3.3OP CL = 0 pF; 66.8 MHz 100 160 mA

Supply Current

Input frequency FiVDD = 3.3 V; 14.318 MHz

Input Capacitance1CIN Logic Inputs 5 pF

CINX X1 & X2 pins 27 36 45 pF

Transition Time1Ttrans To 1st crossing of target Freq. 2 ms

Settling Time1TsFrom 1st crossing to 1% target Freq. ms

Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 2 ms

Skew1TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads -500 200 500 ps

TCPU-PCI1 VT = 1.5 V; CPU Leads 256ns

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating IDD2.5OP CL = 0 pF; 66.8 MHz 10 20 mA

Supply Current

TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads -500 200 500 ps

TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads 256ns

1Guaranteed by design, not 100% tested in production.

Skew1

ICS9148-17

Electrical Characteristics - CPU

TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH2A IOH = -28 mA 2.5 2.6 V

Output Low Voltage VOL2A IOL = 27 mA 0.35 0.4 V

Output High Current IOH2A VOH = 2.0 V -29 -23 mA

Output Low Current IOL2A VOL = 0.8 V 33 37 mA

Rise Time tr2A1VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns

Fall Time tf2A1VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns

Duty Cycle dt2A1VT = 1.5 V 45 50 55 %

Skew tsk2A1VT = 1.5 V 50 250 ps

Jitter, One Sigma tj1s2A1VT = 1.5 V 65 150 ps

Jitter, Absolute tjabs2A1VT = 1.5 V -250 165 250 ps

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - CPU

TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH2B IOH = -8 mA 2 2.2 V

Output Low Voltage VOL2B IOL = 12 mA 0.3 0.4 V

Output High Current IOH2B VOH = 1.7 V -20 -16 mA

Output Low Current IOL2B VOL = 0.7 V 19 26 mA

Rise Time tr2B1VOL = 0.4 V, VOH = 2.0 V 1.5 1.8 ns

Fall Time tf2B1VOH = 2.0 V, VOL = 0.4 V 1.6 1.8 ns

Duty Cycle dt2B1VT = 1.25 V 40 47 55 %

Skew tsk2B1VT = 1.25 V 60 250 ps

Jitter, Single Edge

Displacement2tjsed2B1VT = 1.25 V 200 250 ps

Jitter, One Sigma tj1s2B1VT = 1.25 V 65 150 ps

Jitter, Absolute tjabs2B1VT = 1.25 V -300 160 300 ps

1 Guaranteed by design, not 100% tested in production.

2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.

ICS9148-17

Electrical Characteristics - PCI

TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH1 IOH = -28 mA 2.4 3 V

Output Low Voltage VOL1 IOL = 23 mA 0.2 0.4 V

Output High Current IOH1 VOH = 2.0 V -60 -40 mA

Output Low Current IOL1 VOL = 0.8 V 41 50 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 1.8 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns

Duty Cycle dt11VT = 1.5 V 45 51 55 %

Skew tsk11VT = 1.5 V 130 250 ps

Jitter, One Sigma1tj1s1a VT = 1.5 V, synchronous 40 150 ps

tj1s1b VT = 1.5 V, asynchronous 200 250 ps

Jitter, Absolute1tabs1a VT = 1.5 V, synchronous -250 135 250 ps

tjabs1b VT = 1.5 V, asynchronous -650 500 650 ps

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - SDRAM

TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH1 IOH = -28 mA 2.4 3 V

Output Low Voltage VOL1 IOL = 23 mA 0.2 0.4 V

Output High Current IOH1 VOH = 2.0 V -60 -40 mA

Output Low Current IOL1 VOL = 0.8 V 41 50 mA

Rise Time1Tr1 VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns

Fall Time1Tf1 VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns

Duty Cycle1Dt1 VT = 1.5 V 45 50 55 %

Skew1Tsk1 VT = 1.5 V 200 500 ps

Jitter, One Sigma1Tj1s1 VT = 1.5 V 50 150 ps

Jitter, Absolute1Tjabs1 VT = 1.5 V (with synchronous PCI) -250 +250 ps

Jitter, Absolute1Tjabs1 VT = 1.5 V (with asynchronous PCI) -400 400 ps

1Guaranteed by design, not 100% tested in production.

ICS9148-17

Electrical Characteristics - AGP

TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH1 IOH = -28 mA 2.4 3 V

Output Low Voltage VOL1 IOL = 23 mA 0.2 0.4 V

Output High Current IOH1 VOH = 2.0 V -60 -40 mA

Output Low Current IOL1 VOL = 0.8 V 41 50 mA

Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 1.1 2 ns

Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 1 2 ns

Duty Cycle dt11VT = 1.4 V 45 49 55 %

Skew tsk11VT = 1.5 V 130 250 ps

Jitter, One Sigma1t

1s1 VT = 1.5 V 2 3 %

Jitter, Absolute1tabs1a VT = 1.5 V, synchronous -5 2.5 5 %

tjabs1b VT = 1.5 V, asynchronous -6 4.5 6 %

1Guaranteed by design, not 100% tested in production.

Electrical Characteristics - 24MHz, 48MHz, REF0

TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage VOH5 IOH = -16 mA 2.4 2.6 V

Output Low Voltage VOL5 IOL = 9 mA 0.3 0.4 V

Output High Current IOH5 VOH = 2.0 V -32 -22 mA

Output Low Current IOL5 VOL = 0.8 V 16 25 mA

Rise Time tr51VOL = 0.4 V, VOH = 2.4 V 2 4 ns

Fall Time tf51VOH = 2.4 V, VOL = 0.4 V 1.9 4 ns

Duty Cycle dt51VT = 1.5 V 455457%

Jitter, One Sigma tj1s51VT = 1.5 V 1 3 %

Jitter, Absolute tjabs51VT = 1.5 V -5 - 5 %

1Guaranteed by design, not 100% tested in production.

ICS9148-17

General Layout Precautions:

1) Use a ground plane on the top layer

of the PCB in all areas not used by

traces.

2) Make all power traces and vias as

wide as possible to lower inductance.

Notes:

1 All clock outputs should have series

terminating resistor. Not shown in all

places to improve readibility of

diagram

2 Optional EMI capacitor should be

used on all CPU, SDRAM, and PCI

outputs.

3 Optional crystal load capacitors are

recommended.

Capacitor Values:

C1, C2 : Crystal load values determined by user

C3 : 100pF ceramic

All unmarked capacitors are 0.01µF ceramic

ICS9148-17

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

Ordering Information

ICS9148yF-17-T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T