ICS9161A-01CN16LF - Integrated Device Technology

Integrated

Circuit

Systems, Inc.

General Description Features

ICS9161A

9161

0210I—03/21/05

Block Diagram

Dual Programmable Graphics Frequency Generator

The ICS9161A is a fully programmable graphics clock

generator. It can generate user-specified clock

frequencies using an externally generated input

reference or a single crystal. The output frequency is

programmed by entering a 24-bit digital word through

the serial port. Two fully user-programmable phase-

locked loops are offered in a single package. One PLL

is designed to drive the memory clock, while the

second drives the video clock. The outputs may be

changed on-the-fly to any desired frequency between

390 kHz and 120 MHz. The ICS9161A is ideally suited

for any design where multiple or varying frequencies

are required.

This part is ideal for graphics applications. It generates

low jitter, high speed pixel clocks. It can be used to replace

multiple, expensive high speed crystal oscillators. The

flexibility of the device allows it to generate non-standard

graphics clocks.

The ICS9161A is also ideal in disk drives. It can generate

zone clocks for constant density recording schemes. The low

profile, 16-pin SOIC or PDIP package and low jitter outputs

are especially attractive in board space critical disk drives.

The leader in the area of multiple output clocks on a single

chip, ICS has been shipping graphics frequency generators

since October, 1990, and is constantly improving the

phase-locked loop. The ICS9161A incorporates a patented

fourth generation PLL that offers the best jitter performance

available.

• Pin-for-pin and function compatible with ICD2061A

• Dual programmable graphics clock generator

• Memory and video clocks are individually

programmable on-the-fly

• Ideal for designs where multiple or varying

frequencies are required

• Increased frequency resolution from optional pre-

divide by 2 on the M counter

• Output enable feature available for tristating outputs

• Independent clock outputs range from 390 kHz to

120 MHz for VDD >4.75V

• Power-down capabilities

• Low power, high speed 0.8µ CMOS technology

• Glitch-free transitions

• Available in 16-pin, 300-mil SOIC or PDIP package

EXTCLK EXTSEL

VCO OUTPUT

DIVIDER

R=1,2,4,8,16

32,64,128

VCO CMOS

OUTPUT

DRIVER

MCLK

VCO

DIVIDE

(N÷)

VCO OUTPUT

DIVIDER

R=1,2,4,8,16

32,64,128

VCO

REF

DIVIDE

(M÷) MUX

CMOS

OUTPUT

DRIVER VCLK

D14-D20

7D0-D3

D11-D13

REF

D14-D20

D4-D10

D0-D3

D11-D13

MCLK

(D0-D20)

VCLK

(D0-D20)

REGISTERS

ADDRESS

INIT

ROM

POR

INIT1

INIT2

SEL0-CLK

SEL1-DATA

DECODE

LOGIC

DATA

CONTROL REG

XTAL

OSC

3-TO-1

MUX

Pscale

P=2or4

REF

DIVIDE

(M÷)

D4-D10

VCO

DIVIDE

(N÷)

Pscale

P= 2

ICS9161A

0210I—03/21/05

Pin Descriptions

Pin Configuration

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16-Pin 300- mil SOIC or PDIP

ICS9161A

0210I—03/21/05

The register file consists of the following six registers:

As seen in the VCLK Selection table, OE acts to tristate

the output. The PD# pin forces the VCLK signal high while

powering down the part. The EXTCLK pin will only be

multiplexed in when EXTSEL and SEL0 are logic 0 and

SEL1 is a logic 1.

The memory clock outputs are controlled by PD# and

OE as follows:

The Clock Select pins SEL0 and SEL1 have two purposes.

In serial programming mode, these pins act as the clock

and data pins. New data bits come in on SEL1 and these

bits are clocked in by a signal on SEL0. While these pins

are acquiring new information, the VCLK signal remains

unchanged. When SEL0 and SEL1 are acting as register

selects, a time-out interval is required to determine whether

the user is selecting a new register or wants to program the

part. During this initial time-out, the VCLK signal remains

at its previous frequency. At the end of this time-out

interval, a new register is selected. A second time-out

interval is required to allow the VCO to settle to its new

value. During this period of time, typically 5ms, the input

reference signal is multiplexed to the VCLK signal.

When MCLK or the active VCLK register is being re-

programmed, then the reference signal is multiplexed

glitch-free to the output during the first time-out interval. A

second time-Register out interval is also required to allow

the VCO to settle. During this period, the reference signal

is multiplexed to the appropriate output signal.

The ICS9161A places the three video clock registers and

the memory clock register in a known state upon power-

up. The registers are initialized based on the state of the

INIT1 and INIT0 pins at application of power to the device.

The INIT pins must ramp up with VDD if a logical 1 on either

pin is required. These input pins are internally pulled down

and will default to a logical 0 if left unconnected.

The registers are initialized as follows:

When the ICS9161A is operating, the video clock output

is controlled with a combination of the SEL0, SEL1, PD#

and OE pins. The video clock is also multiplexed to an

external clock (EXTCLK) which can be selected with the

EXTSEL pin. The VCLK Selection Table shows how VCLK

is selected.

VCLK Selection

1TINI0TINIGERM0GER1GER2GER

005.23

000.04

053.05

446.65

571.52

000.04

223.82

053.05

223.82

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100

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110

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ICS9161A

0210I—03/21/05

Control Register Definitions

The control register allows the user to adjust various internal options. The register is defined as follows:

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ICS9161A

0210I—03/21/05

Serial Programming Architecture

The pins SEL0 and SEL1 perform the dual functions of

select-ing registers and serial programming. In serial

programming mode, SEL0 acts as a clock pin while SEL1

acts as the data pin. The ICS9161A-01 may not be serially

programmed when in power-down mode.

In order to program a particular register, an unlocking

sequence must occur. The unlocking sequence is detailed

in the following timing diagram:

Serial Data Register

The serial data is clocked into the serial data register in the

order described in Figure 1 below (Serial Data Timing).

The serial data is sent as follows: An individual data bit is

sampled on the rising edge of CLK. The complement of the

data bit must be sampled on the previous falling edge of

CLK. The setup and hold time requirements must be met

on both CLK edges. For specifics on timing, see the timing

diagrams on pages 10, 11 and 12.

The bits are shifted in this order: a start bit, 21 data bits,

3 address bits (which designate the desired register), and

a stop bit. A total of 24 bits must always be loaded into the

serial data register or an error is issued. Following the entry

of the last data bit, a stop bit or load command is issued

by bringing DATA high and toggling CLK high-to-low and

low-to-high. The unlocking mechanism then resets itself

following the load. Only after a time-out period are the

SEL0 and SEL1 pins allowed to return to a register

selection function.

Since the VCLK registers are selected by the SEL0 and

SEL1 pins, and since any change in their state may affect

the output frequency, new data input on the selection bits

is only permitted to pass through the decode logic after the

watchdog timer has timed out. This delay of SEL0 or SEL1

data permits a serial program cycle to occur without

affecting the current register selection.

The unlock sequence consists of at least five low-to-high

transitions of CLK while data is high, followed immediately

by a single low-to-high transition while data is low. Following

this unlock sequence, data can be loaded into the serial

data register. This programming must include the start bit,

shown in Figure 1.

Following any transition of CLK or DATA, the watchdog

timer is reset and begins counting. The watchdog timer

ensures that successive rising edges of CLK and DATA do

not violate the time-out specification of 2ms. If a time-out

occurs, the lock mechanism is reset and the data in the

serial data register is ignored.

Figure 1: Serial Data Timing

ICS9161A

0210I—03/21/05

The serial data register is exactly 24 bits long, enough to

accept the data being sent. The stop bit acts as a load

command that passes the contents of the Serial Data

bits. If a stop bit is not received after the serial register is

full, and more data is sent, all data in the register is ignored

and an error issued. If correct data is received, then the

unlocking mechanism re-arms, all data in the serial data

ERROUT# Operation

Any error in programming the ICS9161A is signaled by

ERROUT#. When the pin goes low, an error has been

detected. It stays low until the next unlock sequence. The

signal is invoked for any of the following errors: incorrect

start bit, incorrect data encoding, incorrect length of data

word, and incorrect stop bit.

Programming the ICS9161A

The ICS9161A has a wide operating range, but it is

recommended that it is operated within the following limits:

4.75V< VDD <5.25V VDD supply voltage

1 MHz <FREF <60 MHz FREF=Input Reference

Frequency

200 kHz <FREF/M <5 MHz M=Reference divide 3

to 129

50 MHz < FVCO <120 MHz FVCO=VCO output

frequency

FCLK ≤ 120 MHz FCLK=output frequency

The frequency of the programmable oscillator FVCO is

determined by the following fields:

The equations used to determine the oscillator frequency

are:

N=N’ + 3 M=M’ + 2

FVCO=Prescale • N/M • FREF

where 3 ≤ M ≤ 129 and 4 ≤ N ≤ 130

and prescale=2 or 4, as set in the control register

(Where N is the VCO divider & M is the reference

divider)

The value of FVCO must remain between 50 MHz and 120

MHz. As a result, for output frequencies below 50 MHz,

FVCO must be brought into range. To achieve this, an

output divisor is selected by setting the values of the Mux

Field (R) as follows:

Where the least significant bit is the last bit of M and the

most significant bit is the first bit of I.

Output Divisor

Unlike the ICD2061A, the ICS9161A’s VCO does not

require tuning to place it in certain ranges. The ICS9161A’s

VCO will operate from 50 MHz to 120 MHz without

adjusting the VCO gain. However, to maintain compatibility,

the I bits are programmed as in the ICD2061A.

These bits are dummy bits except for the following two

cases:

Index Field (I)

When the index field is set to 1111, VCLK is turned off and

both channels run from the same MCLK VCO. This is done

in an effort to reduce jitter, which may increase when

VCOs run at 2n multiples of one another. If the two outputs

have to be multiples of one another, it is best to mux MCLK

over to the output of the VCLK VCO and to power-down the

VCLK VCO. The multiplexed frequency will be divided

down by the correct divisor (M) and output on VCLK.

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101

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ICS9161A

0210I—03/21/05

Power Management Issues

Power-down mode 1

The ICS9161A contains a mechanism to reduce the

quiescent power when stand-by operation is desired.

Power-down mode 1 is invoked by polling PD# low and

having the proper CNTL register bit set to zero. In this

mode, VCOs are shut down, the VCLK output is forced

high, and the MCLK output is set to a user-defined low

frequency value to refresh dynamic RAM.

The power-down MCLK value is determined by the following

equation:

MCLKPD = FREF/(PWRDWN register divisor value)

The power-down register divisor is determined according

to the 4-bit word programmed into the PWRDWN register

(see table below).

Power-down mode 2

When there is no need for any output during power-down,

an alternate mode is available which will completely shut

down all outputs and the reference oscillator, but still

preserves all register contents. Power-down mode 2 in

invoked by first programming the power-down bit in the

CNTL register and then pulling the PD# pin low.

The PD# pin

The PD# pin has a standard internal pull-up resistor during

normal operation. When the chip goes into power-down

mode 1 or 2, the normal pull-up resistor is dynamically

switched to a weak pull-up, which reduces power

consumption. If the PD# pin is allowed to float after it has

been pulled

down, the weak pull-up will bring the signal high and allow

the device to resume operation.

Power-Down Register Table

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zHM91.1

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zHM85.3

ICS9161A

0210I—03/21/05

Absolute Maximum Ratings

Note

1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

VDD referenced to GND ..........................................7V

Operating temperature under bias (TOPER) ..............0°C to 70°C

Storage temperature ...............................................-40°C to +150°C

Max. soldering temperature (10 sec) (TSOL) ............+260°C

Voltage on I/O pins referenced to GND ...................GND -0.5V to VDD +0.5V

Junction temperature (Tj) ........................................+125°C

Power dissipation ....................................................0.35 Watts

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect product reliability.

Electrical Characteristics at 5.0V

VDD = +5V ± 5%, 0°C ≤ TAMBIENT ≤ +70°C

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ICS9161A

0210I—03/21/05

Electrical Characteristics at 5.0V (continued)

Notes:

1. Parameter guaranteed by design and characterization. Not 100% tested in production.

2. For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally.

3. Duty cycle is measured at CMOS threshold levels. At 5 volts, VTH=2.5 volts.

4. If the interval is too short, see the time-out interval section in the control register definition.

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ICS9161A

0210I—03/21/05

Rise and Fall Times

Tristated Timing

ICS9161A

0210I—03/21/05

Selection Timing

MCLK and Active VCLK Register Programming Timing

ICS9161A

0210I—03/21/05

Soft Power-Down Timing (Mode 2)

Serial Programming Timing

ICS9161A

0210I—03/21/05

General Layout Precautions:

1) Use a ground plane on the top layer

of the PCB in all areas not used by

traces.

2) Make all power traces and vias as

wide as possible to lower inductance.

Notes:

1) All clock outputs should have series

terminating resistor. Not shown in

all places to improve readibility of

diagram.

2) 47 ohm / 56pf RC termination

should be used on all over 50MHz

outputs.

3) Optional crystal load capacitors are

recommended.

Capacitor Values:

C1, C2 : Crystal load values determined by user

C3 : 100pF ceramic

All unmarked capacitors are 0.01µF ceramic

Connections to VDD:

ICS9161A

0210I—03/21/05

Ordering Information

ICS9161A-01CN16LF

Example:

ICS XXXX - PPP M X#WLF

Prefix

ICS, AV=Standard Device

Device Type (consists of 3 or 4 digit numbers)

Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)

Package Type

N=DIP (Plastic)

Lead Count & Package Width

Lead Count=1, 2 or 3 digits

W=.3” SOIC or .6” DIP; None=Standard Width

16-Pin PDIP Package

Annealed Lead Free (Optional)

ICS9161A

0210I—03/21/05

SOIC Package (wide body)

Ordering Information

ICS9161A-01CW16

Example:

TNUOCDAELL61

LNOISNEMID404.0

ICS XXXX - PPP M X#WLF

Prefix

ICS, AV=Standard Device

Device Type (consists of 3 or 4 digit numbers)

Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)

Package Type

M=SOIC

Lead Count & Package Width

Lead Count=1, 2 or 3 digits

W=.3” SOIC or .6” DIP; None=Standard Width

Annealed Lead Free (Optional)