LH28F008SA * High-Density Symmetrically Blocked Architecture - Sixteen 64K Blocks * Extended Cycling Capability - 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles per Chip * Automated Byte Write and Block Erase - Command User Interface - Status Register * System Performance Enhancements - RY/BY Status Output - Erase Suspend Capability * Deep-Powerdown Mode - 0.20 A ICC Typical * Access Times: 85/120 ns * SRAM-Compatible Write Interface * Hardware Data Protection Feature - Erase/Write Lockout During Power Transitions * Industry Standard Packaging - 44-Lead SOP - 40-Lead TSOP * ETOX TM 1 Non-volatile Flash Technology - 12 V Byte Write/Block Erase * Independent Software Vendor Support - Microsoft 2 Flash File System (FFS) 1 2 3 8M (1M x 8) Flash Memory DESCRIPTION SHARP's LH28F008SA 8M Flash FileTM 3 Memory is the highest density non-volatile read/write solution for solid state storage. The LH28F008SA's extended cycling, symmetrically blocked architecture, fast access time, write automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The LH28F008SA brings new capabilities to portable computing. Application and operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high density data acquisition applications, the LH28F008SA offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of the LH28F008SA's non-volatility, blocking and minimal system code requirements for flexible firmware and modular software designs. The LH28F008SA is offered in 40-lead TSOP (standard) package. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The LH28F008SA memory map consists of 16 separately erasable 64 Kbyte blocks. SHARP's LH28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 85 ns access time provides superior performance when compared with magnetic storage media. A deep powerdown mode lowers power consumption to 1 W typical thru VCC, crucial in portable computing, hand-held instrumentation and other lowpower applications. The PWD power control input also provides absolute data protection during system powerup/down. ETOX is a trademark of Intel Corporation. Microsoft is a trademark of Microsoft Corporation. Flash File is a trademark of Intel Corporation. 7-41 LH28F008SA PRODUCT OVERVIEW The LH28F008SA is a hi gh-perform ance 8M (8,388,608 bit) memory organized as 1M (1,048,576 bytes) of 8 bits each. Sixteen 64K (65,536 byte) blocks are included on the LH28F008SA. A memory map is shown in Figure 4 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can be independently erased and written 100,000 cycles. Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the LH28F008SA. The LH28F008SA is available in the 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick) package. Pinouts are shown in Figure 2 of this specification. The Command User Interface serves as the interface between the microprocessor or microcontroller and the internal operation of the LH28F008SA. Byte Write and Block Erase Automation allow byte write and block erase operations to be executed using a two-write command sequence to the Command User Interface. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in byte increments typically within 9 s, an 80% improvement over current flash memory products. Ipp byte write and block erase currents are 10 mA typical, 30 mA maximum. Vpp byte write and block erase voltage is 11.4 V to 12.6 V. 7-42 8M (1M x 8) Flash Memory The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation. The RY/BY output gives an additional indicator of WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). Status polling using RY/BY minimizes both CPU overhead and system power consumption. When low, RY/BY indicates that the WSM is performing a block erase or byte write operation. RY/BY high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. Maximum access time is 85 ns (tACC) over the commercial temperature range (0C to +70C) and over VCC supply voltage range (4.5 V to 5.5 V and 4.75 V to 5.25 V). ICC active current (CMOS Read) is 20 mA typical, 35 mA maximum at 8 MHz. When the CE and PWD pins are at V CC, the ICC CMOS Standby mode is enabled. A Deep Powerdown mode is enabled when the PWD pin is at GND, minimizing power consumption and providing write protection. ICC current in deep powerdown is 0.20 A typical. Reset time of 400 ns is required from PWD switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1 s from PWD high until writes to the Command User Interface are recognized by the LH28F008SA. With PWD at GND, the WSM is reset and the Status Register is cleared. A0 - A19 X-DECODER ADDRESS LATCH ADDRESS COUNTER Y-DECODER INPUT BUFFER OUTPUT MULTIPLEXER OUTPUT BUFFER 16 64 KBYTE BLOCKS Y-GATING DATA COMPARATOR STATUS REGISTER IDENTIFIER REGISTER INPUT BUFFER DATA A REGISTER DQ0 - DQ7 WRITE STATE MACHINE COMMAND USER INTERFACE PROGRAM/ERASE VOLTAGE SWITCH I/O LOGIC GND VCC VPP RY/BY PWD OE WE CE 8M (1M x 8) Flash Memory LH28F008SA Figure 1. Block Diagram 7-43 8M (1M x 8) Flash Memory LH28F008SA Table 1. Pin Description Symbol A0 - A19 DQ0 - DQ7 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. INPUT/OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during Command User Interface write cycles; outputs data during memory array, Status Register and Identifier read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CE INPUT CHIP ENABLE: Activates the device's control logic input buffers decoders, and sense amplifiers. CE is active low; CE high deselects the memory device and reduces power consumption to standby levels. PWD INPUT POWERDOWN: Puts the device in deep powerdown mode. PWD is active low; PWD high gates normal operation. PWD also locks out block erase or byte write operations when active low, providing data protection during power transitions. OE INPUT OUTPUT ENABLE: Gates the device's outputs through the data buffers during a read cycle. OE is active low. WE INPUT WRITE ENABLE: Controls writes to the Command User Interface and array blocks. WE is active low. Addresses and data are latched on the rising edge of the WE pulse. RY/BY 7-44 Name and Function Type OUTPUT READY/BUSY: Indicates the status of the internal Write State Machine. When low, it indicates that the WSM is performing a block erase or byte write operation. RY/BY high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. RY/BY is always active and does NOT float to tri-state off when the chip is deselected or data outputs are disabled. VPP BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of the array or writing bytes of each block. NOTE: With VPP < VPPLMAX, memory contents cannot be altered. VCC DEVICE POWER SUPPLY (5V10%, 5V5%) GND GROUND 8M (1M x 8) Flash Memory LH28F008SA Standard Pinout A19 A18 A17 A16 A15 A14 A13 A12 CE VCC VPP PWD A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 STANDARD PINOUT LH28F008SAT 40 LEAD TSOP 10mm x 20 mm TOP VIEW 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC WE OE RY/BY DQ 7 DQ 6 DQ 5 DQ 4 V CC GND GND DQ 3 DQ 2 DQ 1 DQ 0 A0 A1 A2 A3 Figure 2. TSOP Lead Configuration 7-45 8M (1M x 8) Flash Memory GND VCC 16 64 KBYTE BLOCKS Y-GATING DATA COMPARATOR STATUS REGISTER X-DECODER ADDRESS LATCH ADDRESS COUNTER Y-DECODER INPUT BUFFER A0 - A19 OUTPUT BUFFER OUTPUT MULTIPLEXER DQ0 - DQ7 IDENTIFIER REGISTER DATA A REGISTER INPUT BUFFER COMMAND USER INTERFACE WRITE STATE MACHINE I/O LOGIC PROGRAM/ERASE VOLTAGE SWITCH VPP RY/BY PWD OE WE CE LH28F008SA Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus (Including RY/BY Masking and Selective Powerdown), for DRAM Backup During System SUSPEND, Resident O/S and Applications and Motherboard Solid-State Disk 7-46 8M (1M x 8) Flash Memory PRINCIPLES OF OPERATION LH28F008SA FFFFF The LH28F008SA includes on-chip write automation to manage write and erase functions. The Write State Machine allows for: 100% TTL-level control inputs; fixed power supplies during block erasure and byte write; and minimal processor overhead with SRAM-like interface timings. F0000 EFFFF After initial device powerup, or after return from deep powerdown mode (see Bus Operations), the LH28F008SA functions as a read-only memory. Manipulation of external memory-control pins allow array read, standby and output disable operations. Both Status Register and intelligent identifiers can also be accessed through the Command User Interface when VPP = VPPL. C0000 BFFFF This same subset of operations is also available when high voltage is applied to the VPP pin. In addition, high voltage on V PP enables successful block erasure and byte writing of the device. All functions associated with altering memory contents - byte write, block erase, status and intelligent identifier - are accessed via the Command User Interface and verified thru the Status Register. Commands are written using standard microprocessor write timings. Command User Interface contents serve as input to the WSM, which controls the block erase and byte write circuitry. Write cycles also internally latch addresses and data needed for byte write or block erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output byte write and block erase status for verification. Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the LH28F008SA blocks. This code is copied to, and executed from, system RAM during actual flash memory update. After successful completion of byte write and/or block erase, code/data reads from the LH28F008SA are again possible via the Read Array command. Erase suspend/resume capability allows system software to suspend block erase to read data and execute code from any other block. E0000 DFFFF D0000 CFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 64 Kbyte Block 00000 Figure 4. Memory Map Command User Interface and Write Automation An on-chip state machine controls block erase and byte write, freeing the system processor for other tasks. After receiving the Erase Setup and Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the Status Register and RY/BY output. Byte write is similarly controlled, after destination address and expected data are supplied. The program and erase algorithms of past standard Flash memories are now regulated by the state machine, including pulse repetition where required and internal verification and margining of data. 7-47 8M (1M x 8) Flash Memory LH28F008SA The first task is to write the appropriate read mode command to the Command User Interface (array, intelligent identifier, or Status Register). The LH28F008SA automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown. The LH28F008SA has four control pins, two of which must be logically active to obtain data at the outputs. Chip Enable (CE) is the device selection control, and when active enables the selected memory device. Output Enable (OE) is the data input/output (DQ0-DQ7) direction control, and when active drives data from the selected memory onto the I/O bus. PWD and WE must also be at VIH. Figure 8 illustrates read bus cycle waveforms. Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory byte writes/block erases are required) or hardwired to VPPH. When VPP = VPPL, memory contents cannot be altered. The LH28F008SA Command User Interface architecture provides protection from unwanted byte write or block erase operations even when high voltage is applied to V PP. Additionally, all functions are disabled whenever VCC is below the write lockout voltage VLKO , or when PWD is at V IL. The LH28F008SA accommodates either design practice and encourages optimization of the processor-memory interface. Output Disable The two-step byte write/block erase Command User Interface write sequence provides additional software write protection. With OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ7) are placed in a high-impedance state. BUS OPERATION Standby Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. CE at a logic-high level (VIH) places the LH28F008SA in standby mode. Standby operation disables much of the LH28F008SA's circuitry and substantially reduces device power consumption. The outputs (DQ0-DQ7) are placed in a high-impedance state independent of the status of OE. If the LH28F008SA is deselected during block erase or byte write, the device will continue functioning and consuming normal active power until the operation completes. Read The LH28F008SA has three read modes. The memory can be read from any of its blocks, and information can be read from the intelligent identifier or Status Register. V PP can be at either V PPL or VPPH. Table 2. Bus Operations Notes PWD CE OE WE A0 VPP DQ0-7 RY/BY 1, 2, 3 VIH VIL VIL VIH X X DOUT X Output Disable 3 VIH VIL VIH VIH X X High Z X Standby 3 VIH VIH X X X X High Z X Deep PowerDown VIL X X X X X High Z VOH Intelligent Identifier (Mfr) VIH VIL VIL VIH VIL X 89H VOH Intelligent Identifier (Device) VIH VIL VIL VIH VIH X A2H VOH VIH VIL VIH VIL X X DIN X Mode Read Write 3, 4, 5 NOTES: 1. Refer to DC Characteristics. When VPP = VPPL, memory contents can be read but not written or erased. 2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH voltages. 3. RY/BY is VOL when the Write State Machine is executing internal block erase or byte write algorithms. It is VOH when the WSM is not busy, in Erase Suspend mode or deep powerdown mode. 4. Command writes involving block erase or byte write are only successfully executed when VPP = VPPH. 5. Refer to Table 3 for valid DIN during a write operation. 7-48 8M (1M x 8) Flash Memory LH28F008SA Deep Power-Down Intelligent Identifier Operation The LH28F008SA offers a deep powerdown feature, entered when PWD is at V IL. Current draw thru VCC is 0.20 A typical in deep powerdown mode, with current draw through VPP typically 0.1 A. During read modes, PWD-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. The LH28F008SA requires time tPHQV (see AC Characteristics-Read-Only Operations) after return from powerdown until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The Command User Interface is reset to Read Array, and the upper 5 bits of the Status Register are cleared to value 10000, upon return to normal operation. The intelligent identifier operation outputs the manufacturer code, 89H; and the device code, A2H for the LH28F008SA. The system CPU can then automatically match the device with its proper block erase and byte write algorithms. The manufacturer- and device-codes are read via the Command User Interface. Following a write of 90H to the Command User Interface, a read from address location 00000H outputs the manufacturer code (89H). A read from address 00001H outputs the device code (A2H). It is not necessary to have high voltage applied to VPP to read the intelligent identifiers from the Command User Interface. During block erase or byte write modes, PWD low will abort either operation. Memory contents of the block being altered are no longer valid as the data will be partially written or erased. Time tPHWL after PWD goes to logic-high (VIH) is required before another command can be written. Write Writes to the Command User Interface enable reading of device data and intelligent identifiers. They also control inspection and clearing of the Status Register. Additionally, when VPP = VPPH, the Command User Interface controls block erasure and byte write. The contents of the interface register serve as input to the internal state machine. Table 3. Command Definitions Command Bus Cycles Req'd First Bus Cycle Notes Second Bus Cycle Operation Address Data Operation Address Data Read Array/Reset 1 1 Write X FFH Intelligent Identifier 3 2, 3, 4 Write X 90H Read IA IID Read Status Register 2 3 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Erase Setup/Erase Confirm 2 2 Write BA 20H Write X D0H Byte Write Setup/Write 2 2, 3, 5 Write WA 40H Write WA WD Alternate Byte Write Setup/Write 2 2, 3, 5 Write WA 10H Write WA WD NOTES: 1. Bus operations are defined in Table 2. 2. IA = Identifier Address: 00H for manufacturer code, 01H for device code. BA = Address within the block being erased. WA = Address of memory location to be written. 3. SRD = Data read from Status Register. See Table 4 for a description of the Status Register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE. IID = Data read from intelligent identifiers. 4. Following the intelligent identifier command, two read operations access manufacture and device codes. 5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command. 6. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 7-49 8M (1M x 8) Flash Memory LH28F008SA The Command User Interface itself does not occupy an addressable memory location. The interface register is a latch used to store the command and address and data information needed to execute the command. Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased. The Byte Write Setup command requires both appropriate command data and the address of the location to be written, while the Byte Write command consists of the data to be written and the address of the location to be written. The Command User Interface is written by bringing WE to a logic-low level (VIL) while CE is low. Addresses and data are latched on the ri sing edge of WE. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the AC Waveforms for Write Operations, Figure 9, for specific timing parameters. COMMAND DEFINITIONS When VPPL is applied to the VPP pin, read operations from the Status Register, intelligent identifiers, or array blocks are enabled. Placing VPPH on VPP enables successful byte write and block erase operations as well. Read Array Command Upon initial device powerup and after exit from deep powerdown mode, the LH28F008SA defaults to Read Array mode. This operation is also initiated by writing FFH into the Command User Interface. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the Command User Interface contents are altered. Once the internal Write State Machine has started a block erase or byte write operation, the device will not recognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional when V PP = VPPL or VPPH. Intelligent Identifier Command The LH28F008SA contains an intelligent identifier operation, initiated by writing 90H into the Command User Interface. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H. To terminate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the intelligent identifier command is functional when VPP = VPPL or VPPH. Device operations are selected by writing specific commands into the Command User Interface. Table 3 defines the LH28F008SA commands. Table 4. Status Register Definitions SR.7 = SR.6 = SR.5 = SR.4 = SR.3 = WSMS ESS ES BWS VPPS R R R 7 6 5 4 3 2 1 0 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy ERASE SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase in Progress/Completed ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase BYTE WRITE STATUS (BWS) 1 = Error in Byte Write 0 = Successful Byte Write VPP STATUS (VPPS) 1 = VPP Low Detect; Operation Abort 0 = VPP OK NOTES: RY/BY or the Write State Machine Status bit must first be checked to determine byte write or block erase completion, before the Byte Write or Erase Status bit are checked for success. If the Byte Write AND Erase Status bits are set to "1"s during a block erase attempt, an improper command sequence was entered. Attempt the operation again. If VPP low status is detected, the Status Register must be cleared before another byte write or block erase operation is attempted. The V PP Status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH. SR.2 - SR.0 = RESERVED FOR FUTURE (R) ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register. 7-50 8M (1M x 8) Flash Memory Read Status Register Command The LH28F008SA contains a Status Register which may be read to determine when a byte write or block erase operation is complete, and whether that operation completed successfully. The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command User Interface. After writing this command, all subsequent read operations output data from the Status Register, until another valid command is written to the Command User Interface. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle. OE or CE must be toggled to VIH before further reads to update the Status Register latch. The Read Status Register command functions when V PP = V PPL or VPPH. Clear Status Register Command The Erase Status and Byte Write Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register Command. These bits indicate various failure conditions (see Table 4). By allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). The Status Register may then be polled to determine if an error occurred during that sequence. This adds flexibility to the way the device may be used. Additionally, the VPP Status bit (SR.3) MUST be reset by system software before further byte writes or block erases are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the Command User Interface. The Clear Status Register command is functional when VPP = VPPL or V PPH. Erase Setup/Erase Confirm Commands Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the Command User Interface, followed by the Erase Confirm command (D0H). These commands require both appropriate sequencing and an address within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After the two-command erase sequence is written to it, the LH28F008SA automatically outputs Status Register data when read (see Figure 6; Block Erase Flowchart). The CPU can detect the completion of the erase event by analyzing the output of the RY/BY pin, or the WSM Status bit of the Status Register. When erase is completed, the Erase Status bit should be checked. If erase error is detected, the Status Register should be cleared. The Command User Interface LH28F008SA remains in Read Status Register mode until further commands are issued to it. This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, reliable blockerasure can only occur when VPP = VPPH. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while VPP = VPPL, the VPP Status bit will be set to "1". Erase attempts while VPPL <VPP <VPPH produce spurious results and should not be attempted. Erase Suspend/Erase Resume Commands The Erase Suspend command allows block erase interruption in order to read data from another block of memory. Once the erase process starts, writing the Erase Suspend command (B0H) to the Command User Interface requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The LH28F008SA continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to "1"). RY/BY will also transition to VOH. At this point, a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase process. The Erase Suspend Status and WSM Status bits of the Status Register will be automatically cleared and RY/ BY will return to VOL. After the Erase Resume command is written to it, the LH28F008SA automatically outputs Status Register data when read (see Figure 7; Erase Suspend/Resume Flowchart). VPP must remain at VPPH while the LH28F008SA is in Erase Suspend. Byte Write Setup/Write Commands Byte write is executed by a two-command sequence. The Byte Write Setup command (40H) is written to the Command User Interface, followed by a second write specifying the address and data (latched on the rising edge of WE) to be written. The WSM then takes over, controlling the byte write and write verify algorithms internally. After the two-command byte write sequence is written to it, the LH28F008SA automatically outputs Status Register data when read (see Figure 5; Byte Write Flowchart). The CPU can detect the completion of the byte write event by analyzing the output of the RY/BY pin, or the WSM Status bit of the Status Register. Only the Read Status Register command is valid while byte write is active. 7-51 LH28F008SA When byte write is complete, the Byte Write Status bit should be checked. If byte write error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The Command User Interface remains in Read Status Register mode until further commands are issued to it. If byte write is attempted while VPP = VPPL, the VPP Status bit will be set to "1". Byte write attempts while VPPL <VPP <VPPH produce spurious results and should not be attempted. EXTENDED BLOCK ERASE/ BYTE WRITE CYCLING The LH28F008SA is designed for 100,000 byte write/ block erase cycles on each of the sixteen 64K blocks. Low electric fields, advanced oxides and minimal oxide area per cell subjected to the tunneling electric field combine to greatly reduce oxide stress and the probability of failure. A 20M solid-state drive using an array of LH28F008SAs has a MTBF (Mean Time Between Failure) of 33.3 million hours(1), over 600 times more reliable than equivalent rotating disk technology. AUTOMATED BYTE WRITE The LH28F008SA integrates the Quick-Pulse programming algorithm using the Command User Interface, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register. WSM operation, internal verify and VPP high voltage presence are monitored and reported via the RY/BY output and appropriate Status Register bits. Figure 5 shows a system software flowchart for device byte write. The entire sequence is performed with VPP at VPPH. Byte write abort occurs when PWD transitions to VIL, or V PP drops to VPPL. Although the WSM is halted, byte data is partially written at the location where byte write was aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value. AUTOMATED BLOCK ERASE As above, the Quick-Erase algorithm is now implemented internally, including all preconditioning of block data. WSM operation, erase success and V PP high voltage presence are monitored and reported through RY/BY and the Status Register. Additionally, if a command other than Erase Confirm is written to the device following Erase Setup, both the Erase Status and Byte Write Status bits will be set to "1"s. When issuing the Erase Setup and Erase Confirm commands, they 8M (1M x 8) Flash Memory should be written to an address within the address range of the block to be erased. Figure 6 shows a system software flowchart for block erase. Erase typically takes 1.6 seconds per block. The Erase Suspend/Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. A system software flowchart is shown in Figure 7. The entire sequence is performed with VPP at V PPH. Abort occurs when PWD transitions to VIL or V PP falls to VPPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. DESIGN CONSIDERATIONS Three-Line Output Control The LH28F008SA will often be used in large memory arrays. Intel provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE, while OE should be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode. Finally, PWD should either be tied to the system RESET, or connected to VCC if unused. RY/BY and Byte Write/Block Erase Polling RY/BY is a full CMOS output that provides a hardware method of detecting byte write and block erase completion. It transitions low time tWHRL after a write or er ase com m and se quen ce is wr it t en to th e LH28F008SA, and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY can be connected to the interrupt input of the system CPU or controller. It is active at all times, not tristated if the LH28F008SA CE or OE inputs are brought to V IH. RY/BY is also VOH when the device is in Erase Suspend or deep powerdown modes. (1) Assumptions: 10K file written every 10 minutes. (20M array)/(10K file) = 2,000 file writes before erase required. (2000 files writes/erase) x (100,000 cycles per LH28F008SA block) = 200 million file writes. 6 6 (200 x 10 file writes) x (10 min/write) x (1 hr/60 min) = 33.3 x 10 MTBF. 7-52 8M (1M x 8) Flash Memory LH28F008SA Bus Operation Start Write 40H (10H), Byte Address Command Write Byte Write Setup Data = 40H (10H) Address = Byte to be written Write Byte Write Data to be written Address = Byte to be written Write Byte Address/Data Check RY/BY VOH = Ready, VOL = Busy or Standby/Read WSM Ready? Comments NO Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to update Status Register YES Full Status Check if Desired Repeat for subsequent bytes Full status check can be done after each byte or after a sequence of bytes Byte Write Completed Write FFH after the last byte write operation to reset the device to Read Array Mode FULL STATUS CHECK PROCEDURE Status Register Data Read (See Above) SR.3=0 ? NO VPP Range Error YES SR.4=0 ? YES Byte Write Successful NO Byte Write Error Bus Operation Command Comments Optional Read CPU may already have read Status Register data in WSM Ready polling above Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4 1 = Byte Write Error SR.3 MUST be cleared, if set during a byte write attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register Command, in cases where multiple bytes are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 5. Automated Byte Write Flowchart 7-53 8M (1M x 8) Flash Memory LH28F008SA Bus Operation Start Command Write Erase Setup Data = 20H Address = Within block to be erased Write Erase Data = D0H Address = Within block to be erased Write 20H, Block Address Write D0H Block Address Check RY/BY VOH = Ready, VOL = Busy or Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to update Status Register Standby/Read NO WSM Ready? NO Suspend Erase? Erase Suspend Loop YES YES Full Status Check if Desired Comments Repeat for subsequent bytes Full status check can be done after each block or after a sequence of blocks Block Erase Completed Write FFH after the last block erase operation to reset the device to Read Array Mode FULL STATUS CHECK PROCEDURE Status Register Data Read (See Above) NO SR.3=0 ? VPP Range Error YES SR.4,5=1 ? YES Command Sequence Error Bus Operation Command Comments Optional Read CPU may already have read Status Register data in WSM Ready polling above Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error NO SR.5=0 ? YES Block Erase Successful NO Block Erase Error SR.3 MUST be cleared, if set during a block erase attempt, before further attempts are allowed by the Write State Machine. SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 6. Automated Block Erase Flowchart 7-54 8M (1M x 8) Flash Memory LH28F008SA Start Bus Operation Command Write Erase Suspend Data = B0H Write Read Status Register Data = 70H Write B0H Comments Write 70H Standby/ Read Check RY/BY VOH = Ready, VOL = Busy or Read Status Register Read Status Register SR.7=1 ? Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to Update Status Register NO YES SR.6=1 ? Check SR.6 1 = Suspended Standby NO YES Write Read Array Read Read array data from block other than that being erased. Write FFH Done Reading? Data = FFH Erase Has Completed Write NO Erase Resume Data = D0H YES Write D0H Continue Erase Figure 7. Erase Suspend/Resume Flowchart Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in 3 supply current issues; standby current levels (ISB), active current levels (ICC) and transient peaks produced by falling and rising edges of CE. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to package leads. Additionally, for every 8 devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. VPP Trace on Printed Circuit Boards Writing flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for writing and erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP Supply traces and decoupling will decrease VPP voltage spikes and overshoots. 7-55 8M (1M x 8) Flash Memory LH28F008SA VCC, VPP, PWD Transitions and the Command/Status Registers Byte write and block erase completion are not guaranteed if VPP drops below VPPH. If the VPP Status bit of the Status Register (SR.3) is set to "1", a Clear Status Register command MUST be issued before further byte write/block erase attempts are allowed by the WSM. Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to "1"s if error is detected. PWD transitions to VIL during byte write and block erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or PWD transitions to VIL, clear the Status Register to initial value 10000 for the upper 5 bits. The Command User Interface latches commands as issued by system software and is not altered by VPP or CE transitions or WSM actions. Its state upon powerup, after exit from deep powerdown or after VCC transitions below VLKO, is Read Array Mode. After byte write or block erase is complete, even after V PP transitions down to VPPL, the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired. Power Up/Down Protection The LH28F008SA is designed to offer protection against accidental block erasure or byte writing during power transitions. Upon power-up, the LH28F008SA is indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the LH28F008SA ensures that the Command User Interface is reset to the Read Array mode on power up. 7-56 A system designer must guard against spurious writes for V CC voltages above VLKO when VPP is active. Since both WE and CE must be low for a command write, driving either to VIH will inhibit writes. The Command User Interface architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. Finally, the device is disabled until PWD is brought to VIH, regardless of the state of its control inputs. This provides an additional level of memory protection. Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash non-volatility increases usable battery life, because the LH28F008SA does not consume any power to retain code or data when the system is off. In addition, theLH 28F008SA's deep powerdown mode ensures extremely low power dissipation even when system power is applied. For example, portable PCs and other power sensitive applications, using an array of LH28F008SAs for solid-state storage, can lower PWD to VIL in standby or sleep modes, producing negl igi ble p ower consum pt ion. I f acce ss to t he LH28F008SA is again needed, the part can again be read, following the tPHQV and tPHWL wakeup cycles required after PWD is first raised back to VIH. See AC Characteristics - Read-Only and Write Operations and Figures 8 and 9 for more information. 8M (1M x 8) Flash Memory LH28F008SA ABSOLUTE MAXIMUM RATINGS* Operating Temperature During Read 0C to +70C (1) During Block Erase/Byte Write 0C to +70C Temperature Under Bias -10C to +80C Storage Temperature -65C to +125C Voltage on Any Pin (except VCC and VPP) with Respect to GND -2.0 V to +7.0 V(2) VPP Program Voltage with Respect to GND during Block Erase/Byte Write -2.0 V to +14.0 V (2, 3) VCC Supply Voltage with Respect to GND -2.0 V to +7.0 V(2) Output Short Circuit Current 100 mA(4) * WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is - 0.5 V on input/output pins. During transitions, this level may undershoot to - 2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to + 14.0 V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. 5% VCC specifications reference the LH28F008SA-85 in its High Speed configuration. 10% VCC specifications reference the LH28F008SA-85 in its Standard configuration, and the LH28F008SA-12. OPERATING CONDITIONS Symbol Parameter Notes Min Max Unit 0 70 C TA Operating Temperature V CC V CC Supply Voltage (10%) 5 4.50 5.50 V V CC V CC Supply Voltage (5%) 5 4.75 5.25 V DC CHARACTERISTICS Symbol Parameter Notes Min Typ Max Unit Test Condition ILI Input Load Current 1 1.0 A V CC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 10 A VCC = VCC Max VOUT = VCC or GND ICCS VCC Standby Current 1.0 2.0 mA VCC = VCC Max CE = PWD = VIH 30 100 A VCC = VCC Max CE = PWD = VCC 0.2 V 1, 3 ICCD VCC Deep PowerDown Current 1 0.20 1.2 A PWD = GND 0.2 V IOUT (RY/BY) = 0 mA ICCR VCC Read Current 1 20 35 mA VCC = VCC Max, CE = GND f = 8 MHz, IOUT = 0 mA CMOS Inputs 25 50 mA VCC = VCC Max, CE = VIL f = 8 MHz, IOUT = 0 mA TTL Inputs 7-57 8M (1M x 8) Flash Memory LH28F008SA DC CHARACTERISTICS (Continued) Symbol Parameter Notes Min Typ Max Unit Test Condition ICCW VCC Byte Write Current 1 10 30 mA Byte Write In Progress ICCE VCC Block Erase Current 1 10 30 mA Block Erase In Progress ICCES VCC Erase Suspend Current 1, 2 5 10 mA Block Erase Suspended CE = VIH IPPS VPP Standby Current 1 1 10 A VPP VCC 90 200 A VPP VCC IPPD VPP Deep PowerDown Current 1 0.10 5.0 A PWD = GND 0.2 V IPPW VPP Byte Write Current 1 10 30 mA VPP = VPPH Byte Write in Progress IPPE VPP Block Erase Current 1 10 30 mA VPP = VPPH Block Erase in Progress IPPES VPP Erase Suspend Current 1 90 200 A VPP = VPPH Block Erase Suspended VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage 3 0.45 V VCC = VCC Min IOL = 5.8 mA VOH Output High Voltage 3 2.4 V VCC = VCC Min IOH = - 2.5 mA VPPL VPP during Normal Operations 4 0.0 VPPH VPP during Erase/Write Operations 11.4 VLKO VCC Erase/Write Lock Voltage 2.0 12.0 6.5 V 12.6 V V CAPACITANCE (5) TA = 25C, f = 1 MHz Symbol Parameter Typ Max CIN Input Capacitance 6 8 COUT Output Capacitance 8 12 Unit pF pF Condition VIN = 0V VOUT = 0V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25C. These currents are valid for all product versions (package and speeds). 2. I CCES is specified with the device deselected. If the LH28F008SA is read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR. 3. Includes RY/BY. 4. Block Erases/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 5. Sampled, not 100% tested. 7-58 8M (1M x 8) Flash Memory LH28F008SA AC INPUT/OUTPUT REFERENCE WAVEFORM (1) AC TESTING LOAD CIRCUIT(1) 1.3V 2.4 2.0 INPUT 2.0 0.45 1N914 OUTPUT TEST POINTS 0.8 0.8 RL DEVICE UNDER TEST AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. OUT CL C L = 100 pF C L Includes Jig Capacitance R L = 3.3 k HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM (2) HIGH SPEED AC TESTING LOAD CIRCUIT(2) 1.3V 3.0 1.5 INPUT 1.5 TEST POINTS OUTPUT 1N914 0.0 RL DEVICE UNDER TEST AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) <10 ns. OUT CL C L = 30 pF C L Includes Jig Capacitance R L = 3.3 k NOTES: 1. Testing characteristics for LH28F008SA-85 in Standard configuration, and LH28F008SA-12. 2. Testing characteristics for LH28F008SA-85 in High Speed configuration. AC CHARACTERISTICS - Read-Only Operations (1) VCC 5% Versions Symbol LH28F008SA-85 VCC 10% Parameter Notes tAVAV tRC Read Cycle Time tAVQV tACC Address to Output Delay tELQV tCE CE to Output Delay tPHQV tPWH PWD High to Output Delay tGLQV tOE OE to Output Delay 2 tELQX tLZ CE to Output Low Z 3 tEHQZ tHZ CE High to Output High Z 3 tGLQX tOLZ OE to Output Low Z 3 tGHQZ tDF OE High to Output High Z 3 tOH Output Hold from Addresses, CE or OE Change,Whichever is First 3 (4) LH28F008SA-85 Min Max 85 2 Min Max LH28F008SA-12 (5) Unit Min Max 90 ns 120 85 90 120 ns 85 90 120 ns 400 400 400 ns 40 45 50 ns 0 0 55 0 0 55 0 30 0 (5) 55 0 30 0 ns ns ns 30 0 ns ns NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load circuits for testing characteristics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. 7-59 7-60 Figure 8. AC Waveform for Read Operations PWD (P) VCC DATA (D/Q) WE (W) OE (G) CE (E) ADDRESSES (A) VIL VIH GND 5.0 V VOL VOH VIL VIH VIL VIH VIL VIH VIL VIH HIGH Z VCC POWER-UP STANDBY tPHQV tAVQV tELQX tELQV DEVICE AND ADDRESS SELECTION tGLQX tGLQV tAVAV VALID OUTPUT DATA VALID ADDRESSES STABLE OUTPUTS ENABLED tOH tGHQZ tEHQZ STANDBY HIGH Z VCC POWER-DOWN LH28F008SA 8M (1M x 8) Flash Memory 8M (1M x 8) Flash Memory LH28F008SA AC CHARACTERISTICS - Write Operations(1) VCC 5% Versions Symbol Parameter tWC Write Cycle Time tPHWL tPS PWD High Recovery to WE Going Low tCS (8) LH28F008SA-85 VCC 10% tAVAV tELWL (7) LH28F008SA-85 Notes Min Max CE Setup to WE Going Max Unit Min Max 90 120 ns 1 1 s 10 10 10 ns 40 40 40 ns 85 2 Min (8) LH28F008SA-12 1 Low tWLWH tWP WE Pulse Width tVPWH tVPS VPP Setup to WE Going High 2 100 100 100 ns tAVWH tAS Address Setup to WE Going 3 40 40 40 ns 4 40 40 40 ns High tDVWH tDS Data Setup to WE Going High tWHDX tDH Data Hold from WE High 5 5 5 ns tWHAX tAH Address Hold from WE High 5 5 5 ns tWHEH tCH CE Hold from WE High 10 10 10 ns tWHWL tWPH WE Pulse Width High 30 30 30 ns tWHRL WE High to RY/BY Going Low tWHQV1 Duration of Byte Write Operation 5, 6 6 6 6 tWHQV2 Duration of Block Erase Operation 5, 6 0.3 0.3 0.3 s tWHGL Write Recovery before Read 0 0 0 s 0 0 tQVVL tVPH VPP Hold from Valid SRD, 100 2, 6 100 100 0 ns s ns RY/BY High NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measure to completion (SR.7 = 1, RY/BY = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0). 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. 7-61 8M (1M x 8) Flash Memory LH28F008SA BLOCK ERASE AND BYTE WRITE PERFORMANCE LH28F008SA-12 LH28F008SA-85 Parameter Notes Min Typ (1) Max Min Unit Typ(1) Max Block Erase Time 2 1.6 10 1.6 10 s Block Write Time 2 0.6 2.1 0.6 2.1 s NOTES: 1. 25C, 12.0 VPP. 2. Excludes System-Level Overhead. ORDERING INFORMATION L H 2 8 F 0 0 8 S A T - 8 5 PACKAGE T = STANDARD 40 LEAD TSOP ACCESS SPEED 85=85 ns 12=120 ns 7-62 VPP (V) VIL VIH VOL VOH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VPPL VIH VPPH PWD (P) RY/BY (R) DATA (D/Q) WE (W) OE (G) CE (E) ADDRESSES (A) tPHWL HIGH Z tDVWH tELWL VCC POWER-UP AND STANDBY tWLWH DIN tAVAV AIN WRITE BYTE WRITE OR ERASE SETUP COMMAND tWHDX tWHWL tWHEH tVPWH tAVWH DIN AIN tWHRL tWHAX WRITE VALID ADDRESS AND DATA (BYTE WRITE) OR ERASE CONFIRM COMMAND tWHQV1, 2 tWHGL AUTOMATED BYTE WRITE OR ERASE DELAY tQVVL VALID SRD READ STATUS REGISTER DATA DIN WRITE READ ARRAY COMMAND 8M (1M x 8) Flash Memory LH28F008SA Figure 9. AC Waveform for Write Operations 7-63 8M (1M x 8) Flash Memory LH28F008SA ALTERNATIVE CE-CONTROLLED WRITES VCC 5% Versions Symbol (6) LH28F008SA-85 LH28F008SA-85 VCC 10% Parameter tAVAV tWC Write Cycle Time tPHEL tPS PWD High Recovery to Notes 2 Min Max Min Max (7) (7) LH28F008SA-12 Unit Min Max 85 90 120 ns 1 1 1 s 0 0 0 ns 50 50 50 ns CE Going Low tWLEL tWS WE Setup to CE Going Low tELEH tCP CE Pulse Width tVPEH tVPS VPP Setup to CE Going High 2 100 100 100 ns tAVEH tAS Address Setup to CE Going 3 40 40 40 ns 4 40 40 40 ns High tDVEH tDS Data Setup to CE Going High tEHDX tDH Data Hold from CE High 5 5 5 ns tEHAX tAH Address Hold from CE High 5 5 5 ns tEHWH tWH WE Hold from CE High 0 0 0 ns tEHEL tEPH CE Pulse Width High 25 25 25 ns tEHRL CE High to RY/BY Going Low tEHQV1 Duration of Byte Write Operation 5 6 6 6 tEHQV2 Duration of Block Erase Operation 5 0.3 0.3 0.3 s tEHGL Write Recovery before Read 0 0 0 s 0 0 tQVVL tVPH VPP Hold from Valid SRD, 100 2, 5 100 100 0 ns s ns RY/BY High NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE. In systems where CE defines the write pulsewidth (within a longer WE timing waveform), all setup, hold and inactive WE times should be measured relative to the CE waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0). 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. 7-64 VPP (V) VIL VIH VOL VOH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VPPL VIH VPPH PWD (P) RY/BY (R) DATA (D/Q) CE (E) OE (G) WE (W) ADDRESSES (A) tPHEL HIGH Z tDVEH tWLEL VCC POWER-UP AND STANDBY tELEH DIN tAVAV AIN WRITE BYTE WRITE OR ERASE SETUP COMMAND tEHDX tEHEL tEHWH tVPEH tAVEH DIN AIN tEHRL tEHAX WRITE VALID ADDRESS AND DATA (BYTE WRITE) OR ERASE CONFIRM COMMAND tEHQV1, 2 tEHGL AUTOMATED BYTE WRITE OR ERASE DELAY tQVVL VALID SRD READ STATUS REGISTER DATA DIN WRITE READ ARRAY COMMAND 8M (1M x 8) Flash Memory LH28F008SA Figure 10. Alternate AC Waveform for Write Operations 7-65 8M (1M x 8) Flash Memory LH28F008SA PACKAGE DIAGRAMS 44-Lead SOP 7-66 8M (1M x 8) Flash Memory LH28F008SA 40-Lead TSOP (Type I) 7-67 8M (1M x 8) Flash Memory LH28F008SA ORDERING INFORMATION LH28F008SA Device Type X Package -## Speed 85 ns 120 ns N 44-pin SOP T 40-pin TSOP (Type I) 8M Dual Volt (5/12) Flash Memory Example: LH28F008SAT-85 (8M Dual Volt (5/12) Flash Memory, 85 ns, 40-pin TSOP (Type I)) FLASH-1 7-68