LH28F008SA 8 M (1M × 8) Flas h Memory
•• High-Density Symmetrical ly Block ed
Architecture
– Sixteen 64K Blo cks
•• Ex te nde d Cycl ing C ap abi lity
– 10 0,000 Bl ock Erase C ycles
– 1.6 Mil lion Block Erase Cycle s per Ch ip
•• Automated Byte Write and Block Erase
– Co mma nd U ser In te rfa ce
– Statu s Reg ister
•• Syste m Performance Enhancements
– RY/BY Status Outp ut
– Erase Su spen d Ca pab ili ty
•• Dee p-Pow erdo wn Mo de
– 0.20 µA ICC Typic al
•• Access Times: 8 5/120 n s
•• SRAM-Co mpatib le Write Interface
•• Hard ware Data Protectio n Fe ature
– Erase /Write L ockou t During Powe r
Transitions
•• In dustry Stand ard Packa gin g
– 44 -L ea d SOP
– 40-Lead TSOP
•• ETOX TM 1 N on-vo latile Fl ash Techn olo gy
– 12 V Byte Write/Blo ck Era se
•• Indep en dent Software Vendor Sup port
– Microso ft 2 Flash File System (FFS)
DESCRIPTION
SH ARP ’s LH 28F008S A 8M Fl ash FileTM 3 Memory is
the hi ghest density n on-vola ti le read/wri te sol ution for
solid state storage. The LH28F008SA’s extended
cycling, symmetrically blocked ar chitecture, fast access
time, write automation and low power consumption
provide a more reliable, l o wer p ower, lighter weight and
higher performance alternative to traditional rotating
disk technology. The LH28F008SA brings new capabili-
ties to portable computing. Appli cation and operating
system software stored in resident flash memory arrays
provide instant-on rapid execute-in-place and protec-
tion from obsolescence through in-system software
updates. Resident software also extends system bat-
tery life and increases reliability by reducing disk drive
accesses.
For high density data acquisition applications, the
LH28F008SA offers a m ore cost-e ffective and reliable
alternative to SRAM and battery. Traditional high density
embedded applications, su ch a s telecommun ications,
can t ake advantage of the LH28F008SA’s non-volatility ,
blocking and minimal system code requirements for
flexi ble fi rmware and modul a r software designs.
The LH28F008SA i s o ffered in 40-lead TSOP (stand-
ard) package. Pin assignments simplify board layout
when integrating multiple devices in a flash memory
array or subsystem. This device uses an integrated
C om mand User I nter face and st ate machine f or simpli-
fied block erasure and byte write. The LH28F008SA
memory map consists of 16 separately erasable 64
Kbyte blocks.
SHARP’s LH28F008SA employs advanced CMOS
circui try for systems requi rin g low power consump tion
and noise immunity. Its 85 ns access time provides
superior performance when compared with magnetic
storage media. A deep powerdown mode lo wers power
consumption to 1 µW t ypical thr u V CC, crucial in portable
computing, hand-held instrumentation and other low-
power applications. The PWD power control input also
provides absolute data protection during system
powerup/down.
1 ETOX is a trademar k of Intel Cor poration.
2 Microsoft is a t rademark of Microsoft Cor poration.
3 Flash F ile is a trademark of Inte l Corporat ion.
7-41
PRO DUCT OVERVIEW
The LH28F008SA is a high-performance 8M
(8,388,608 bit) memory organized as 1M (1,048,576
bytes) of 8 bits each. Sixteen 64K (65, 536 byt e) blocks
are included on the LH28F008SA. A memory map is
shown in Figure 4 of this specification. A block erase
operation erases one o f the sixteen blocks of memory
in typically 1.6 seconds, independent of the remaining
blocks. Each block can be independently erased and
written 100,000 cycles. Erase Suspend mode allows
system software to suspend block erase to read data
or execute code from any other block of the
LH28F008SA.
The LH28F008SA is available in the 40-lead TSOP
(Thi n Small Ou tline P ackage, 1 .2 mm thi ck) package.
P inouts are shown in Fi gure 2 of this specification.
The Command User Interface serves as the interface
between the microprocessor or microcont roller and t he
internal operation of the LH28F008SA.
Byte Write and Block Erase Automation allow byte
w rite and block erase operations to be execute d using
a t wo-write comm and sequence t o t he Command User
Interface. The internal Write State Machine (WSM)
automatically execut es t he a lgorithm s and timings nec-
essary for byte write and block erase operations,
including verifications, thereby unburdening the micro-
processor or microcontr oller . W riting of m emory data is
performed in byte i ncrements typ icall y wi thi n 9 µs, an
80% improvement over cur rent f lash m emory products.
Ipp byte write and block erase currents are 10 mA
typical, 30 mA maximum. Vpp byte wr ite and block
erase voltage is 11.4 V to 12.6 V.
T he Status R egister indicat es the status of t he WSM
and when the WSM successf u lly com plet es the desired
byte write o r block erase ope ration.
T he RY/BY output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase, for
example). Status polling using RY/BY minimizes both
C PU over he ad and system po wer consumption. W hen
low, RY/BY indicates that the WSM is performing a
block erase or byte write operation. RY/BY hi gh indi-
c ates t hat t he WSM is ready f or new com mands, b lock
er ase is suspended or the device is in deep powerdown
mode.
Maximum access time is 85 ns (tACC) over the com-
mercial temper ature range ( 0° C to + 70°C) and over VCC
s upply voltage range (4. 5 V to 5.5 V an d 4. 75 V to 5.25
V) . ICC active current (CMOS Read) is 20 mA typical,
35 mA maximum at 8 MHz.
Whe n the CE and PWD pins are at VCC, the ICC CMOS
Standby mode i s enabled.
A Deep Powerdown mode is e nab led when the PWD
pin is at GND, minimizing power consumption and pro-
v idi ng write protect ion. ICC current in deep powerdown
is 0.20 µA typical. Reset time of 400 ns is required
from PWD switching high until outputs are valid to read
attempts. Equivalently , the device ha s a w ake time of
1 µs from PWD high until writes to the Command User
Interface are recognized by the LH28F008SA. With
PWD at GND, the WSM is reset and the Stat us Register
is cleared.
LH28F008S A 8M (1M × 8) F la sh Memory
7-42
INPUT
BUFFER
ADDRESS
LATCH
ADDRESS
COUNTER
Y-DECODER
X-DECODER
Y-GATING WRITE STATE
MACHINE PROGRAM/ERASE
VOLTAGE SWITCH
COMMAND
USER
INTERFACE
OUTPUT
BUFFER INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
16
64 KBYTE
BLOCKS
I/O LOGIC
CE
WE
OE
PWD
RY/BY
VPP
VCC
GND
DQ0 - DQ7
A0 - A19
OUTPUT
MULTIPLEXER
DATA A
REGISTER
Fi gur e 1. Block Dia gram
8M (1M × 8) Flash Memory LH28F008SA
7-43
Table 1. Pin Description
Name and Function
GROUND
GND
DEVICE POWER SUPPLY (5V±10%, 5V±5%)
V
CC
BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of
the array or writing bytes of each block.
With V
PP
< V
PPLMAX
, memory contents cannot be altered.
READY/BUSY: Indicates the status of the internal Write State Machine.
When low, it indicates that the WSM is performing a block erase or byte
write operation. RY/BY high indicates that the WSM is ready for new
commands, block erase is suspended or the device is in deep
powerdown mode. RY/BY is always active and does NOT float to tri-state
off when the chip is deselected or data outputs are disabled.
OUTPUT
RY/BY
WRITE ENABLE: Controls writes to the Command User Interface and
array blocks. WE is active low. Addresses and data are latched on the
rising edge of the WE pulse.
INPUT
WE
OUTPUT ENABLE: Gates the device's outputs through the data buffers
during a read cycle. OE is active low.
INPUT
OE
POWERDOWN: Puts the device in deep powerdown mode. PWD is
active low; PWD high gates normal operation. PWD also locks out block
erase or byte write operations when active low, providing data protection
during power transitions.
INPUTPWD
CHIP ENABLE: Activates the device's control logic input buffers
decoders, and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.
INPUT
CE
DATA INPUT/OUTPUTS: Inputs data and commands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.
INPUT/OUTPUTDQ
0
- DQ
7
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
INPUT
A
0
- A
19
Symbol Type
V
PP
NOTE:
LH28F008S A 8M (1M × 8) F la sh Memory
7-44
DQ4
PP
CC
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Standard Pinout
STANDARD PINOUT
LH28F008SAT
40 LEAD TSOP
10mm x 20 mm
TOP VIEW
A
17
A
A
19
A
A
18
A
A
16
A
A
15
A
A
14
A
A
13
A
A
12
A
V
V
PWD
A
11
A
A
10
A
9
A
A
8
A
A
7
A
A
6
A
A
5
A
A
4
A
CC
WE
NC
NC
OE
RY/BY
DQ
DQ
DQ5
V
GND
A
0
A
A
1
A
A
2
A
A
3
A
7
6
GND
DQ3
DQ2
DQ1
DQ0
Figure 2. TSOP Lead Conf iguration
8M (1M × 8) Flash Memory LH28F008SA
7-45
INPUT
BUFFER
ADDRESS
LATCH
ADDRESS
COUNTER
Y-DECODER
X-DECODER
Y-GATING WRITE STATE
MACHINE PROGRAM/ERASE
VOLTAGE SWITCH
COMMAND
USER
INTERFACE
OUTPUT
BUFFER INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
16
64 KBYTE
BLOCKS
I/O LOGIC
CE
WE
OE
PWD
RY/BY
VPP
VCC
GND
DQ0 - DQ7
A0 - A19
OUTPUT
MULTIPLEXER
DATA A
REGISTER
Figure 3. LH28F008SA Array Interface to
386SL Microprocessor Superset through PI Bus
(Including RY/ BY Masking and Selective Powerdown), for DRAM Backup During System SUSPEND,
Resident O/S and Appli cati ons a nd Mother board Sol id-Stat e Disk
LH28F008S A 8M (1M × 8) F la sh Memory
7-46
PRIN CIPLES OF OPERATION
The LH28F008SA includes on-chi p write au tomation
to mana ge w rite a nd erase functi ons. Th e Write S tate
Machine allows for: 100% TTL-level control inputs; fixed
power supplies during block erasure and byte write;
and minimal processor overhead with SRAM -like inter-
face timings.
After initial device powerup, or after return from deep
powerdown mode (see Bus Operations), the LH28F008SA
functions as a read-only memory . Manipulation of external
memo ry-contro l pins allow array read, st andby and out p ut
disable operations. Both Status Register and intelligent
identifiers can also be accessed through the Command
User Interface when VPP = V PPL.
Th is s ame subset of operations is also available when
high voltage is applied t o the VPP pin. In addition, high
voltage on VPP enables successful block erasure and
byte writing of the device. All funct ions associated with
altering memory contents – byte write, block erase,
status and i ntel li gent identifier – are accessed via the
Command User Interface and verified thru the Status
Register.
Commands are written using standard microprocessor
write timings. Command User Interface contents serve
as input to the WSM, which controls the block erase
and byt e w rite circuitr y . W rite cycles also inter nally latch
addresses and data needed for byte write or block erase
operations. With the appropriate command written to
the register, standard micropr ocessor read timings out -
put array data, access the intelligent identifier codes,
or out put byte write and block er ase stat us for verifica-
tion.
Interface software t o ini ti ate and poll progress of in-
te rn al byte write and blo ck erase can be stored in any
of the LH28F008SA blocks. This code is copied to, a n d
executed from, system RAM during actual flash memory
update. After successful completion of byte write and/or
block erase, code/data reads from the LH28F008SA
are again possible via the Read Array command. Erase
suspend/resume capability allows system software to
suspend block erase to read data and execute code
from any other block.
Command User Interface and
Writ e Automati on
An on-chip state machine controls block erase and
byte write, freeing the system processor for other tasks.
After receiving the Erase Setup and Erase Confirm
commands, the state machi ne controls bl ock pre-con-
ditioning and erase, re turni ng progress via the Status
Register and RY/BY output. Byte write is si milarly con-
trolled, after destination address and expected data are
supplied. The program and erase algorithms of past
standard Flash memories are now regulated by the
state machine, including pulse repetition where required
and internal verifica tion and margini ng of data .
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
FFFFF
F0000
EFFFF
E0000
DFFFF
CFFFF
D0000
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
Figure 4. Mem or y Map
8M (1M × 8) Flash Memory LH28F008SA
7-47
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply sw itchable
(available only when me mory byte w rites/block erases
are required) or hardwired to VPPH. When VPP = VPPL,
memor y cont ents cannot be alter ed. The LH28F008SA
Co mmand User Interface architecture provides protec-
ti on f rom u n wanted byte write or block erase operations
even w hen high voltage is appl ied to V PP. Additionally,
all functions are disabled whenever VCC is below the
w ri te lockout vol tage VLKO, or when PWD is at VIL. The
LH28F008SA accommodates either design practice
and encourages opt imizat ion of the processor- memor y
interface.
The two-step byte write /bl ock erase Co mmand User
Interface write sequence provides additional software
write protection.
BUS OPERATION
F lash memor y r eads, erases and writes in- system vi a
the local CPU. All bus cycles to or from the flash memory
conform to standard micropro cessor bus cycles.
Read
The LH28F008SA has three read modes. The memory
can be read fr om any of its blocks, and infor mation can
be read fr om t he int ell igent identifier or Status Register.
VPP can be at either V PPL or VPPH.
The first task is to write the appropriate read mode
c om mand t o t he Command User Int erf ace (ar ray, intel-
ligent identifier, or Status R egister). The LH28F008SA
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown. The
LH28F008SA has four contro l pins, two of whi ch must
be l ogica lly active to obtain data at the outputs. Chip
Enable ( CE) is the device sele cti on control, and when
active enables the selected memory device. Output
Enable (OE) is the data input/output (DQ0-DQ7) direction
co ntrol, and when active dri ves data from the sel ected
memory onto the I/O bus. PWD and WE must also be
at VIH. Fi gure 8 il lustrates read bus cycle waveforms.
Output Disable
With OE at a logic-high level (VIH) , the device outputs
are disabled. Output pins (DQ0-DQ7) are placed in a
high-impedance state.
Standby
CE at a logic-high level (VIH) p laces the LH 28F 008 SA
in standby mode. Standby operati on di sables much o f
the LH28F008SA’s circuitry and substantially reduces
device po wer consumption. The out put s (DQ 0-DQ7) ar e
placed in a high-impedance state independent of the
status of OE. If the LH 28F008SA i s dese lected duri ng
block er ase or byte write, the device wi ll cont inue func-
tioning and consuming normal active power until the
operation completes.
X
D
IN
X
X
3, 4, 5Write
V
OH
A2HX
Intelligent Identifier (Device)
89H
X
V
IL
V
IH
Intelligent Identifier (Mfr) High Z
X
X
XX
X
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
OH
V
OH
X
X
XX
High Z
High Z
V
IL
V
IL
V
IL
Deep PowerDown
Standby
Output Disable
Read
Mode Notes CE A
0
V
PP
DQ
0-7
1, 2, 3
3
3
D
OUT
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
X X
X
X
X
X
X
PWD OE WE RY/BY
V
IH
V
IL
Table 2. Bus Operations
NOTES:
1. Refer to D C Charact erist ics. When VPP = VPPL, memory cont ents can be read but not written or erased.
2. X can be VIL or V IH for control p ins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH volt ages.
3. RY/BY is VOL w hen the Wr ite St ate Machine is execut ing int ernal block erase or byte wr it e algorithms. It is VOH wh en the WSM is not busy,
in Erase Suspend mode or deep power down mode.
4. Command writes involving block erase or byte write are only successfully executed when VPP = VPPH.
5. Refer to Ta ble 3 for val id DIN during a writ e operation.
LH28F008S A 8M (1M × 8) F la sh Memory
7-48
Deep Power-Down
The LH 28F008S A o ff ers a dee p powerdown feature,
entered when PWD is at VIL. Cu rrent draw thru VCC is
0.20 µA typical in deep powerdown mode, with current
draw through VPP typically 0.1 µA. During read modes,
PWD-low deselects the memory, places o u tput drivers
in a high-impedance state and turns off all internal
circuits. The LH28F008SA requires ti me tPHQV (see AC
Characteristics-Read-Only Operations) after return
from powerdown until initial memory access outputs are
valid. After this wakeup interval, normal operation is
restored. The Command User Interface is reset to Read
A rray, and the uppe r 5 bits of the S tatus Regis te r a re
cleared to value 10000, upon return to normal operation.
Dur ing block er as e or byt e wr ite m odes, PWD l ow wil l
abort either operation. Memory contents of the block
being altered are no longer valid as the data will be
partial ly wri tten or e rased. Time tPHWL after PWD goes
to logic-high (VIH) is re quired before another command
can be written.
I nte lligent Identifier Operation
The i ntel li gent identifier operati on outputs the manu-
facturer code, 89H; and the device code, A2H for the
LH28F008SA. The system CPU can t hen automat ically
match the device w ith i ts proper bl ock e rase and byte
wri te algorithms.
The manu facturer- and device-codes ar e r ead via the
Co mmand User I nterface. Following a write o f 90H to
the Command User Interface, a read from address
l ocat ion 00000H out put s t he m anuf actur er code (89H).
A read from address 00001H outputs the device code
(A2H). It is not necessary to have high voltage applied
to VPP t o read the intel li gent identifiers f rom the Com-
mand User Interfa ce.
Write
W rit es to t he Comm and User Inter face en able reading
of device data and int e ll igent identifiers. They also con-
trol inspection and clearing of the Status Register. Ad-
ditionally , when VPP = VPPH, the Command User Interface
control s bl ock erasure and byte w ri te . The contents of
the inter face register serve as input to the int ernal state
machine.
Table 3. Command Definitions
Command Bus
Cycles
Req’d Notes First Bus Cycle Second Bus Cycle
Operation Address Data Operation Address Data
Read Array/Reset 1 1 Write X FFH
Intelligent Identifier 3 2, 3, 4 Write X 90H Read IA IID
Rea d S tat us Reg ist er 2 3 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Erase Setup/Erase
Confirm 2 2 Write BA 20H Write X D0H
Byte Write Setup/Write 2 2, 3, 5 Write WA 40H Write WA WD
Alt ern ate By te Wr ite
Setup/Write 2 2, 3, 5 Write WA 10H Write WA WD
NOTES:
1. Bus operations are def ined i n Table 2.
2. I A = Id e ntifier Addre ss: 0 0 H for ma n uf acturer code, 0 1 H for device code.
B A = Address w it hin the block be ing erased.
WA = Address of memory location to be wr itten.
3. S R D = Dat a read f rom St atus Register. See Ta ble 4 for a descr ipt ion of the Stat us Register bi ts.
WD = Dat a to be writt en at location WA. Dat a is latched on the rising edge of WE.
IID = Data read from intelligent ident ifiers.
4. Follo wing the intellig ent id entifier command, two read operations access manufacture an d device codes.
5. E it her 40H or 10H are recognized by the W SM as the Byt e Writ e Setup comm and.
6. Commands ot her than those shown above are reserved by I nt e l for futur e device implementations and should not be used.
8M (1M × 8) Flash Memory LH28F008SA
7-49
The C ommand U ser Interface itself does not occupy
an addressable mem ory location. The interface register
is a latch used to store the command and address and
data information needed to execute the command.
Erase Setup and Erase Confirm commands require both
appropriate command data an d an address wi thi n the
block to be erased. The Byte Write Setup command
requires both appropriate command data an d the ad-
dress of the location to be written, while the Byte Write
command consists of the data to be written and the
address of the l ocati on to be w ritten.
The Command User Interface is written by bringing
WE t o a logic-low level (VIL) while CE is low. Addr esses
and data are latched on the rising edge of WE. Standard
microprocessor wri te ti mi ngs are used.
Re fer to AC Wri te Characteri stics and the A C Wave-
for ms for Writ e O perations, F igur e 9, f or specif ic timing
parameters.
COMMAND DEFINITIONS
When VPPL is appl ied to the VPP pin, read op erations
from the St atus Register, intelligent identifiers, or array
bl ocks are enabled. Placing VPPH on VPP enables suc-
cessful byte w rite and block erase ope rations as wel l.
Device operations are selected by writing specific
commands into the Command User I nte rface. Table 3
define s the LH 28F008SA co mmands.
Read Array Command
U pon ini tial device powerup and after exit from deep
powerdown mode, the LH28F008S A defaults to Re ad
Array mode. This operation is also initiated by writing
FFH int o the Command User I nter face. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the Command User Interface
contents are altered. Once the internal Write State
Machine has star ted a block er ase or byte write opera-
tion, the device will not recognize the Read Ar ray com-
m and, unt il t he WSM has completed its operation. The
Read Array command i s functi onal when VPP = VPPL or
VPPH.
I ntell igent Id en tifier Command
The LH28F008SA contains an intelligent ident ifier op-
er ation, in itiat ed by writing 90H int o t he Com mand User
Interface. Following the command write, a read cycle
from address 00000H retrieves the manufacturer code
of 89H . A read cycle from address 00001 H returns the
device code of A2H. To terminate the operation, it is
necessary to write another valid command into the
regi ste r. Like the R ead Array command, the i nte lligent
identifier command is functional when VPP = VPPL or
VPPH.
WSMS
01
23
4
567
R
R
R
VPPS
BWSESESS
Table 4. Status Register Definitions
SR.2 - SR.0 = R ES E RV E D FO R FU TUR E (R) E NH ANCEMENT S
These b its are r e ser ved for future use and should be masked out when pol ling the St atus Register.
S R.7 = WRITE STATE MACH IN E STATU S (WS MS )
1 = Ready
0 = Busy
NOTES:
RY/BY or the Write State Machine Status bit must
first be checked to determine byte write or block erase
comple tion, before the Byte Write or Erase Status bi t
are checked for success.
I f the Byte Writ e AND Er ase Stat us b it s are set t o "1"s
during a block erase attempt, an improper command
sequence was entered. Attemp t th e operati on again.
If VPP low stat us is det ected, the Status Register must
be cleared before another byte write o r bl ock erase
operation is attempted.
The VPP St atus bit, unlike an A/D conver ter, does not
pr ovide cont inuous indication of VPP level. The WSM
interrogates the VPP level onl y after the byte w rite o r
block erase comm and sequences have been ent ered
and inf orms the system if VPP has not been switched
on. The VPP Status bit is not guaranteed to report
accurate feedback between VPPL and VPPH.
SR.6 = E RASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
S R.5 = ERASE STAT US (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
S R.4 = BYTE WRITE STATUS (BWS)
1 = Error i n By te W rite
0 = Successful Byte Write
SR.3 = V PP STATU S (V PP S)
1 = VPP Low D e tect; Operation Abort
0 = VPP OK
LH28F008S A 8M (1M × 8) F la sh Memory
7-50
Read Status Register Command
The LH28F008SA contains a Status Regi ster which
may be read to determine when a byte write or block
erase operation is complete, and whether that operation
completed successfully. The Status Register may be
read at any time by writing the Read Status Register
command (70H) to the Command User In terface. After
writing this command, all subsequent read operati ons
output dat a fr om the St atus Register, until another valid
command is written to the Command User Interface.
The contents of the Status R egister a re l a tched on the
fall ing edge of OE or C E, w hichever occurs last i n t he
read cycle. OE or CE must be toggled to VIH before
further read s to update the Sta tus R egister latch. The
Read Status Regi s te r c ommand function s w hen VPP =
VPPL or VPPH.
Clear Status Register Command
The Erase Status and Byte Write Statu s bits a re set
to “1”s by the Write State Machine and can only be
reset by the Clear Status Regi ster Command. These
b its indicate various failure conditions (see Table 4). By
allowing system software to control the resetting of
these bits, several operations may be performed (such
as cumulatively writing several bytes or erasing multiple
blocks in sequence). The Status Register may then be
polled to determine if an error occurred during that
sequence. This adds flexibility to the way the device
may be used.
A dditional ly, the VPP Status bit (S R.3) MUS T be reset
by system softwa re before further byte writes or block
erases ar e at tempt ed. To clear the St atus Register, the
Clear Status Register command (50H) is written to the
Command User Interface. The Clear Status Register
command is functional when VPP = VPPL or VPPH.
Eras e Set up/ Eras e Confirm Commands
E rase i s executed one block a t a time, initiated by a
two-cycle command sequence. An Erase Setup com-
mand ( 20H) is first wr itten t o t he Com mand User Inter -
face, foll owed by the Erase Confirm command (D0H).
These com mands r equire bot h appr opriate sequencing
and an address within the block to b e e rased to FFH.
Block preconditioning, erase and verify are all handled
internally by the Write State Machine, invisibl e to the
system. After the two-command erase sequence is writ-
ten to it , the LH28F008SA aut omatically output s Status
Register data when read (see Figure 6; Block Erase
Fl owchart). The CPU can detect the compl e tion of the
erase event by ana lyzing the output of the RY/BY pin,
or the WSM S tatus bi t of the Sta tus Register.
When erase is completed, t he Erase Stat us b it should
be checked. If e rase error is detected, the Status Reg-
i ste r should be cl eared. The C ommand User Interface
remains in Read Status Register mode until further
commands are i ssued to it.
This two-step sequence of set-up followed by execu-
tion e nsur es t hat mem ory contents ar e not accidentally
erased. Also, reliable block erasure can only occur when
VPP = VPPH. In the absence of th is high voltage, m emory
contents are protected agai n st erasure. If block erase
is a t tempted while VPP = VPPL, the VPP Status bit will be
set to “1”. Erase attempts while VPPL <VPP <VPPH produce
spurious results and should not be attempted.
Er ase Suspend/ E ra se Re sume Commands
The Erase Suspend command allows block erase
interruption in order to read data fro m another block of
memory. Once the erase process starts, writing the
Erase Suspend command (B0H) t o the Com mand User
Interface requests that the WSM suspend the erase
sequence at a predetermined po int in the erase al go-
rithm. The LH28F008SA continues to output Status
Register data when read, after the Erase Suspend
command i s written t o it. Po lling the WSM Status a nd
Erase Suspend Status bits will determine when the
erase operation has been suspended (both will be set
to “1”). RY /B Y wil l also t ransi ti on to VOH.
At th is poi nt, a Re ad Array command can be written
to the Command User Interface to read data from
blocks other than that which is suspended. The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H), at which time
the WSM will continue with the erase process. The
Erase Suspend Status and WSM Status bits of the
Status Register will be automatically cleared and RY/BY
wi ll return to VOL. After the Erase Resum e comm and is
written to it, the LH28F008SA automatically outputs
Status Register data w hen read (see Figure 7; Erase
Suspend/Resume Flowchart). VPP must remain at VPPH
wh ile the LH 28F008S A i s in Erase S uspend.
Byte Write Setup/Write Commands
Byte write is executed by a tw o-command sequence.
The Byte Write Setup command (40H) is written to the
Co mmand U ser In ter face, foll owed by a second write
speci fyi ng the address an d data (la tched on the rising
edge of WE) to be w ritten. The WSM then takes over,
controlling the byte write and write verify algorithms
in ternally. After the two-command b y te write sequence
is wri tten to it, the LH28F008SA automatically outputs
Status Register data when read (see Figure 5; Byte
W ri te Fl owcha rt ). The C PU can d etect the completion
of the byte write event by analyzing the output of the
RY/BY pin, or the W SM Status bit of the Stat us Register.
Only t he Read Status Register command is valid whi le
byte w rite is active.
8M (1M × 8) Flash Memory LH28F008SA
7-51
When byte write is complete, the Byte Write Status
bit should be checked. If byte write error i s d etected,
the Status Register should be cleared. The internal
WSM verify only detects errors for “1”s that do not
successfully write to “0”s. The Command User Interface
remains in Read Status Register mode until further
commands are issued to it. If byte write is attempted
while VPP = VPPL, the VPP Status bit will be set to “1”.
Byt e wr it e attem pts w h ile VPPL <VPP <VPPH produce spu-
rious results and shoul d n o t be att emp ted.
EXTENDED BLOCK ERASE/
B Y TE WRITE CYCLING
The LH28F008SA is designed for 100,000 byte write/
bl ock erase cycles on each o f the sixteen 64K bl ocks.
Lo w elect ric fields, advanced oxides and minima l oxide
area per cell subjected to the tunneling electric field
combine to greatly reduce oxide stress and the prob-
ability of failure. A 20M soli d-state drive using an array
of LH28F008SAs has a MTBF (Mean Time Between
Failure) of 33.3 million hours(1), over 600 times more
reliable than equival ent ro tating disk technology.
AUTOMATED BYTE WRITE
The LH28F008SA integrates the Quick-Pulse pro-
gramming algorithm using the Command User Inter-
face, Stat us Register and W rite State Machine ( WSM).
On-chip integration dramatically simplifies system soft-
ware and provides processor interface timings to the
Command User Interface and Status Register. WSM
operation, inter na l ver if y and VPP high voltage presence
are monitored a nd reported via the R Y/BY output and
appropriate Status Register bits. Figure 5 shows a
system software flowchart for device byte write. The
entire sequence is performed with VPP at VPPH. Byte
write abort o ccu rs when PWD transitions to VIL, or VPP
drops to VPPL. Although the WSM is hal ted , byte data
is partially written at the location w here byte write was
aborted. Block erasure, or a repeat of byte write, is
requi red to i nitial ize thi s data to a known value.
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm is now imple-
mented int ern ally, including all preconditioning of block
data. WSM operation, erase success and VPP high
vol tage prese nce are mon itored an d repo rted through
RY/B Y and the Status Regi s te r. Add iti onal ly, i f a c om-
mand ot her t han Erase Confirm is writ ten to t he device
following E rase Setup, both the Erase Status and Byt e
Write Status bits wi ll be se t t o “1”s. When i ssuing the
Erase Setup and Erase Confirm commands, they
should be written to an address within the address range
of the block to be erased. Figure 6 shows a system
so ftware flow chart fo r block era se.
Erase typically takes 1.6 seconds per block. The Erase
Suspend/Erase Resume command sequence allows
suspension of this erase operation to read data from a
block ot her th an that in which erase is being performed.
A system software flowcha rt i s show n in Figure 7 .
The entire sequence is performed with VPP at VPPH.
Abort occurs when PWD transitions to VIL or VPP fall s
to VPPL, while erase is in progress. Block data is partially
erased by this operation, and a repeat of erase is
required to obtai n a ful ly erased b lock.
DESIGN CONSIDERATIONS
Three-Line Output Control
The LH28F008SA will often be used in large memory
arrays. I ntel provides thr ee control inputs t o accom mo-
date multiple memory connections. Three-line control
provi des for:
a) low est possibl e memory pow er dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CE, while OE should be con-
nected to all memory devices and the system’s READ
control line. This assures that only selected memory
devices have acti ve ou tputs whi le desele c ted memory
devices are in Standby Mode. Finally, PWD should
either be tied to the system RESET, or connected to
VCC if un used.
RY/BY an d Byte Write/Blo ck Erase Polli ng
RY/BY is a full CMOS output that provides a hard-
ware method of detecting byte write and block erase
completion. It transitions low time tWHRL after a write or
erase command sequence is written to the
LH28F008SA, and re turns to VOH when the WSM has
fin ished executi ng the internal algorithm.
RY/BY can be connected to the interrupt input of the
system C PU or controll er. It is a c ti ve a t all times, not
tristated if the LH28F008SA CE or OE inputs are brought
to V IH. RY/BY is also VOH when the devi ce is in Erase
Suspend or deep pow erdow n modes.
( 1) Assumptions: 10K fi le writt en every 10 m inutes. (20M ar ray)/(10K file) = 2,000 file writes bef or e erase required.
( 2000 f iles wr it es/erase) x (100,000 cycles per L H 28F008SA block) = 200 mi ll ion f ile wr it es.
(200 x 106 file w r it es) x (10 min/write) x (1 hr/ 60 min) = 33.3 x 106 MTBF.
LH28F008S A 8M (1M × 8) F la sh Memory
7-52
Start
Write 40H (10H),
Byte Address
Write Byte
Address/Data
NO
YES
Full Status
Check if Desired
Byte Write
Completed
Status Register Data
Read (See Above)
Byte Write
Successful
V
PP
Range
Error
Byte Write
Error
FULL STATUS CHECK PROCEDURE
WSM
Ready?
SR.3=0
?
SR.4=0
?
YES
YES
NO
NO
Bus
Operation Command Comments
Write
Write
Standby/Read
Byte Write
Setup
Byte Write
Data = 40H (10H)
Address = Byte to be written
Data to be written
Address = Byte to be written
Check RY/BY
V
OH
= Ready, V
OL
= Busy
or
Read Status Register
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to update
Status Register
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
device to Read Array Mode
Bus
Operation Command Comments
Optional
Read
Standby
Standby
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR.3
1 = V
PP
Low Detect
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Check SR.4
1 = Byte Write Error
Fi gur e 5. Automat ed Byt e Wri te Flowchart
8M (1M × 8) Flash Memory LH28F008SA
7-53
Start
Write 20H,
Block Address
Write D0H
Block Address
NO
YES
Full Status
Check if Desired
Block Erase
Completed
Suspend
Erase?
Erase Suspend
Loop
Status Register Data
Read (See Above)
Block Erase
Successful
V
PP
Range
Error
Command Sequence
Error
FULL STATUS CHECK PROCEDURE
Block Erase
Error
YES
YES
NO
NO
YES
NO
WSM
Ready? NO
SR.3=0
?
SR.4,5=1
?
SR.5=0
?
YES
Bus
Operation Command Comments
Write
Write
Standby/Read
Erase
Setup
Erase
Data = 20H
Address = Within block to be
erased
Data = D0H
Address = Within block to be
erased
Check RY/BY
V
OH
= Ready, V
OL
= Busy
or
Read Status Register
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to update
Status Register
Repeat for subsequent bytes
Full status check can be done after each block or after a
sequence of blocks
Write FFH after the last block erase operation to reset the
device to Read Array Mode
Bus
Operation Command Comments
Optional
Read
Standby
Standby
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR.3
1 = V
PP
Low Detect
SR.3 MUST be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine.
SR.5 is only cleared by the Clear Status Register Command,
in cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Check SR.4,5
Both 1 = Command Sequence
Error
Standby Check SR.5
1 = Block Erase Error
Figure 6. Automated Block Erase Flow char t
LH28F008S A 8M (1M × 8) F la sh Memory
7-54
Power Supp ly Decoupli ng
Flash memory power switching characteristics require
careful device decoupling. System designers are inter-
ested in 3 supply curr ent issues; standby current levels
(ISB), active current levels (ICC) and transient peaks
produced b y fal li n g and ri si ng edge s o f CE. Transient
current magni tu des depend o n the device outputs’ ca-
pacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacit or connect ed bet ween each VCC
and GN D, and between its VPP and GND. These hi gh
frequency, low inherent-inductance capacitors should
be pl aced as close as possi ble t o package lead s. Ad-
ditionally, for every 8 devices, a 4.7 µF electrolytic
capacitor should be placed at the array’s po wer supply
connection between VCC and GND. The bulk capacitor
will overcome voltage slumps caused by PC board trace
inductances.
VPP Trace on Printed Circuit Boards
W riting flash mem ories, w hile t hey reside in the t arget
system , requires th a t the printed circui t board designer
pay attention to the VPP power supply trace. The VPP
pin supplies the memory cell current for writing and
erasing. Use similar trace widths and layout considera-
tions given to the VCC p ower bus. Adequate V PP Supply
traces and decoupling will decrease VPP voltage spikes
and overshoots .
Write B0H
Write 70H
YES
YES
Read Status
Register
NO
NO
YES
SR.7=1
?
Done
Reading?
Write D0H
Write FFH
Continue Erase
Erase Has
Completed
NO
Start
SR.6=1
?
Bus
Operation Command Comments
Write
Standby
Read
Check RY/BY
V
OH
= Ready, V
OL
=
Busy or Read Status
Register
Standby/
Read
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to Update
Status Register
Write
Write
Write
Erase
Suspend
Read
Status Register
Read Array
Erase Resume
Data = B0H
Data = 70H
Check SR.6
1 = Suspended
Data = FFH
Read array data from block
other than that being
erased.
Data = D0H
Figure 7. Erase Suspend/Resume Fl owchart
8M (1M × 8) Flash Memory LH28F008SA
7-55
VCC, VPP, PWD Tr ansitions and
the Command/Status Registers
B yte wri te and bl ock erase completion are not g uar-
anteed if VPP d rops bel ow VPPH. If the VPP Status bit of
the Status Register (SR.3) i s set to “1”, a Clear Status
Register command MUST be issued before furt her byte
write/block erase attempts are allowed by the WSM.
Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status
bi ts of the Status Re gister wi ll be set to “1”s if error is
detected. PWD tra nsitions to VIL during b yte write and
block erase also abort the operations. Data is partially
altered in either case, and the command sequence must
be repeated after normal operation is restored. Device
poweroff, or PWD transitions to VIL, clear the Status
R egister t o i nitial val ue 10000 for the upper 5 bits.
The Co mmand U ser I nterface latches commands as
issued by system software and is not altered by VPP or
CE t ransitions or WSM act ions. Its st ate upon powerup,
after exit from deep powerdown or after VCC t ransi tions
bel o w VLKO, i s Read Array Mode.
After byte write or block erase is complete, even after
VPP transitions down to VPPL, the Command User Inter-
face must be reset to Read Array mode via the R ead
Array command if access to the memory array i s de-
sired.
Power Up/Down Protection
The LH28F008SA is designed to offer protection
agai nst accidental blo ck erasure o r by te writing during
power transitions. Upon po wer -up, the LH28F008SA is
indifferent as to w hich power supply , VPP or VCC, powers
up first. Power supply sequenci ng is not required. In-
ternal circuitry in the LH28F008SA ensures that the
Command User Interface is reset to the Read Array
mode on po wer up.
A system designer must guard against spurious writes
for VCC voltages above VLKO when VPP is active. Si nce
both WE and CE must be low for a command write,
driving either to VIH will inhibit writes. The Command
User Interface architecture provides an a dded l evel o f
protection since alteration of memory contents only
occurs after successful completion of the two-step com-
mand sequences.
Finally, the device is disabled until PWD is brought to
VIH, regardless of the state of its control inpu ts. This
provides an additiona l level of memory protection.
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idl e time. Fl ash non-vo latili ty in creases usabl e
battery life, because the LH28F008SA does not con-
sume any power to retain code or data when the system
is off .
In addition, the LH28F008SA ’s deep powerdown mode
ensures extremely low power dissipation even when
system power is appl ied. Fo r example, portable PCs
and other power sensitive applications, using an array
of LH28F008SAs for solid-state storage, can lower
PWD to VIL in standby or sleep modes , producing neg-
ligible power consumption. If access to the
LH28F008SA is again needed, the part can again be
read, foll owing the tPHQV and tPHWL wakeup cycles re-
quired after PWD is first raised back to VIH. See AC
C har acter ist ics – Read-Only and Wr it e O perat ions and
Fi gures 8 and 9 for m ore in formation .
LH28F008S A 8M (1M × 8) F la sh Memory
7-56
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature D uring Read 0°C t o +70°C(1)
During Bl ock E rase /Byte Write 0°C to +70°C
Temperature Under Bias -10°C to +80°C
Storage Temperature -65°C to +125°C
Voltage on Any Pin (except VCC and VPP) with Respect to GND -2 .0 V to +7.0 V(2)
VPP Program Vol tage wi th R espect to GND during Bl ock Era se/Byte Write -2 .0 V to +14.0 V(2, 3)
VCC Suppl y Voltage w ith R espect to GND -2 .0 V to + 7.0 V(2)
Output Short C ircuit C urrent 100 mA(4)
* WAR NING
Str essing t he device beyond the “ Absolute Maximum Ratings” m ay cause permanent damage. These ar e str ess ratings on ly.
O per ation beyond t he “O p er ating Conditions” is not recomm ended and ext e nded exposure beyond the “Operating Conditions”
may affect device rel iability.
NOTES:
1. Operating temperat ure is for commer c ia l product def ined by t his specification.
2. M inimum DC voltage is - 0.5 V on input/ output pins. During transit ions, this level m ay under shoot to - 2.0 V for periods < 20 ns. M aximum
DC voltage on input/ out put pins is VCC + 0.5 V wh ich, dur ing transitions, may overshoot to VCC + 2.0 V for per iods <20 ns.
3. M aximum DC voltage on VPP may ove rshoot to + 14.0 V for per iods <20 ns.
4. O utput shor ted f or no m or e than one second. No m ore t han one output shorted at a time.
5. 5% VCC specifications r eference the LH28F008SA-85 in its High Speed configuration. 1 0% VCC specifications reference the LH28F008SA-85
in its Standard conf igurat ion, and the LH28F008SA-12.
OPERATING CONDITIONS
Symbol Parameter Notes Min Max Unit
TAO per ati ng Te mpe rat ure 070°C
V
CC VCC Su ppl y Volt age (1 0%) 5 4.50 5.50 V
VCC VCC Su ppl y Volt age (5 %) 5 4.75 5.25 V
DC CHARACTERISTICS
VCC = VCC Max, CE = VIL
f = 8 MHz, IOUT = 0 mA
TTL Inputs
mA5025
VCC = VCC Max, CE = GND
f = 8 MHz, IOUT = 0 mA
CMOS Inputs
mA35201VCC Read CurrentICCR
PWD = GND ±0.2 V
IOUT (RY/BY) = 0 mA
1.20.201VCC Deep PowerDown
Current
ICCD
VCC = VCC Max
CE = PWD = VCC ±0.2 V
10030
VCC = VCC Max
CE = PWD = VIH
mA2.01.01, 3VCC Standby CurrentICCS
VCC = VCC Max
VOUT = VCC or GND
±101
1
Output Leakage CurrentILO
ILI Input Load Current V CC = VCC Max
VIN = VCC or GND
Symbol Parameter Notes Min Typ Max Unit Test Condition
±1.0
µA
µA
µA
µA
8M (1M × 8) Flash Memory LH28F008SA
7-57
DC CHARACTERISTI CS (Co nti nued)
CAPACITANCE (5) TA = 25°C, f = 1 MHz
NOTES:
1. A ll curr ents are in RMS un less otherwise noted. Ty pica l values at VCC = 5.0 V, VPP = 12.0 V, T = 25°C.
These current s are valid for all pr oduct versions (package and speeds).
2. ICCES is specif ied w ith the device deselected. If the LH28F008SA is read whi le in Erase Suspend Mode,
current draw is the su m of ICCES and ICCR.
3. In cludes RY/BY.
4. Block Erases/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and V PPL.
5. Sampled, not 10 0% teste d.
V
2.0
V
CC
Erase/Write Lock
Voltage
V
LKO
V12.612.011.4V
PP
during Erase/Write
Operations
V
PPH
V
V
V
V
V
6.50.04V
PPL
V
OH
V
PP
during Normal
Operations
Output High Voltage
V
OL
Output Low Voltage
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
PPES
V
PP
Erase Suspend Current
I
PPE
V
PP
Block Erase Current
I
PPW
V
PP
Byte Write Current
I
PPD
V
PP
Deep PowerDown
Current
I
PPS
V
PP
Standby Current
I
CCES
V
CC
Erase Suspend Current
I
CCE
V
CC
Block Erase Current
I
CCW
V
CC
Byte Write Current
Symbol Parameter Notes Min Typ Max Unit Test Condition
V
CC
= V
CC
Min
I
OH
= - 2.5 mA
V
CC
= V
CC
Min
I
OL
= 5.8 mA
V
PP
= V
PPH
Block Erase Suspended
V
PP
= V
PPH
Block Erase in Progress
V
PP
= V
PPH
Byte Write in Progress
PWD = GND ±0.2 V
V
PP
≤ V
CC
V
PP
≤ V
CC
Block Erase Suspended
CE = V
IH
Block Erase In Progress
Byte Write In Progress
mA1 10 30
10 30
10
±10±1
90 200
0.10 5.0
10
10
90 200
0.8
V
CC
+ 0.5
0.45
2.43
3
1
1
1
1
1
1
-0.5
2.0
mA
mA
µA
µA
µA
µA
mA
mA
5
30
30
1, 2
Symbol
V
OUT
= 0V
pF128
Output Capacitance
C
OUT
C
IN
Input Capacitance 6 8 pF V
IN
= 0V
ConditionUnitMax
Typ
Parameter
LH28F008S A 8M (1M × 8) F la sh Memory
7-58
NOTES:
1. Testing cha racteristics for LH28F 008SA -85 i n Standard configuration, and
LH28F008SA-12.
2. Testing characteristics for L H28F008SA-85 in H igh Speed configuration.
AC CHARACTERISTI CS – Read-On ly O peratio ns (1)
NOTES:
1. See A C Input/O utput Reference Waveform for ti ming m e asu r ements.
2. OE may be delayed up to tCE - tOE after the fa ll ing edge of CE w it hout impact on tCE.
3. Sampled, not 1 00% teste d.
4. See H igh Speed AC Input/ Out p ut Reference Wavef orms and H igh Speed AC Testing Load cir cuits f or testing characteristics.
5. See A C Input/O utput Reference Waveforms and AC Testing Load C ircuits f or testing characteristics.
AC test inputs are driven at VOH ( 2.4 V TTL) for a Logic “1” and VOL
( 0. 45 VTTL) for a Logic “0”. Input t iming begins at VIH (2. 0 V TTL) and
VIL (0.8 V TTL). Output t im ing ends at VIH and VIL. Input rise and fall
t im es (10% t o 90%) <10 ns.
A C IN PUT /OUTP UT RE FER ENC E WAV EFORM (1)
TEST POINTS
2.0
0.8
INPUT
2.4
0.45
2.0
0.8 OUTPUT
AC test inputs are driven at 3. 0 V for a Logic “1” and 0. 0 V for a
Logic “0”. Input timing begins, and out put t im ing ends, at 1. 5 V. Input
r ise and fa ll times ( 10% to 90%) <10 ns.
HIGH SPEED
A C IN PUT /OUTP UT RE FER ENC E WAV EFORM (2)
TEST POINTS
1.5
INPUT
3.0
0.0
1.5 OUTPUT
DEVICE
UNDER
TEST
1N914
OUT
RL
CL
C = 100 pF
C Includes Jig
Capacitance
R = 3.3 kΩ
L
L
L
1.3V
A C TEST IN G L OA D CIRC UIT(1)
DEVICE
UNDER
TEST
1.3V
1N914
OUT
RL
CL
C = 30 pF
C Includes Jig
Capacitance
R = 3.3 kΩ
L
L
L
HIGH SPEED
A C TEST IN G L OA D CIRC UIT(2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
000
0
0 0
0
0
0
3Output Hold from
Addresses, CE or OE
Change,Whichever is First
t
OH
303030OE High to Output High Zt
DF
t
GHQZ
t
GLQX
t
OLZ
OE to Output Low Z
t
EHQZ
t
HZ
CE High to Output High Z
t
ELQX
t
LZ
t
GLQV
CE to Output Low Z
t
OE
OE to Output Delay
t
PHQV
t
PWH
PWD High to Output Delay
t
ELQV
t
CE
CE to Output Delay
t
AVQV
t
ACC
Address to Output Delay
t
AVAV
t
RC
Read Cycle Time
Versions V
CC
± 5%
V
CC
± 10%
LH28F008SA-85
(4)
UnitLH28F008SA-85
(5)
LH28F008SA-12
(5)
Symbol Parameter Notes Min Max Min Max MaxMin
85
85
85
400
40
55
90
90
90
400
45
55 55
50
400
120
120
120
3
3
3
3
2
2
8M (1M × 8) Flash Memory LH28F008SA
7-59
STANDBY DEVICE AND
ADDRESS SELECTION OUTPUTS ENABLED DATA VALID STANDBY
ADDRESSES (A)
CE (E)
OE (G)
WE (W)
DATA (D/Q)
PWD (P)
HIGH Z
t
AVAV
VALID OUTPUT
V
CC
POWER-UP
HIGH Z
t
EHQZ
t
GHQZ
t
OH
t
PHQV
t
AVQV
t
ELQX
t
ELQV
t
GLQX
ADDRESSES STABLE
V
CC
POWER-DOWN
t
GLQV
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
5.0 V
GND
V
CC
Figure 8. AC Waveform for Read Operations
LH28F008S A 8M (1M × 8) F la sh Memory
7-60
AC CHARACTERISTI CS - W ri te Operat ion s(1)
NOTES:
1. Read timing charac teristi cs during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics
for Read-Only Operations.
2. Sampled, not 100% teste d.
3. Refer to Ta ble 3 for val id AIN for byte write or b lock erasure.
4. Refer to Ta ble 3 for val id DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory,
including byte program and verif y (byt e wr it e) and block precondition, precondition verify, erase and erase ver if y (block er as e) .
6. Byte write and b lock erase durations are measure t o com p letion (SR.7 = 1, R Y/BY = VOH). VPP should be held at V PPH unt il determination
of byte write/block erase success (SR.3/4/ 5 = 0) .
7. See H igh Speed AC Input/ Out p ut Reference Wavef orms and H igh Speed AC Testing Load Circuits for test ing charact e rist ics.
8. See A C Input/O utput Reference Waveforms and AC Testing Load C ircuits for testing characteristics.
ns
ns
ns
ns
ns
ns
ns
ns
ns
Versions V
CC
± 5%
V
CC
± 10%
LH28F008SA-85
(7)
UnitLH28F008SA-85
(8)
LH28F008SA-12
(8)
Symbol Parameter Notes Min Max Min Max MaxMin
t
QVVL
00 02, 6
V
PP
Hold from Valid SRD,
RY/BY High
t
VPH
t
WHGL
Write Recovery before
Read 0 0 0
t
WHQV2
Duration of Block Erase
Operation 5, 6 0.3 0.3 0.3
µs
s
t
WHQV1
Duration of Byte Write
Operation 5, 6 6 6 6 µs
ns
ns
ns
100
100100
t
WHRL
WE High to RY/BY Going
Low
WE Pulse Width High
t
WHWL
t
WPH
1209085t
AVAV
t
WC
Write Cycle Time
t
PHWL
t
PS
PWD High Recovery to
WE Going Low 2 1 1 1
t
ELWL
t
CS
CE Setup to WE Going
Low 10 10 10
40
t
WLWH
t
WP
WE Pulse Width 40 40
V
PP
Setup to WE Going
High
t
VPWH
t
VPS
Address Setup to WE Going
High
t
AVWH
t
AS
Data Setup to WE Going
High
t
DVWH
t
DS
Data Hold from WE High
t
WHDX
t
DH
t
WHAX
Address Hold from WE
High
t
AH
t
WHEH
CE Hold from WE High
t
CH
2
3
4
100
40
40
5
5
10
30
100 100
40 40
40 40
5 5
5 5
10 10
30 30
µs
8M (1M × 8) Flash Memory LH28F008SA
7-61
BLOCK ERASE AND BYTE WRITE PERFORMANCE
NOTES:
1. 25°C, 12.0 VPP.
2. Excludes System -Level Overhead.
ORD ERIN G INFORMATION
s
s
Parameter Notes LH28F008SA-85 LH28F008SA-12 Unit
Min Typ
(1)
Max
Block Erase Time
Block Write Time
2
2
1.6
0.6
10
2.1
1.6
0.6
10
2.1
Min Typ
(1)
Max
L H 2 8 F 0 0 8 S A T - 8 5
PACKAGE
T = STANDARD 40 LEAD TSOP ACCESS SPEED
85=85 ns
12=120 ns
LH28F008S A 8M (1M × 8) F la sh Memory
7-62
WRITE BYTE WRITE
OR ERASE SETUP
COMMAND
ADDRESSES (A)
CE (E)
HIGH Z
WRITE
VALID ADDRESS AND DATA
(BYTE WRITE) OR ERASE
CONFIRM COMMAND
AUTOMATED BYTE
WRITE OR
ERASE DELAY READ STATUS
REGISTER DATA
DATA (D/Q)
RY/BY (R)
OE (G)
WE (W)
PWD (P)
WRITE READ ARRAY
COMMAND
V
PP
(V)
V
CC
POWER-UP
AND STANDBY
A
IN
A
IN
t
AVAV
t
AVWH
t
WHAX
t
WHGL
t
WHEH
t
ELWL
t
WHWL
t
WLWH
t
DVWH
t
WHDX
t
PHWL
t
VPWH
t
WHRL
t
QVVL
D
IN
D
IN
D
IN
VALID
SRD
t
WHQV1, 2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
PPH
V
PPL
V
IH
V
IL
Figure 9. AC Waveform for Wri te Operati on s
8M (1M × 8) Flash Memory LH28F008SA
7-63
ALTERNATIVE CE-CONTROLLE D WRIT ES
NOTES:
1. Chip-Enable Cont rolled Writes: Write operations are driven by the val id combinat ion of CE and WE. In system s where CE def ines the wr it e
pulsew idth (wit hin a longer WE t iming wavefor m), a ll setup, hold and inactive W E times should be measured relative to the C E wavef orm.
2. Sampled, not 10 0% teste d.
3. Refer to Ta ble 3 for val id AIN for byte write or block erasure.
4. Refer to Ta ble 3 for val id DIN for byte write or block erasure.
5. Byte wr it e and b lock erase durat ions are m ea sur ed to complet ion (SR.7 = 1, RY/BY = VOH). VPP should be held at VPPH until determination
of byte write/block erase success (SR.3/4/ 5 = 0) .
6. See H igh Speed AC Input/ Out p ut Reference Wavef orms and H igh Speed AC Testing Load Circuits for test ing charact e rist ics.
7. See A C Input/Output Ref erence Wavefor ms and A C Testing Load C ir cuits f or test ing characterist ics.
ns
ns
ns
ns
ns
ns
ns
ns
ns
Versions VCC ± 5%
VCC ± 10%
LH28F008SA-85(6)
UnitLH28F008SA-85(7) LH28F008SA-12(7)
Symbol Parameter Notes Min Max Min Max MaxMin
tQVVL 00 02, 5
VPP Hold from Valid SRD,
RY/BY High
tVPH
tEHGL Write Recovery before
Read 0 0 0
tEHQV2 Duration of Block Erase
Operation 5 0.3 0.3 0.3
µs
s
tEHQV1 Duration of Byte Write
Operation 5 6 6 6 µs
ns
ns
ns
100
100100
tEHRL CE High to RY/BY Going
Low
CE Pulse Width High
tEHEL tEPH
1209085tAVAV tWC Write Cycle Time
tPHEL tPS PWD High Recovery to
CE Going Low 2 1 1 1
tWLEL tWS WE Setup to CE Going
Low 0 0 0
50
tELEH tCP CE Pulse Width 50 50
VPP Setup to CE Going
High
tVPEH tVPS
Address Setup to CE Going
High
tAVEH tAS
Data Setup to CE Going
High
tDVEH tDS
Data Hold from CE High
tEHDX tDH
tEHAX Address Hold from CE HightAH
tEHWH WE Hold from CE High
tWH
2
3
4
100
40
40
5
5
0
25
100 100
40 40
40 40
5 5
5 5
0 0
25 25
µs
LH28F008S A 8M (1M × 8) F la sh Memory
7-64
WRITE BYTE WRITE
OR ERASE SETUP
COMMAND
ADDRESSES (A)
WE (W)
HIGH Z
WRITE
VALID ADDRESS AND DATA
(BYTE WRITE) OR ERASE
CONFIRM COMMAND
AUTOMATED BYTE
WRITE OR
ERASE DELAY READ STATUS
REGISTER DATA
DATA (D/Q)
RY/BY (R)
OE (G)
CE (E)
PWD (P)
WRITE READ ARRAY
COMMAND
V
PP
(V)
V
CC
POWER-UP
AND STANDBY
A
IN
A
IN
t
AVAV
t
AVEH
t
EHAX
t
EHGL
t
EHWH
t
WLEL
t
EHEL
t
ELEH
t
DVEH
t
EHDX
t
PHEL
t
VPEH
t
EHRL
t
QVVL
D
IN
D
IN
D
IN
VALID
SRD
t
EHQV1, 2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
PPH
V
PPL
V
IH
V
IL
Figure 10. A lternate AC Waveform for Wr ite Operations
8M (1M × 8) Flash Memory LH28F008SA
7-65
PACKAGE DIAGRAMS
44-Lead SOP
LH28F008S A 8M (1M × 8) F la sh Memory
7-66
40-Lead TSOP (Type I)
8M (1M × 8) Flash Memory LH28F008SA
7-67
ORD ERIN G INFORMATION
N 44-pin SOP
T 40-pin TSOP (Type I)
LH28F008SA
Device Type X
Package
FLASH-1
Example: LH28F008SAT-85 (8M Dual Volt (5/12) Flash Memory, 85 ns, 40-pin TSOP (Type I))
8M Dual Volt (5/12) Flash Memory
-##
Speed
85 ns
120 ns
LH28F008S A 8M (1M × 8) F la sh Memory
7-68
