Intel® PXA270 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
■High-performance processor:
—Intel XScale® microarchitecture with
Intel® Wireless MMX™ Technology
—7 Stage pipeline
—32 KB instruction cache
—32 KB data cache
—2 KB “mini” data cache
—Extensive data buffering
■256 Kbytes of internal SRAM for high
speed code or data storage preserved
during low-power states
■High-speed baseband processor interface
(Mobile Scalable Link)
■Rich serial peripheral set:
—AC’97 audio port
—I2S audio port
—USB Client controller
—USB Host controller
—USB On-The-Go controller
—Three high-speed UARTs (two with
hardware flow control)
—FIR and SIR infrared communications
port
■Hardware debug features — IEEE JTAG
interface with boundary scan
■Hardware performance-monitoring
features with on-chip trace buffer
■Real-time clock
■Operating-system timers
■LCD Controller
■Universal Subscriber Identity Module
interface
■Low power:
—Wireless Intel Speedstep® Technology
—Less than 500 mW typical internal
dissipation
—Supply voltage may be reduced to
0.85 V
—Four low-power modes
—Dynamic voltage and frequency
management
■High-performance memory controller:
—Four banks of SDRAM: up to 104 MHz
@ 2.5V, 3.0V, and 3.3V I/O interface
—Six static chip selects
—Support for PCMCIA and Compact
Flash
—Companion chip interface
■Flexible clocking:
—CPU clock from 104 to 624 MHz
—Flexible memory clock ratios
—Frequency changes
—Functional clock gating
■Additional peripherals for system
connectivity:
—SD Card / MMC Controller (with SPI
mode support)
—Memory Stick card controller
—Three SSP controllers
—Two I2C controllers
—Four pulse-width modulators (PWMs)
—Keypad interface with both direct and
matrix keys support
—Most peripheral pins double as GPIOs
Order Number 280002-003
ii Electrical, Mechanical, and Thermal Specification
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined. Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PXA270
processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
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Copyright © Intel Corporation, 2004
Intel® PXA270 Processor
Contents
Electrical, Mechanical, and Thermal Specification iii
Contents
1 Introduction .........................................................................................................1-1
1.1 About This Document.................................................................................1-1
1.1.1 Number Representation ................................................................1-1
1.1.2 Typographical Conventions ...........................................................1-1
1.1.3 Applicable Documents...................................................................1-2
2 Functional Overview ...........................................................................................2-1
3 Package Information...........................................................................................3-1
3.1 Package Information ..................................................................................3-1
3.2 Processor Materials....................................................................................3-6
3.3 Junction To Case Temperature Thermal Resistance.................................3-7
3.4 Processor Markings....................................................................................3-7
3.5 Tray Drawing ..............................................................................................3-8
4 Pin Listing and Signal Definitions .....................................................................4-1
4.1 Ball Map View.............................................................................................4-2
4.1.1 13x13 mm VF-BGA Ball map ........................................................4-2
4.1.2 23x23 mm PBGA Ball map............................................................4-6
4.2 Pin Usage...................................................................................................4-9
4.3 Signal Types.............................................................................................4-27
4.4 Memory Controller Reset and Initialization...............................................4-28
4.5 Power-Supply Pins ...................................................................................4-29
5 Electrical Specifications.....................................................................................5-1
5.1 Absolute Maximum Ratings........................................................................5-1
5.2 Operating Conditions..................................................................................5-1
5.2.1 Internal Power Domains ................................................................5-6
5.3 Power-Consumption Specifications............................................................5-6
5.4 DC Specification.........................................................................................5-8
5.5 Oscillator Electrical Specifications..............................................................5-9
5.5.1 32.768-kHz Oscillator Specifications .............................................5-9
5.5.2 13.000-MHz Oscillator Specifications..........................................5-11
5.6 CLK_PIO and CLK_TOUT Specifications ................................................5-12
5.7 48 MHz Output Specifications ..................................................................5-13
6 AC Timing Specifications ...................................................................................6-1
6.1 AC Test Load Specifications ......................................................................6-1
6.2 Reset and Power Manager Timing Specifications......................................6-2
6.2.1 Power-On Timing Specifications ...................................................6-2
6.2.2 Hardware Reset Timing.................................................................6-4
6.2.3 Watchdog Reset Timing ................................................................6-5
6.2.4 GPIO Reset Timing .......................................................................6-5
6.2.5 Sleep Mode Timing .......................................................................6-6
6.2.6 Deep-Sleep Mode Timing..............................................................6-7
Intel® PXA270 Processor
Contents
iv Electrical, Mechanical, and Thermal Specification
6.2.7 Standby-Mode Timing .................................................................6-10
6.2.8 Idle-Mode Timing.........................................................................6-10
6.2.9 Frequency-Change Timing..........................................................6-10
6.2.10 Voltage-Change Timing...............................................................6-11
6.3 GPIO Timing Specifications .....................................................................6-11
6.4 Memory and Expansion-Card Timing Specifications................................6-12
6.4.1 Internal SRAM Read/Write Timing Specifications .......................6-12
6.4.2 SDRAM Parameters and Timing Diagrams.................................6-12
6.4.3 ROM Parameters and Timing Diagrams .....................................6-18
6.4.4 Flash Memory Parameters and Timing Diagrams.......................6-23
6.4.5 SRAM Parameters and Timing Diagrams ...................................6-33
6.4.6 Variable-Latency I/O Parameters and Timing Diagrams.............6-36
6.4.7 Expansion-Card Interface Parameters and Timing Diagrams.....6-40
6.5 LCD Timing Specifications .......................................................................6-43
6.6 SSP Timing Specifications .......................................................................6-44
6.7 JTAG Boundary Scan Timing Specifications............................................6-45
Index ..............................................................................................................................1-1
Figures
2-1 Intel® PXA270 Processor Block Diagram, Typical System................................2-2
3-1 13x13mm VF-BGA Intel® PXA270 Processor Package, top view .....................3-1
3-2 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-2
3-3 13x13mm VF-BGA Intel® PXA270 Processor Package, side view ...................3-3
3-4 VF-BGA Product Information Decoder...............................................................3-3
3-5 23x23 mm PBGA Intel® PXA270 Processor Package (Top View) ....................3-4
3-6 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View) ...............3-4
3-7 23x23 mm PBGA Intel® PXA270 Processor Package (Side View) ...................3-5
3-8 PBGA Product Information Decoder ..................................................................3-5
3-9 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-6
3-10Intel® PXA270 Processor Production Markings, (Laser Mark on Top Side)......3-7
4-1 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) .............................4-2
4-2 13x13 mm VF-BGA Ball Map, Top View (upper right quarter) ...........................4-3
4-3 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) ...........................4-4
4-4 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) ........................4-5
4-5 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter) ..............................4-6
4-6 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter)............................4-7
4-7 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) ..............................4-8
4-8 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)............................4-9
6-1 AC Test Load .....................................................................................................6-2
6-2 Power On Reset Timing .....................................................................................6-3
6-3 Hardware Reset Timing .....................................................................................6-4
6-4 GPIO Reset Timing ............................................................................................6-5
6-5 Sleep Mode Timing ............................................................................................6-7
6-6 Deep-Sleep-Mode Timing ..................................................................................6-8
6-7 SDRAM Timing ................................................................................................6-15
6-8 SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing............................6-16
6-9 SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing ...............6-17
6-10SDRAM Fly-by DMA Timing.............................................................................6-18
Intel® PXA270 Processor
Contents
Electrical, Mechanical, and Thermal Specification v
6-1132-Bit Non-burst ROM, SRAM, or Flash Read Timing .....................................6-20
6-1232-Bit Burst-of-Eight ROM or Flash Read Timing ............................................6-21
6-13Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing..........6-22
6-1416-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing ....................................6-23
6-15Synchronous Flash Burst-of-Eight Read Timing ..............................................6-26
6-16Synchronous Flash Stacked Burst-of-Eight Read Timing ................................6-27
6-17First-Access Latency Configuration Timing......................................................6-28
6-18Synchronous Flash Burst Read Example.........................................................6-30
6-1932-Bit Flash Write Timing .................................................................................6-31
6-2032-Bit Stacked Flash Write Timing ...................................................................6-32
6-2116-Bit Flash Write Timing .................................................................................6-33
6-2232-Bit SRAM Write Timing ...............................................................................6-35
6-2316-bit SRAM Write for 4/2/1 Byte(s) Timing .....................................................6-36
6-2432-Bit VLIO Read Timing .................................................................................6-38
6-2532-Bit VLIO Write Timing..................................................................................6-39
6-26Expansion-Card Memory or I/O 16-Bit Access Timing.....................................6-41
6-27Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ............6-42
6-28LCD Timing Definitions.....................................................................................6-43
6-29SSP Master Mode Timing Definitions...............................................................6-44
6-30Timing Diagram for SSP Slave Mode Transmitting Data
to an External Peripheral..................................................................................6-44
6-31Timing Diagram for SSP Slave Mode Receiving Data
from External Peripheral...................................................................................6-45
6-32JTAG Boundary-Scan Timing...........................................................................6-46
Tables
1-1 Supplemental Documentation ............................................................................1-2
3-1 Processor Material Properties ............................................................................3-7
4-1 Pin Usage Summary ........................................................................................4-10
4-2 Pin Usage and Mapping Notes.........................................................................4-27
4-3 Signal Types.....................................................................................................4-28
4-4 Memory Controller Pin Reset Values ...............................................................4-28
4-5 Discrete (13x13 VF-BGA) Power Supply Pin Summary...................................4-29
5-1 Absolute Maximum Ratings................................................................................5-1
5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2
5-3 Memory Voltage and Frequency Electrical Specifications .................................5-4
5-4 Core Voltage and Frequency Electrical Specifications.......................................5-4
5-5 Internally Generated Power Domain Descriptions .............................................5-6
5-6 Core Voltage Specifications For Lower Power Modes .......................................5-6
5-7 Power-Consumption Specifications....................................................................5-7
5-8 Standard Input, Output, and I/O Pin DC Operating Conditions ..........................5-8
5-9 Typical 32.768-kHz Crystal Requirements .........................................................5-9
5-10 Typical External 32.768-kHz Oscillator Requirements ....................................5-11
5-11Typical 13.000-MHz Crystal Requirements......................................................5-11
5-12Typical External 13.000-MHz Oscillator Requirements....................................5-12
5-13CLK_PIO Specifications ...................................................................................5-12
5-14CLK_TOUT Specifications ...............................................................................5-12
5-1548 MHz Output Specifications ..........................................................................5-13
6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions ..........................6-1
6-2 Power-On Timing Specifications (OSCC[CRI] = 0) ............................................6-3
Intel® PXA270 Processor
Contents
vi Electrical, Mechanical, and Thermal Specification
6-3 Hardware Reset Timing Specifications (OSCC[CRI] = 0) ..................................6-4
6-4 Hardware Reset Timing Specifications (OSCC[CRI] = 1) .................................6-5
6-5 GPIO Reset Timing Specifications .....................................................................6-6
6-6 Sleep-Mode Timing Specifications.....................................................................6-7
6-7 Deep-Sleep Mode Timing Specifications ...........................................................6-8
6-8 GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode .................................6-9
6-9 Standby-Mode Timing Specifications...............................................................6-10
6-10Idle-Mode Timing Specifications ......................................................................6-10
6-11Frequency-Change Timing Specifications .......................................................6-10
6-12Voltage-Change Timing Specification for a 1-Byte Command.........................6-11
6-13GPIO Timing Specifications .............................................................................6-11
6-14SRAM Read/Write AC Specification ................................................................6-12
6-15SDRAM Interface AC Specifications ................................................................6-13
6-16ROM AC Specification .....................................................................................6-18
6-17Synchronous Flash Read AC Specifications....................................................6-24
6-18Flash Memory AC Specification .......................................................................6-30
6-19SRAM Write AC Specification ..........................................................................6-34
6-20VLIO Timing .....................................................................................................6-37
6-21Expansion-Card Interface AC Specifications ...................................................6-40
6-22LCD Timing Specifications ...............................................................................6-43
6-23SSP Master Mode Timing Specifications .........................................................6-44
6-24Timing Specification SSP Slave Mode Transmitting Data
to External Peripheral.......................................................................................6-45
6-25Timing Specification for SSP Slave Mode Receiving Data
from External Peripheral ..................................................................................6-45
6-26Boundary Scan Timing Specifications..............................................................6-45
Intel® PXA270 Processor
Contents
Electrical, Mechanical, and Thermal Specification vii
Revision History
§§
Date Revision Description
April 2004 -001 First public release of the EMTS
June 2004 -002 Added 23x23 mm 360-ball PBGA package
June 2004 -003 Added 624-MHz active and idle power consumption values to
Table 5-7.
Intel® PXA270 Processor
Contents
viii Electrical, Mechanical, and Thermal Specification
Electrical, Mechanical, and Thermal Specification 1-1
Introduction 1
The Intel® PXA270 processor (PXA270 processor) provides industry-leading multimedia
performance, low-power capabilities, rich peripheral integration and second generation memory
stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances
in mobile technology over its predecessor, the Intel® PXA255 processor. These same attributes
and features also make the PXA270 processor ideal for embedded applications. The PXA270
processor redefines scalability by operating from 104 MHz up to 624 MHz, providing enough
performance for the most demanding mobile applications.
The PXA270 processor is the first Intel processor to include Intel® Wireless MMX™ technology,
enabling high-performance, low-power multimedia acceleration with a general-purpose instruction
set. Intel® Quick Capture technology provides a flexible and powerful camera interface for
capturing digital images and video. While performance is key in the PXA270 processor, power
consumption is also a critical component. The new capabilities of Wireless Intel SpeedStep®
technology set the standard for low-power consumption.
The PXA270 processor is offered in two packages: 13x13 mm VFBGA and 23x23 mm PBGA.
1.1 About This Document
This document constitutes the electrical, mechanical, and thermal specifications for the PXA270
processor. It contains a functional overview, mechanical data, package signal locations, targeted
electrical specifications, and functional bus waveforms. For detailed functional descriptions other
than parametric performance, refer to the Intel® PXA27x Processor Family Developers Manual.
1.1.1 Number Representation
All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have
a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is represented as 0x6B in
hexadecimal and 0b110_1011 in binary.
1.1.2 Typographical Conventions
All signal and register-bit names appear in uppercase. Active low items are prefixed with a
lowercase “n”.
Bits within a signal name are enclosed in angle brackets:
EXTERNAL_ADDRESS<31:0>
nCS<1>
Bits within a register bit field are enclosed in square brackets:
REGISTER_BITFIELD[3:0]
REGISTER_BIT[0]
1-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Introduction
Single-bit items have either of two states:
•clear — the item contains the value 0b0. To clear a bit, write 0b0 to it.
•set — the item contains the value 0b1. To set a bit, write 0b1 to it.
1.1.3 Applicable Documents
Table 1-1 lists supplemental information sources for the PXA270 processor. Contact an Intel
representative for the latest document revisions and ordering instructions.
§§
Table 1-1. Supplemental Documentation
Document Title
Intel® PXA27x Processor Family Developers Manual
ARM® Architecture Version 5T Specification (Document number ARM* DDI 0100D-10), and ARM®
Architecture Reference Manual (Document number ARM* DDI 0100B)
Intel® XScale™ Core Developer’s Manual
Intel® Wireless MMX™ Technology Developer’s Guide
Intel® PXA27x Processor Design Guide
Intel® PXA27x Processor Power Supply Requirements Application Note
Electrical, Mechanical, and Thermal Specification 2-1
Functional Overview 2
The Intel® PXA270 processor is an integrated system-on-a-chip microprocessor for high
performance, dynamic, low-power portable handheld and hand-set devices as well as embedded
platforms. It incorporates the Intel XScale® technology which complies with the ARM* version
5TE instruction set (excluding floating-point instructions) and follows the ARM* programmer’s
model. The PXA270 processor also provides Intel® Wireless MMX™ media enhancement
technology, which supports integer instructions to accelerate audio and video processing. In
addition, it incorporates Wireless Intel Speedstep® Technology, which provides sophisticated
power management capabilities enabling excellent MIPs/mW performance.
The PXA270 processor provides a scalable, bi-directional data interface to a cellular baseband
processor, supporting seven logical channels and other features. The operating-system (OS) timer
channels and synchronous serial ports (SSPs) also accept an external network clock input so that
they can be synchronized to the cellular network. The processor also provides a Universal
Subscriber Identity Module* (USIM) card interface.
The PXA270 processor memory interface gives designers flexibility as it supports a variety of
external memory types. The processor also provides four 64 kilobyte banks of on-chip SRAM,
which can be used for program code or multimedia data. Each bank can be configured
independently to retain its contents when the processor enters a low-power mode. An integrated
LCD panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray
scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit color pixels. A 256-byte palette RAM provides flexible
color mapping.
A set of serial devices and general-system resources offers computational and connectivity
capability for a variety of applications. Figure 2-1 shows the block diagram for a typical PXA270
processor system.
2-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Functional Overview
Figure 2-1. Intel® PXA270 Processor Block Diagram, Typical System
General Purpose I/O
DMA
Controller
And
Bridge
MHz
Osc
XScale™
Micro-
Memory
Controller
PCMCIA & CF
Control
Variable
Control
Dynamic
Control
Static
Control
Memory
Memory
Latency I/O
ASIC
XCVR
ROM/
Flash/
SRAM
Socket 0
Socket 1
Intel® Wireless MMX™
USB
Host
System Bus
Controller
Internal
SRAM
13
Power Management
Clock Control
Primary GPIO
Peripheral Bus
Address
and
Data
Address and Data Bus
AC97
RTC
I2S
OS Timers
4 x PWM
Interrupt
USIM
3 x SSP
IrDA
I
2
C
Full Function
UART
USB
Client
BB Processor
Interface
Keypad
Interface
Bluetooth
UART
SDCard/MMC
Interface
Memory Stick
Interface
LCD
LCD
kHz
Osc
32.768
Controller
architecture
Intel®
JTAG
Controller
Debug
USB
OTG
Camera
Interface
SDRAM
General P ur pos e I/O
DMA
Controller
and
Bridge
MHz
Osc
XScale™
Mi cro-
Memory
Controller
PCMCIA & CF
Control
Var ia ble
Control
Dynamic
Control
Static
Control
Memory
Memory
Latency I/O AS IC
XCVR
SDRAM/
Boot
ROM/
Flash/
SRAM
Soc ket 0
Soc ket 1
Intel® Wireless MMX™
USB
Host
Sy stem Bus
Controller
Internal
SRAM
13
Power Management
Clock Cont ro l
P rimar y GP IO
Periphera l Bus
Address
and
Data
Address and Data B us
AC 97
RT C
I2S
OS Timers
4 x PWM
I nt erru pt
USIM
3 x SSP
IrDA
I
2
C
Full Function
UA RT
USB
Client
BB Processor
Interface
K e yp ad
Interface
Bluet ooth*
UART
SDCard/MMC
Interface
Memory Stick
Int erface
LCD
LCD
kHz
Osc
32 .76 8
Controller
architecture
Intel®
JTAG
Controller
Debug
ROM
USB
OTG
Camera
Interface
®
§§
Electrical, Mechanical, and Thermal Specification 3-1
Package Information 3
This chapter provides the mechanical specifications for the PXA270 processor.
The PXA270 processor is offered in two packages. The 13- by 13-mm, 356-ball, 0.50-mm VF-
BGA molded matrix array package is shown in Figure 3-1, Figure 3-2, and Figure 3-3. The 23- by
23-mm, 360-ball, 1.0-mm PBGA molded matrix array package is shown in Figure 3-5, Figure 3-6,
and Figure 3-7.
3.1 Package Information
Figure 3-1. 13x13mm VF-BGA Intel® PXA270 Processor Package, top view
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A1 Corner
3-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Package Information
Note: Figure 3-2 and Figure 3-3 show all dimensions in millimeters (mm).
Figure 3-2. 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view
11.50
11.50
0.50
0.50
A
B
0.15 M C A B
0.15 M C
ø0.30±0.05 (356)
13±0.10
13±0.10
Electrical, Mechanical, and Thermal Specification 3-3
Intel® PXA270 Processor
Package Information
Figure 3-4. VF-BGA Product Information Decoder
Figure 3-3. 13x13mm VF-BGA Intel® PXA270 Processor Package, side view
0.21±0.04 0.45±0.05
0.18 MIN. – 0.30 MAX.
1.0 MAX.
0.10 C
0.12 C
C
SEATING PLANE
0.91 MIN. -
Intel XScale® Family
Product Family Member
270=Discrete product
Package Type
LV=Leaded
RC=Lead-Free
Commercial
Temperature rating
Speed
312 MHz
416 MHz
520 MHz
624 MHz
Stepping
RCPXA270C0C4 16
3-4 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Package Information
Note: Figure 3-5, Figure 3-6 and Figure 3-7 show all dimensions in millimeters (mm).
Figure 3-5. 23x23 mm PBGA Intel® PXA270 Processor Package (Top View)
A1 CORNER
14.70 ± 0.25
Figure 3-6. 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View)
1.00
1.00
1.00
17
16
15
14
13
12
1.00
U
T
R
P
N
M
L
K
J
H
G
F
CORNER
PIN #1
4
111098765
E
D
C
B
A
321
V
W
Y
AA
AB
18
19
20
21
22
Electrical, Mechanical, and Thermal Specification 3-5
Intel® PXA270 Processor
Package Information
Figure 3-7. 23x23 mm PBGA Intel® PXA270 Processor Package (Side View)
0.20 C
C
0.15
//
SEATING PLANE
3
Figure 3-8. PBGA Product Information Decoder
Intel XScale® Family
Product Family Member
270 = Discrete product
Package Type
FW = Leaded
NH = Lead-Free
Temperature Rating
C = -25 to 85 C
E = -40 to 85 C
Speed
312 MHz
416 MHz
520 MHz
Stepping
FWPXA270C1 C 4 16
Electrical, Mechanical, and Thermal Specification 3-7
Intel® PXA270 Processor
Package Information
3.3 Junction To Case Temperature Thermal Resistance
3.4 Processor Markings
The diagram in this section details the processor’s top markings, which identify the PXA270
processor in the 356-ball VF-BGA and 360-ball PBGA package. Refer to Figure 3-4 for product
information. A Pb-Free (lead-free) package is indicated by the letter “E” on the 3rd line of
information (Intel legal line). The “E” appears after the date stamp.
Table 3-1. Processor Material Properties
Component VF-BGA Material PBGA Material
Mold compound ShinEtsu KMC 2500 VAT1 Sumitomo G770LE
Solder balls 63 Sn/37 Pb† 63 Sn/37 Pb†
†Subsequent processor steppings may use Pb-free (94.5 Sn/5.0 Ag/ 0.5 Cu) balls.
Parameter VF-BGA Value and Units PBGA Value and Units
Theta Jc 2 degrees C / watt 1.4 degrees C / watt
Figure 3-10. Intel® PXA270 Processor Production Markings, (Laser Mark on Top Side)
g
Laser Mark on top side of Package
Product
Lot #
Intel Legal
i
PXA270C0C416
FPO#
M C ‘03
TAIWAN
PIN 1 INDICATOR
COO
g
Laser Mark on top side of Package
Product
Lot #
Intel Legal
i
PXA270C0C416
FPO#
M C ‘03
TAIWAN
PIN 1 INDICATOR
COO
3-8 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Package Information
3.5 Tray Drawing
For tray drawing information, refer to the Intel Developer website for the Intel® Wireless
Communications and Computing Package Users Guide.
§§
Electrical, Mechanical, and Thermal Specification 4-1
Pin Listing and Signal Definitions 4
This chapter describes the signals and pins for the Intel® PXA270 processor.
For descriptions of all PXA270 processor signals, refer to the “System Architecture” chapter in the
Intel® PXA27x Processor Family Developer’s Manual.
Table 4-2 lists the mapping of signals to specific package pins. Many of the package pins are
multiplexed so that they can be configured for use as a general purpose I/O signal or as one of two
or three alternate functions using the GPIO alternate-function select registers. Some signals can be
configured to appear on one of several different package pins.
4-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
4.1 Ball Map View
Note: In the following ball map figures the lowercase letter “n”, which normally indicates negation,
appears as uppercase “N”.
4.1.1 13x13 mm VF-BGA Ball map
Figure 4-1 through Figure 4-4 shows the ball map for the VF-BGA PXA270 processor.
Figure 4-1. 13x13 mm VF-BGA Ball Map, Top View (upper left quarter)
123456789101112
AVSS_CORE VSS_CORE GPIO<15> VCC_MEM VCC_SRAM MA<1> VCC_CORE VCC_SRAM VCC_SRAM GPIO<49> GPIO<47> VCC_IO
BVSS_CORE VSS_CORE NCS<0> VCC_SRAM VSS_CORE GPIO<33> GPIO<78> VCC_MEM GPIO<18> GPIO<12> GPIO<46> VCC_CORE
CMA<18> MA<22> VCC_MEM MA<24> VSS_MEM MA<0> GPIO<80> GPIO<79> RDNWR GPIO<13> GPIO<11> GPIO<31>
DMA<17> MA<21> VCC_CORE MA<23> VSS_MEM MA<25> VSS_CORE VSS_CORE VSS_MEM VSS_CORE VSS_IO VSS_CORE
EMA<13> VCC_MEM MA<19> MA<20>
FVCC_MEM MA<14> MA<16> VSS_MEM
GMA<8> MA<11> MA<12> MA<15>
HVCC_MEM MA<9> MA<10> VSS_MEM
JMA<3> MA<6> MA<7> VSS_MEM
KMD<15> MA<4> MA<5> MA<2> VSS_CORE VSS_CORE VSS_CORE
LMD<14> MD<31> VCC_MEM VSS_MEM VSS_CORE VSS_CORE VSS_CORE
MVCC_MEM MD<30> MD<29> MD<13> VSS_CORE VSS_CORE VSS_CORE
Electrical, Mechanical, and Thermal Specification 4-3
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Figure 4-2. 13x13 mm VF-BGA Ball Map, Top View (upper right quarter)
13 14 15 16 17 18 19 20 21 22 23 24
GPIO<113> GPIO<28> GPIO<37> VCC_IO GPIO<24> GPIO<16> GPIO<92> GPIO<32> GPIO<34> GPIO<118> VCC_USB VCC_USB A
GPIO<29> GPIO<38> GPIO<26> GPIO<23> GPIO<110> GPIO<112> GPIO<35> GPIO<44> VCC_CORE USBC_P VCC_USB VCC_USB B
GPIO<30> GPIO<36> GPIO<27> GPIO<17> GPIO<111> GPIO<41> GPIO<45> USBC_N GPIO<42> GPIO<43> GPIO<88> GPIO<116> C
GPIO<22> GPIO<40> VSS_IO GPIO<25> GPIO<109> VSS_IO GPIO<39> GPIO<117> VSS_CORE GPIO<89> USBH_N<1> GPIO<114> D
GPIO<115> USBH_P<1> UIO VCC_USIM E
VSS_IO GPIO<90> GPIO<91> VCC_CORE F
VSS_CORE GPIO<59> GPIO<60> GPIO<58> G
VSS_IO GPIO<62> GPIO<63> GPIO<61> H
VSS_CORE GPIO<64> VCC_CORE VCC_LCD J
VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<66> GPIO<67> GPIO<65> K
VSS_CORE VSS_CORE VSS_CORE GPIO<68> GPIO<71> GPIO<69> VCC_CORE L
VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<73> VCC_CORE GPIO<70> M
4-4 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Figure 4-3. 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter)
NMD<27> MD<28> MD<12> VSS_MEM VSS_CORE VSS_CORE VSS_CORE
PVCC_MEM MD<11> MD<26> MD<10> VSS_CORE VSS_CORE VSS_CORE
RMD<24> VSS_MEM MD<25> MD<9> VSS_CORE VSS_CORE VSS_CORE
TMD<23> VCC_CORE MD<8> VSS_MEM
UMD<7> VCC_MEM VSS_CORE MD<5>
VMD<21> MD<22> MD<6> VSS_MEM
WMD<20> VCC_MEM VCC_CORE VSS_CORE
YMD<19> MD<4> MD<3> VSS_MEM
AA MD<18> VCC_MEM MD<2> MD<16> VSS_MEM NSDCAS VSS_CORE VSS_MEM VSS_MEM GPIO<55> GPIO<84> VSS_CORE
AB MD<1> VSS_MEM MD<17> MD<0> NWE GPIO<20> NSDCS<0> NSDCS<1> DQM<0> DQM<1> GPIO<56> GPIO<81>
AC VCC_MEM VCC_MEM VSS_MEM SDCLK<0> NOE VCC_MEM NSDRAS VCC_MEM DQM<2> DQM<3> GPIO<57> GPIO<85>
AD VCC_MEM VCC_MEM SDCLK<2> VCC_CORE GPIO<21> SDCKE SDCLK<1> VCC_MEM GPIO<82> GPIO<83> VCC_CORE VCC_BB
123456789101112
Electrical, Mechanical, and Thermal Specification 4-5
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Figure 4-4. 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter)
VSS_CORE VSS_CORE VSS_CORE VSS_IO GPIO<86> GPIO<87> GPIO<72> N
VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO<76> GPIO<75> VCC_LCD P
VSS_CORE VSS_CORE VSS_CORE GPIO<77> GPIO<19> GPIO<74> VCC_CORE R
TMS TCK TESTCLK GPIO<14> T
NTRST GPIO<9> TDI VSS_IO U
VSS GPIO<0> GPIO<10> TDO V
GPIO<3> NVDD_FAUL
TGPIO<4> CLK_REQ W
NRESET_O
UT NRESET PWR_EN GPIO<1> Y
VSS_BB GPIO<54> VSS_CORE VSS_IO GPIO<97> GPIO<95> VSS_IO PWR_CAP<
3> VSS TXTAL_IN TXTAL_OUT SYS_EN AA
GPIO<50> GPIO<53> GPIO<106> GPIO<105> GPIO<102> GPIO<99> GPIO<93> VCC_BATT PWR_CAP<
0> PWR_OUT BOOT_SEL NBATT_FAU
LT AB
GPIO<48> GPIO<52> GPIO<107> GPIO<103> GPIO<101> GPIO<100> GPIO<96> VCC_PLL PXTAL_IN PWR_CAP<
2> VSS VSS AC
GPIO<51> GPIO<108> GPIO<104> VCC_CORE VCC_IO GPIO<98> GPIO<94> VSS_PLL PXTAL_OUT PWR_CAP<
1> VSS VSS AD
13 14 15 16 17 18 19 20 21 22 23 24
4-6 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
4.1.2 23x23 mm PBGA Ball map
Figure 4-5. 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter)
1234567891011
AVSS_MEM VSS_MEM MA[25] GPIO[15] GPIO[79] GPIO[13] GPIO[12] GPIO[11] GPIO[46] GPIO[113] GPIO[29]
BVSS_MEM VCC_MEM VSS_MEM VCC_RAM MA[1] VSS_MEM VCC_RAM VCC_RAM VSS_MEM VCC_IO GPIO[30]
CMA[16] MA[17] VCC_MEM MA[24] VCC_RAM VCC_MEM GPIO[33] RDNWR VCC_MEM GPIO[47] GPIO[31]
DMA[14] MA[15] MA[19] MA[22] MA[0] NCS_0 GPIO[80] GPIO[78] GPIO[18] GPIO[49] VCC_CORE
EMA[11] MA[12] MA[21] MA[23] VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE
FMA[9] VSS_MEM VCC_MEM MA[20] VCC_CORE
GMA[7] MA[8] MA[13] MA[18] VSS_CORE
HMA[4] VSS_MEM VCC_MEM MA[10] VCC_CORE
JMA[3] MA[2] MA[6] MA[5] VSS_CORE VSS_CORE VSS_CORE VSS_CORE
KMD[15] MD[30] VCC_MEM MD[31] VSS_CORE VSS_CORE VSS_CORE
LMD[14] VSS_MEM MD[29] VCC_CORE VSS_CORE VSS_CORE VSS_CORE
Electrical, Mechanical, and Thermal Specification 4-7
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Figure 4- 6. 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter)
12 13 14 15 16 17 18 19 20 21 22
GPIO[22] GPIO[38] GPIO[26] GPIO[25] GPIO[23] GPIO[111] GPIO[92] GPIO[41] GPIO[44] VCC_USB VCC_USB A
VSS_IO GPIO[36] GPIO[24] VSS_IO GPIO[112] GPIO[39] VSS_IO GPIO[34] GPIO[118] GPIO[43] VCC_USB B
GPIO[40] GPIO[27] GPIO[16] GPIO[110] GPIO[32] GPIO[45] GPIO[117] NC NC GPIO[89] GPIO[88] C
GPIO[28] GPIO[37] VCC_IO GPIO[17] GPIO[109] GPIO[35] USBC_P VCC_USB GPIO[42] VSS_IO USBH_N[1] D
VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE USBC_N GPIO[116] GPIO[115] USBH_P[1] E
VCC_CORE GPIO[114] UIO VCC_USIM GPIO[61] F
VSS_CORE GPIO[91] GPIO[58] GPIO[60] GPIO[62] G
VCC_CORE GPIO[90] GPIO[59] VSS_IO GPIO[64] H
VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO[66] GPIO[63] VCC_LCD GPIO[69] J
VSS_CORE VSS_CORE VSS_CORE GPIO[67] GPIO[65] GPIO[68] GPIO[70] K
VSS_CORE VSS_CORE VSS_CORE VCC_CORE GPIO[71] GPIO[72] GPIO[73] L
4-8 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Figure 4-7. 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter)
MMD[13] MD[11] VCC_MEM MD[12] VSS_CORE VSS_CORE VSS_CORE
NMD[28] MD[26] MD[24] MD[25] VSS_CORE VSS_CORE VSS_CORE
PMD[27] VSS_MEM VCC_MEM MD[8] VSS_CORE VSS_CORE VSS_CORE VSS_CORE
RMD[10] MD[23] MD[21] MD[7] VCC_CORE
TMD[9] VSS_MEM VCC_MEM MD[5] VSS_CORE
UMD[22] MD[6] MD[4] MD[2] VCC_CORE
VMD[20] VSS_MEM VCC_MEM MD[16] VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE
WMD[19] MD[18] MD[1] MD[0] GPIO[20] NSDRAS SDCKE DQM[0] GPIO[55] GPIO[81] VCC_CORE
YMD[3] MD[17] VCC_MEM NSDCAS VCC_MEM GPIO[21] VCC_MEM NSDCS[1] VCC_MEM GPIO[84] GPIO[48]
AA VSS_MEM VCC_MEM NWE NOE NSDCS[0] VSS_MEM DQM[1] GPIO[82] VSS_MEM GPIO[85] VCC_BB
AB VSS_MEM VSS_MEM SDCLK[0] SDCLK[2] SDCLK[1] DQM[2] DQM[3] GPIO[56] GPIO[57] GPIO[83] VSS_BB
1234567891011
Electrical, Mechanical, and Thermal Specification 4-9
Intel® PXA270 Processor
Pin Listing and Signal Definitions
4.2 Pin Usage
The pin usage summary shown in Table 4-1 does not include the 36 center balls identified as K10
through R15 (VF-BGA) or J9 through P14 (PBGA), all of which function as VSS_CORE (see the
recommendations for connecting the 36 center balls in the Intel® PXA27x Processor Family
Design Guide).
Each signal’s alternate function inputs are shown in the upper section of each signal row and the
outputs are shown in the lower section of each signal row. For example, GPIO<48> has a primary
input function of CIF_DD<5> and a secondary output function of nPOE.
Figure 4- 8. 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)
VSS_CORE VSS_CORE VSS_CORE VCC_LCD GPIO[86] VSS_IO GPIO[87] M
VSS_CORE VSS_CORE VSS_CORE VSS_IO GPIO[75] GPIO[76] GPIO[74] N
VSS_CORE VSS_CORE VSS_CORE VSS_CORE GPIO[19] GPIO[14] GPIO[77] TESTCLK P
VCC_CORE TCK TMS TDO TDI R
VSS_CORE GPIO[4] NTRST CLK_REQ GPIO[9] T
VCC_CORE NBATT_FAU
LT GPIO[0] GPIO[1] GPIO[10] U
VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE BOOT_SEL NVDD_FAUL
TSYS_EN GPIO[3] V
GPIO[50] GPIO[106] GPIO[104] VCC_IO GPIO[96] PWR_CAP
[3] VSS PWR_OUT NRESET NRESET_O
UT PWR_EN W
GPIO[52] GPIO[105] GPIO[102] GPIO[97] GPIO[93] VCC_BATT PWR_CAP
[2]
PWR_CAP
[0] VSS TXTAL_IN TXTAL_OUT Y
GPIO[53] GPIO[108] VSS_IO GPIO[100] GPIO[98] GPIO[94] VSS_IO VSS_PLL PXTAL_OUT PWR_CAP
[1] VSS AA
GPIO[51] GPIO[54] GPIO[107] GPIO[103] GPIO[101] GPIO[99] GPIO[95] VCC_PLL PXTAL_IN VSS VSS AB
12 13 14 15 16 17 18 19 20 21 22
4-10 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Table 4-1. Pin Usage Summary (Sheet 1 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
VCC_MEM
D6 A3 MA<25> OCZ MA<25> MA<25> — — Refer to Table 4-4
C4 C4 MA<24> OCZ MA<24> MA<24> — — Refer to Table 4-4
D4 E4 MA<23> OCZ MA<23> MA<23> — — Refer to Table 4-4
C2 D4 MA<22> OCZ MA<22> MA<22> — — Refer to Table 4-4
D2 E3 MA<21> OCZ MA<21> MA<21> — — Refer to Table 4-4
E4 F4 MA<20> OCZ MA<20> MA<20> — — Refer to Table 4-4
E3 D3 MA<19> OCZ MA<19> MA<19> — — Refer to Table 4-4
C1 G4 MA<18> OCZ MA<18> MA<18> — — Refer to Table 4-4
D1 C2 MA<17> OCZ MA<17> MA<17> — — Refer to Table 4-4
F3 C1 MA<16> OCZ MA<16> MA<16> — — Refer to Table 4-4
G4 D2 MA<15> OCZ MA<15> MA<15> — — Refer to Table 4-4
F2 D1 MA<14> OCZ MA<14> MA<14> — — Refer to Table 4-4
E1 G3 MA<13> OCZ MA<13> MA<13> — — Refer to Table 4-4
G3 E2 MA<12> OCZ MA<12> MA<12> — — Refer to Table 4-4
G2 E1 MA<11> OCZ MA<11> MA<11> — — Refer to Table 4-4
H3 H4 MA<10> OCZ MA<10> MA<10> — — Refer to Table 4-4
H2 F1 MA<9> OCZ MA<9> MA<9> — — Refer to Table 4-4
G1 G2 MA<8> OCZ MA<8> MA<8> — — Refer to Table 4-4
J3 G1 MA<7> OCZ MA<7> MA<7> — — Refer to Table 4-4
J2 J3 MA<6> OCZ MA<6> MA<6> — — Refer to Table 4-4
K3 J4 MA<5> OCZ MA<5> MA<5> — — Refer to Table 4-4
K2 H1 MA<4> OCZ MA<4> MA<4> — — Refer to Table 4-4
J1 J1 MA<3> OCZ MA<3> MA<3> — — Refer to Table 4-4
K4 J2 MA<2> OCZ MA<2> MA<2> — — Refer to Table 4-4
A6 B5 MA<1> OCZ MA<1> MA<1> — — Refer to Table 4-4
C6 D5 MA<0> O CZ MA<0> MA<0> — — Refer to Table 4-4
L2 K4 MD<31> ICOC
ZMD<31> MD<31> — — Refer to Table 4-4
M2 K2 MD<30> ICOC
ZMD<30> MD<30> — — Refer to Table 4-4
M3 L3 MD<29> ICOC
ZMD<29> MD<29> — — Refer to Table 4-4
N2 N1 MD<28> ICOC
ZMD<28> MD<28> — — Refer to Table 4-4
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-11
Intel® PXA270 Processor
Pin Listing and Signal Definitions
N1 P1 MD<27> ICOC
ZMD<27> MD<27> — — Refer to Table 4-4
P3 N2 MD<26> ICOC
ZMD<26> MD<26> — — Refer to Table 4-4
R3 N4 MD<25> ICOC
ZMD<25> MD<25> — — Refer to Table 4-4
R1 N3 MD<24> ICOC
ZMD<24> MD<24> — — Refer to Table 4-4
T1 R2 MD<23> ICOC
ZMD<23> MD<23> — — Refer to Table 4-4
V2 U1 MD<22> ICOC
ZMD<22> MD<22> — — Refer to Table 4-4
V1 R3 MD<21> ICOC
ZMD<21> MD<21> — — Refer to Table 4-4
W1 V1 MD<20> ICOC
ZMD<20> MD<20> — — Refer to Table 4-4
Y1 W1 MD<19> ICOC
ZMD<19> MD<19> — — Refer to Table 4-4
AA1 W2 MD<18> ICOC
ZMD<18> MD<18> — — Refer to Table 4-4
AB3 Y2 MD<17> ICOC
ZMD<17> MD<17> — — Refer to Table 4-4
AA4 V4 MD<16> ICOC
ZMD<16> MD<16> — — Refer to Table 4-4
K1 K1 MD<15> ICOC
ZMD<15> MD<15> — — Refer to Table 4-4
L1 L1 MD<14> ICOC
ZMD<14> MD<14> — — Refer to Table 4-4
M4 M1 MD<13> ICOC
ZMD<13> MD<13> — — Refer to Table 4-4
N3 M4 MD<12> ICOC
ZMD<12> MD<12> — — Refer to Table 4-4
P2 M2 MD<11> ICOC
ZMD<11> MD<11> — — Refer to Table 4-4
P4 R1 MD<10> ICOC
ZMD<10> MD<10> — — Refer to Table 4-4
R4 T1 MD<9> ICOC
ZMD<9> MD<9> — — Refer to Table 4-4
T3 P4 MD<8> ICOC
ZMD<8> MD<8> — — Refer to Table 4-4
U1 R4 MD<7> ICOC
ZMD<7> MD<7> — — Refer to Table 4-4
V3 U2 MD<6> ICOC
ZMD<6> MD<6> — — Refer to Table 4-4
Table 4-1. Pin Usage Summary (Sheet 2 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-12 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
U4 T4 MD<5> ICOC
ZMD<5> MD<5> — — Refer to Table 4-4
Y2 U3 MD<4> ICOC
ZMD<4> MD<4> — — Refer to Table 4-4
Y3 Y1 MD<3> ICOC
ZMD<3> MD<3> — — Refer to Table 4-4
AA3 U4 MD<2> ICOC
ZMD<2> MD<2> — — Refer to Table 4-4
AB1 W3 MD<1> ICOC
ZMD<1> MD<1> — — Refer to Table 4-4
AB4 W4 MD<0> ICOC
ZMD<0> MD<0> — — Refer to Table 4-4
AC5 AA4 NOE OCZ nOE nOE — — Refer to Table 4-4
AB5 AA3 NWE OCZ nWE nWE — — Refer to Table 4-4
AC7 W6 NSDRAS OCZ nSDRAS nSDRAS — — Refer to Table 4-4
AA6 Y4 NSDCAS OCZ nSDCAS nSDCAS — — Refer to Table 4-4
AB9 W8 DQM<0> OCZ DQM<0> DQM<0> — — Refer to Table 4-4
AB10 AA7 DQM<1> OCZ DQM<1> DQM<1> — — Refer to Table 4-4
AC9 AB6 DQM<2> OCZ DQM<2> DQM<2> — — Refer to Table 4-4
AC10 AB7 DQM<3> OCZ DQM<3> DQM<3> — — Refer to Table 4-4
AB7 AA5 NSDCS<
0> OCZ nSDCS<0> nSDCS<0> — — Refer to Table 4-4
AB8 Y8 NSDCS<
1> OC nSDCS<1> nSDCS<1> — — Refer to Table 4-4
AD6 W7 SDCKE OC SDCKE SDCKE — — Refer to Table 4-4
AC4 AB3 SDCLK<0
>OC SDCLK<0> SDCLK<0> — — Refer to Table 4-4
AD7 AB5 SDCLK<1
>OCZ SDCLK<1> SDCLK<1> — — Refer to Table 4-4
AD3 AB4 SDCLK<2
>OC SDCLK<2> SDCLK<2> — — Refer to Table 4-4
C9 C8 RDNWR OCZ RDnWR RDnWR — — Refer to Table 4-4
B3 D6 NCS<0> OCZ nCS<0> nCS<0> — — Refer to Table 4-4
A3 A4 GPIO<15
>ICOC
ZGPIO<15>
———
Pu-1
Note[1] Note[4]
nPCE<1> nCS<1>
Refer to
Table 4-4 —
B9 D9 GPIO<18
>ICOC
ZGPIO<18> RDY — — Pd-0
Note[1] Note [3]
———
Table 4-1. Pin Usage Summary (Sheet 3 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-13
Intel® PXA270 Processor
Pin Listing and Signal Definitions
AB6 W5 GPIO<20
>ICOC
ZGPIO<20>
DREQ<0> MBREQ — Pu-1
Note[1] Note[3]
nSDCS<2>
Refer to
Table 4-4 ——
AD5 Y6 GPIO<21
>ICOC
ZGPIO<21>
———
Pu-1
Note[1] Note[3]
nSDCS<3>
Refer to
Table 4-4 DVAL<0> MBGNT
B6 C7 GPIO<33
>ICOC
ZGPIO<33>
FFRXD19 FFDSR19 —Pu-1
Note[1] Note [4]
DVAL<1> nCS<5>
Refer to
Table 4-4 MBGNT
A10 D10 GPIO<49
>ICOC
ZGPIO<49>
———
Pu-1
Note[1] Note [5]
—nPWE
Refer to
Table 4-4 —
B7 D8 GPIO<78
>ICOC
ZGPIO<78>
———
Pu-1
Note[1] Note[4]
nPCE<2> nCS<2>
Refer to
Table 4-4 —
C8 A5 GPIO<79
>ICOC
ZGPIO<79>
———
Pu-1
Note[1] Note[4]
PSKTSEL nCS<3>
Refer to
Table 4-4
PWM_OUT
<2>
C7 D7 GPIO<80
>ICOC
ZGPIO<80>
DREQ<1> MBREQ — Pu-1
Note[1] Note[4]
—nCS<4>
Refer to
Table 4-4
PWM_OUT
<3>
VCC_BB
AC13 Y11 GPIO<48
>ICOC
ZGPIO<48>
CIF_DD<5> — — Pu-1
Note[1] Note [5]
BB_OB_DAT<1
>
nPOE
Refer to
Table 4-4 —
AB13 W12 GPIO<50
>ICOC
ZGPIO<50>
CIF_DD<3> — SSPSCLK<
2> Pu-1
Note[1] Note [5]
BB_OB_DAT<2
>
nPIOIR
Refer to
Table 4-4
SSPSCLK<
2>
AD13 AB12 GPIO<51
>ICOC
ZGPIO<51>
CIF_DD<2> — — Pu-1
Note[1] Note [5]
BB_OB_DAT<3
>
nPIOIW
Refer to
Table 4-4 —
Table 4-1. Pin Usage Summary (Sheet 4 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-14 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
AC14 Y12 GPIO<52
>ICOC
ZGPIO<52> CIF_DD<4> SSPSCLK<3> — Pd-0
Note[1] Note [3]
BB_OB_CLK SSPSCLK<3> —
AB14 AA12 GPIO<53
>ICOC
ZGPIO<53> FFRXD USB_P2_3 — Pd-0
Note[1] Note [3]
BB_OB_STB CIF_MCLK SSPSYSCL
K
AA14 AB13 GPIO<54
>ICOC
ZGPIO<54> — BB_OB_WAIT CIF_PCLK Pd-0
Note[1] Note [3]
nPCE<2> —
AA10 W9 GPIO<55
>ICOC
ZGPIO<55> CIF_DD<1> BB_IB_DAT<1> — Pu-1
Note[1] Note [5]
— nPREG —
AB11 AB8 GPIO<56
>ICOC
ZGPIO<56> nPWAIT BB_IB_DAT<2> — Pu-1
Note[1] Note [5]
USB_P3_4 — —
AC11 AB9 GPIO<57
>ICOC
ZGPIO<57> nIOIS16 BB_IB_DAT<3> — Pu-1
Note[1] Note [5]
— — SSPTXD
AB12 W10 GPIO<81
>ICOC
ZGPIO<81> — CIF_DD<0> — Pu-1
Note[1] Note [3]
SSPTXD3 BB_OB_DAT<0
>—
AD9 AA8 GPIO<82
>ICOC
ZGPIO<82> SSPRXD3 BB_IB_DAT<0> CIF_DD<5> Pu-1
Note[1] Note [3]
——FFDTR
AD10 AB10 GPIO<83
>ICOC
ZGPIO<83> SSPSFRM3 BB_IB_CLK CIF_DD<4> Pd-0
Note[1] Note [3]
SSPSFRM3 FFTXD FFRTS
AA11 Y10 GPIO<84
>ICOC
ZGPIO<84> SSPSCLK3 BB_IB_STB CIF_FV Pd-0
Note[1] Note [3]
SSPSCLK3 — CIF_FV
AC12 AA10 GPIO<85
>ICOC
ZGPIO<85> FFRXD DREQ<2> CIF_LV Pd-0
Note[1] Note [3]
nPCE<1> BB_IB_WAIT CIF_LV
VCC_LCD
T24 P20 GPIO<14
>ICOC
ZGPIO<14> L_VSYNC SSPSFRM2 — Pd-0
Note[1] Note [3]
— SSPSFRM2 UCLK
R22 P19 GPIO<19
>ICOC
ZGPIO<19> SSPSCLK2 — FFRXD Pd-0
Note[1] Note [3]
SSPSCLK2 L_CS nURST
G24 G20 GPIO<58
>ICOC
ZGPIO<58> — LDD<0> — Pd-0
Note[1] Note [3]
— LDD<0> —
G22 H20 GPIO<59
>ICOC
ZGPIO<59> — LDD<1> — Pd-0
Note[1] Note [3]
— LDD<1> —
G23 G21 GPIO<60
>ICOC
ZGPIO<60> — LDD<2> — Pd-0
Note[1] Note [3]
— LDD<2> —
Table 4-1. Pin Usage Summary (Sheet 5 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-15
Intel® PXA270 Processor
Pin Listing and Signal Definitions
H24 F22 GPIO<61
>ICOC
ZGPIO<61> — LDD<3> — Pd-0
Note[1] Note [3]
— LDD<3> —
H22 G22 GPIO<62
>ICOC
ZGPIO<62> — LDD<4> — Pd-0
Note[1] Note [3]
— LDD<4> —
H23 J20 GPIO<63
>ICOC
ZGPIO<63> — LDD<5> — Pd-0
Note[1] Note [3]
— LDD<5> —
J22 H22 GPIO<64
>ICOC
ZGPIO<64> — LDD<6> — Pd-0
Note[1] Note [3]
— LDD<6> —
K24 K20 GPIO<65
>ICOC
ZGPIO<65> — LDD<7> — Pd-0
Note[1] Note [3]
— LDD<7> —
K22 J19 GPIO<66
>ICOC
ZGPIO<66> — LDD<8> — Pd-0
Note[1] Note [3]
— LDD<8> —
K23 K19 GPIO<67
>ICOC
ZGPIO<67> — LDD<9> — Pd-0
Note[1] Note [3]
— LDD<9> —
L21 K21 GPIO<68
>ICOC
ZGPIO<68> — LDD<10> — Pd-0
Note[1] Note [3]
— LDD<10> —
L23 J22 GPIO<69
>ICOC
ZGPIO<69> — LDD<11> — Pd-0
Note[1] Note [3]
— LDD<11> —
M24 K22 GPIO<70
>ICOC
ZGPIO<70> — LDD<12> — Pd-0
Note[1] Note [3]
— LDD<12> —
L22 L20 GPIO<71
>ICOC
ZGPIO<71> — LDD<13> — Pd-0
Note[1] Note [3]
— LDD<13> —
N24 L21 GPIO<72
>ICOC
ZGPIO<72> — LDD<14> — Pd-0
Note[1] Note [3]
— LDD<14> —
M22 L22 GPIO<73
>ICOC
ZGPIO<73> — LDD<15> — Pd-0
Note[1] Note [3]
— LDD<15> —
R23 N22 GPIO<74
>ICOC
ZGPIO<74> ———
Pd-0
Note[1] Note [3]
— L_FCLK_RD —
P23 N20 GPIO<75
>ICOC
ZGPIO<75> ———
Pd-0
Note[1] Note [3]
— L_LCLK _A0 —
P22 N21 GPIO<76
>ICOC
ZGPIO<76> ———
Pd-0
Note[1] Note [3]
— L_PCLK_WR —
R21 P21 GPIO<77
>ICOC
ZGPIO<77> ———
Pd-0
Note[1] Note [3]
— L_BIAS —
Table 4-1. Pin Usage Summary (Sheet 6 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-16 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
N22 M20 GPIO<86
>ICOC
ZGPIO<86> SSPRXD2 LDD<16> USB_P3_5 Pd-0
Note[1] Note [3]
nPCE<1> LDD<16> —
N23 M22 GPIO<87
>ICOC
ZGPIO<87> nPCE<2> LDD<17> USB_P3_1 Pd-0
Note[1] Note [3]
SSPTXD2 LDD<17> SSPSFRM2
VCC_IO
C11 A8 GPIO<11
>ICOC
ZGPIO<11> EXT_SYNC<0> SSPRXD2 USB_P3_1 Pd-0
Note[1]
Note
[3],
Note[11
CHOUT<0> PWM_OUT2 48_MHz
B10 A7 GPIO<12
>ICOC
ZGPIO<12> EXT_SYNC<1> CIF_DD<7> — Pd-0
Note[1]
Note
[3],
Note[11
CHOUT<1> PWM_OUT3 48_MHz
C10 A6 GPIO<13
>ICOC
ZGPIO<13> CLK_EXT KP_DKIN<7> KP_MKIN<
7> Pd-0
Note[1]
Note
[3],
Note[11
]
SSPTXD2 — —
A18 C14 GPIO<16
>ICOC
ZGPIO<16> KP_MKIN<5> — — Pd-0
Note[1] Note [3]
— PWM_OUT<0> FFTXD
C16 D15 GPIO<17
>ICOC
ZGPIO<17> KP_MKIN<6> CIF_DD<6> — Pd-0
Note[1] Note [3]
—PWM_OUT<1>—
D13 A12 GPIO<22
>ICOC
ZGPIO<22> SSPEXTCLK2 SSPSCLKEN2 SSPSCLK2 Pd-0
Note[1] Note [3]
KP_MKOUT<7
>SSPSYSCLK2 SSPSCLK2
B16 A16 GPIO<23
>ICOC
ZGPIO<23> — SSPSCLK — Pd-0
Note[1] Note [3]
CIF_MCLK SSPSCLK —
A17 B14 GPIO<24
>ICOC
ZGPIO<24> CIF_FV SSPSFRM — Pd-0
Note[1] Note [3]
CIF_FV SSPSFRM —
D16 A15 GPIO<25
>ICOC
ZGPIO<25> CIF_LV — — Pd-0
Note[1] Note [3]
CIF_LV SSPTXD —
B15 A14 GPIO<26
>ICOC
ZGPIO<26> SSPRXD CIF_PCLK FFCTS Pd-0
Note[1] Note [3]
———
C15 C13 GPIO<27
>ICOC
ZGPIO<27> SSPEXTCLK SSPSCLKEN CIF_DD<0> Pd-0
Note[1] Note [3]
SSPSYSCLK — FFRTS
A14 D12 GPIO<28
> ICOC
ZGPIO<28> AC97_BITCLK I2S_BITCLK SSPSFRM Pd-0
Note[1] Note [3]
I2S_BITCLK — SSPSFRM
B13 A11 GPIO<29
>ICOC
ZGPIO<29> AC97_SDATA_I
N_0 I2S_SDATA_IN SSPSCLK Pd-0
Note[1] Note [3]
SSPRXD2 — SSPSCLK
Table 4-1. Pin Usage Summary (Sheet 7 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-17
Intel® PXA270 Processor
Pin Listing and Signal Definitions
C13 B11 GPIO<30
>ICOC
ZGPIO<30> ———
Pd-0
Note[1] Note [3]
I2S_SDATA_O
UT AC97_SDATA_
OUT USB_P3_2
C12 C11 GPIO<31
>ICOC
ZGPIO<31> ———
Pd-0
Note[1] Note [3]
I2S_SYNC AC97_SYNC USB_P3_6
A20 C16 GPIO<32
>ICOC
ZGPIO<32> ———
Pd-0
Note[1] Note [3]
MSSCLK MMCLK —
A21 B19 GPIO<34
>ICOC
ZGPIO<34> FFRXD KP_MKIN<3> SSPSCLK3 Pd-0
Note[1] Note [3]
USB_P2_2 — SSPSCLK3
B19 D17 GPIO<35
> ICOC
ZGPIO<35> FFCTS USB_P2_1 SSPSFRM3 Pd-0
Note[1] Note [3]
—KP_MKOUT<6
>SSPTXD3
C14 B13 GPIO<36
>ICOC
ZGPIO<36> FFDCD SSPSCLK2 KP_MKIN<
7> Pd-0
Note[1] Note [3]
USB_P2_4 SSPSCLK2 —
A15 D13 GPIO<37
>ICOC
ZGPIO<37> FFDSR SSPSFRM2 KP_MKIN<
3> Pd-0
Note[1] Note [3]
USB_P2_8 SSPSFRM2 FFTXD
B14 A13 GPIO<38
>ICOC
ZGPIO<38> FFRI KP_MKIN<4> USB_P2_3 Pd-0
Note[1] Note [3]
SSPTXD3 SSPTXD2 PWM_OUT
<1>
D19 B17 GPIO<39
> ICOC
ZGPIO<39> KP_MKIN<4> — SSPSFRM3 Pd-0
Note[1] Note [3]
USB_P2_6 FFTXD SSPSFRM3
D14 C12 GPIO<40
>ICOC
ZGPIO<40> SSPRXD2 — USB_P2_5 Pd-0
Note[1] Note [3]
KP_MKOUT<6
>FFDTR SSPSCLK3
C18 A19 GPIO<41
>ICOC
ZGPIO<41> FFRXD USB_P2_7 SSPRXD3 Pd-0
Note[1] Note [3]
KP_MKOUT<7
>FFRTS —
C21 D20 GPIO<42
> ICOC
ZGPIO<42> BTRXD ICP_RXD — Pd-0
Note[1] Note [3]
——CIF_MCLK
C22 B21 GPIO<43
>ICOC
ZGPIO<43> ——CIF_FV
Pd-0
Note[1] Note [3]
ICP_TXD BTTXD CIF_FV
B20 A20 GPIO<44
> ICOC
ZGPIO<44> BTCTS — CIF_LV Pd-0
Note[1] Note [3]
——CIF_LV
C19 C17 GPIO<45
> ICOC
ZGPIO<45> ——CIF_PCLK
Pd-0
Note[1] Note [3]
AC97_SYSCLK BTRTS SSPSYSCL
K3
Table 4-1. Pin Usage Summary (Sheet 8 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-18 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
B11 A9 GPIO<46
>ICOC
ZGPIO<46> ICP_RXD STD_RXD — Pd-0
Note[1] Note [3]
—PWM_OUT<2>—
A11 C10 GPIO<47
>ICOC
ZGPIO<47> CIF_DD<0> — — Pd-0
Note[1] Note [3]
STD_TXD ICP_TXD PWM_OUT
<3>
C23 C22 GPIO<88
>ICOC
ZGPIO<88> USBHPWR<1> SSPRXD2 SSPSFRM2 Pd-0
Note[1] Note [3]
— — SSPSFRM2
D22 C21 GPIO<89
>ICOC
ZGPIO<89> SSPRXD3 — FFRI Pd-0
Note[1] Note [3]
AC97_SYSCLK USBHPEN<1> SSPTXD2
A19 A18 GPIO<92
>ICOC
ZGPIO<92> MMDAT<0> — — Pd-0
Note[1] Note [3]
MMDAT<0> MSBS —
AB19 Y16 GPIO<93
>ICOC
ZGPIO<93> KP_DKIN<0> CIF_DD<6> — Pd-0
Note[1] Note [3]
AC97_SDATA_
OUT ——
AD19 AA17 GPIO<94
>ICOC
ZGPIO<94> KP_DKIN<1> CIF_DD<5> — Pd-0
Note[1] Note [3]
AC97_SYNC — —
AA18 AB18 GPIO<95
>ICOC
ZGPIO<95> KP_DKIN<2> CIF_DD<4> KP_MKIN<
6> Pd-0
Note[1] Note [3]
AC97_RESET_
n——
AC19 W16 GPIO<96
>ICOC
ZGPIO<96> KP_DKIN<3> MBREQ FFRXD Pd-0
Note[1] Note [3]
DVAL<1> KP_MKOUT
<6>
AA17 Y15 GPIO<97
>ICOC
ZGPIO<97> KP_DKIN<4> DREQ<1> KP_MKIN<
3> Pd-0
Note[1] Note [3]
—MBGNT—
AD18 AA16 GPIO<98
>ICOC
ZGPIO<98> KP_DKIN<5> CIF_DD<0> KP_MKIN<
4> Pd-0 Note
[1] Note [3]
AC97_SYSCLK — FFRTS
AB18 AB17 GPIO<99
>ICOC
ZGPIO<99> KP_DKIN<6> AC97_SDATA_I
N_1 KP_MKIN<
5> Pd-0 Note
[1] Note [3]
— — FFTXD
AC18 AA15 GPIO<10
0> ICOC
ZGPIO<100> KP_MKIN<0> DREQ<2> FFCTS Pd-0
Note[1] Note [3]
———
AC17 AB16 GPIO<10
1> ICOC
ZGPIO<101> KP_MKIN<1> — — Pd-0
Note[1] Note [3]
———
AB17 Y14 GPIO<10
2> ICOC
ZGPIO<102> KP_MKIN<2> — FFRXD Pd-0
Note[1] Note [3]
nPCE<1> — —
Table 4-1. Pin Usage Summary (Sheet 9 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-19
Intel® PXA270 Processor
Pin Listing and Signal Definitions
AC16 AB15 GPIO<10
3> ICOC
ZGPIO<103> CIF_DD<3> — — Pd-0
Note[1] Note [3]
—KP_MKOUT<0
>—
AD15 W14 GPIO<10
4> ICOC
ZGPIO<104> CIF_DD<2> — — Pd-0
Note[1] Note [3]
PSKTSEL KP_MKOUT<1
>—
AB16 Y13 GPIO<10
5> ICOC
ZGPIO<105> CIF_DD<1> — — Pd-0
Note[1] Note [3]
nPCE<2> KP_MKOUT<2
>—
AB15 W13 GPIO<10
6> ICOC
ZGPIO<106> CIF_DD<9> — — Pd-0
Note[1] Note [3]
—KP_MKOUT<3
>—
AC15 AB14 GPIO<10
7> ICOC
ZGPIO<107> CIF_DD<8> — — Pd-0
Note[1] Note [3]
—KP_MKOUT<4
>—
AD14 AA13 GPIO<10
8> ICOC
ZGPIO<108> CIF_DD<7> — — Pd-0
Note[1] Note [3]
CHOUT<0> KP_MKOUT<5
>—
D17 D16 GPIO<10
9> ICOC
ZGPIO<109> MMDAT<1> MSSDIO — Pd-0
Note[1] Note [3]
MMDAT<1> MSSDIO —
B17 C15 GPIO<11
0> ICOC
ZGPIO<110>
MMDAT<2>/
MMCCS<0> ——
Pd-0
Note[1] Note [3]
MMDAT<2>/
MMCCS<0> ——
C17 A17 GPIO<11
1> ICOC
ZGPIO<111>
MMDAT<3>/
MMCCS<1> ——
Pd-0
Note[1] Note [3]
MMDAT<3>/
MMCCS<1> ——
B18 B16 GPIO<11
2> ICOC
ZGPIO<112> MMCMD nMSINS — Pd-0
Note[1] Note [3]
MMCMD — —
A13 A10 GPIO<11
3> ICOC
ZGPIO<113> — — USB_P3_3 Pd-0
Note[1] Note [3]
I2S_SYSCLK AC97_RESET_
n—
D24 F19 GPIO<11
4>
Note [17]
ICOC
ZGPIO<114>
Note [17]
CIFDD_<1> ——
Pd-0
Note[1] Note [3]
UVS0 —
E21 E21 GPIO<11
5>
Note [17]
ICOC
ZGPIO<115>
Note [17]
DREQ<0> CIF_DD<3> MBREQ Pu-1
Note[1] Note [3]
UEN nUVS1 PWM_OUT
<1>
Table 4-1. Pin Usage Summary (Sheet 10 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-20 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
C24 E20 GPIO<11
6> ICOC
ZGPIO<116> CIF_DD<2> AC97_SDATA_I
N_0 UDET Pu-1
Note[1] Note [3]
DVAL<0> nUVS2 MBGNT
D20 C18 GPIO<11
7> ICOC
ZGPIO<117>
SCL — — Pu-1
Note[1]
Note
[3],
Note[12
]
SCL — —
A22 B20 GPIO<11
8> ICOC
ZGPIO<118>
SDA — — Pu-1
Note[1]
Note
[3],
Note[12
]
SDA — —
VCC_USB
B22 D18 USBC_P IAOA
ZUSBC_P USBC_P ——Hi-ZHi-Z
C20 E19 USBC_N IAOA
ZUSBC_N USBC_N ——Hi-ZHi-Z
E22 E22 USBH_P
<1> IAOA
ZUSBH_P<1
>USBH_P<1> ——Hi-ZHi-Z
D23 D22 USBH_N
<1> IAOA
ZUSBH_N<1
>USBH_N<1> ——Hi-ZHi-Z
VCC_USIM
F22 H19 GPIO<90
>ICOC
ZGPIO<90> KP_MKIN<5> USB_P3_5 CIF_DD<4> Pd-0
Note[1] Note [3]
—nURST—
F23 G19 GPIO<91
>ICOC
ZGPIO<91> KP_MKIN<6> USB_P3_1 CIF_DD<5> Pd-0
Note[1] Note [3]
— UCLK —
E23 F20 UIO ICOC
ZUIO UIO — — Driven
Low Hi-Z
VCC_REG
V22 U20 GPIO<0> ICOC
ZGPIO<0> GPIO<0> — — Pd-0
Note[1] Note [3]
Y24 U21 GPIO<1> ICOC
ZGPIO<1> GPIO<1> — — Pu-1
Note[1] Note [7]
W21 V22 GPIO<3> ICOC
ZGPIO<3> PWR_SCL — — Pu-1
Note[1] Hi-Z
W23 T19 GPIO<4> ICOC
ZGPIO<4> PWR_SDA — — Pu-1
Note[1] Hi-Z
U22 T22 GPIO<9>
Note [18] ICOC
ZGPIO<9>
Note [18] ——FFCTS
Pd-0
Note[1] Note [7]
HZ_CLK — CHOUT<0>
V23 U22 GPIO<10
>
Note [18]
ICOC
ZGPIO<10>
Note [18]
FFDCD — USB_P3_5 Pd-0
Note[1] Note [7]
HZ_CLK — CHOUT<1> Pd-0
Note[1] Note [7]
Table 4-1. Pin Usage Summary (Sheet 11 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-21
Intel® PXA270 Processor
Pin Listing and Signal Definitions
W24 T21 CLK_RE
QICOC
ZCLK_REQ CLK_REQ — — Pu-1 Note [8]
Y22 W20 NRESET IC nRESET nRESET — — Input -
Note [9] Input
Y21 W21 NRESET
_OUT OC nRESET_O
UT nRESET_OUT — — Low Note [8]
AB23 V19 BOOT_S
EL IC BOOT_SEL BOOT_SEL — — Input Input
Y23 W22 PWR_EN OC PWR_EN PWR_EN — — Note[16] Note [8]
AB24 U19 NBATT_F
AULT IC nBATT_FAU
LT nBATT_FAULT — — Low Input
W22 V20 NVDD_F
AULT IC nVDD_FAU
LT nVDD_FAULT — — Low Input
AA24 V21 SYS_EN ICOC
ZSYS_EN SYS_EN — — — Note [7]
AB21 Y19 PWR_CA
P<0> OA — PWR_CAP<0> — — — Note [7]
AD22 AA21 PWR_CA
P<1> OA — PWR_CAP<1> — — — Note [7]
AC22 Y18 PWR_CA
P<2> OA — PWR_CAP<2> — — — Note [7]
AA20 W17 PWR_CA
P<3> OA — PWR_CAP<3> — — — Note [7]
U21 T20 NTRST IC nTRST nTRST — — Input -
Note [9] Input
U23 R22 TDI IC TDI TDI — — Input -
Note [9] Input
V24 R21 TDO OCZ TDO TDO — — Hi-Z Hi-Z
T21 R20 TMS IC TMS TMS — — Input -
Note [9] Input
T22 R19 TCK IC TCK TCK — — Input Input
T23 P22 TESTCLK IC TESTCLK TESTCLK — — Pd-0 Input
VCC_OSC
AC21 AB20 PXTAL_I
NIA PXTAL_IN PXTAL_IN — — Note[2] Note [2]
AD21 AA20 PXTAL_O
UT OA PXTAL_OU
TPXTAL_OUT — — Note[2] Note [2]
AA22 Y21 TXTAL_I
NIA TXTAL_IN TXTAL_IN — — Note[2] Note [2]
AA23 Y22 TXTAL_O
UT OA TXTAL_OU
TTXTAL_OUT — — Note[2] Note [2]
AB22 W19 PWR_OU
TOA PWR_OUT PWR_OUT — — Hi-Z Hi-Z
Table 4-1. Pin Usage Summary (Sheet 12 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-22 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
SUPPLIES
AB20 Y17 VCC_BAT
TPS VCC_BATT VCC_BATT — — Input Input
A12 B10 VCC_IO PS VCC_IO VCC_IO — — Input Input
AD17 W15 VCC_IO PS VCC_IO VCC_IO — — Input Input
A16 D14 VCC_IO PS VCC_IO VCC_IO — — Input Input
B24 A21 VCC_US
BPS VCC_USB VCC_USB — — Input Input
A24 A22 VCC_US
BPS VCC_USB VCC_USB — — Input Input
A23 B22 VCC_US
BPS VCC_USB VCC_USB — — Input Input
B23 D19 VCC_US
BPS VCC_USB VCC_USB — — Input Input
P24 M19 VCC_LC
DPS VCC_LCD0 VCC_LCD — — Input Input
J24 J21 VCC_LC
DPS VCC_LCD1 VCC_LCD — — Input Input
P1 B2 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
C3 C3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
E2 C6 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
L3 C9 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AD2 F3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AC2 H3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AC1 K3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AD1 M3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
M1 P3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
H1 T3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
F1 V3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AD8 Y3 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
Table 4-1. Pin Usage Summary (Sheet 13 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-23
Intel® PXA270 Processor
Pin Listing and Signal Definitions
U2 Y5 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AA2 Y7 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AC8 Y9 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
B8 AA2 VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
A4 N/A VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AC6 N/A VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
W2 N/A VCC_ME
MPS VCC_MEM VCC_MEM — — Input Input
AD12 AA11 VCC_BB PS VCC_BB VCC_BB — — Input Input
AC20 AB19 VCC_PLL PS VCC_PLL VCC_PLL — — Input Input
A9 B4 VCC_SR
AM PS VCC_SRA
MVCC_SRAM — — Input Input
A8 B7 VCC_SR
AM PS VCC_SRA
MVCC_SRAM — — Input Input
A5 B8 VCC_SR
AM PS VCC_SRA
MVCC_SRAM — — Input Input
B4 C5 VCC_SR
AM PS VCC_SRA
MVCC_SRAM — — Input Input
B12 D11 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
A7 E6 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
D3 E8 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
J23 F5 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
L24 H5 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
F24 L4 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
AD16 E15 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
R24 E17 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
M23 F18 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
B21 H18 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
Table 4-1. Pin Usage Summary (Sheet 14 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-24 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
W3 L19 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
AD4 R5 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
T2 U5 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
AD11 V6 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
N/A V8 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
N/A W11 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
N/A R18 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
N/A U18 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
N/A V15 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
N/A V17 VCC_CO
RE PS VCC_COR
EVCC_CORE — — Input Input
E24 F21 VCC_USI
MPS VCC_USIM VCC_USIM — — Input Input
AA21 W18 VSS PS VSS VSS — — Input Input
AC24 Y20 VSS PS VSS VSS — — Input Input
AD24 AA22 VSS PS VSS VSS — — Input Input
AC23 AB21 VSS PS VSS VSS — — Input Input
AD23 AB22 VSS PS VSS VSS — — Input Input
V21 N/A VSS PS VSS VSS — — Input Input
D11 B12 VSS_IO PS VSS_IO VSS_IO — — Input Input
AA19 B15 VSS_IO PS VSS_IO VSS_IO — — Input Input
D15 B18 VSS_IO PS VSS_IO VSS_IO — — Input Input
N21 D21 VSS_IO PS VSS_IO VSS_IO — — Input Input
AA16 H21 VSS_IO PS VSS_IO VSS_IO — — Input Input
H21 M21 VSS_IO PS VSS_IO VSS_IO — — Input Input
F21 N19 VSS_IO PS VSS_IO VSS_IO — — Input Input
D18 AA14 VSS_IO PS VSS_IO VSS_IO — — Input Input
U24 AA18 VSS_IO PS VSS_IO VSS_IO — — Input Input
D5 A1 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
F4 A2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
Table 4-1. Pin Usage Summary (Sheet 15 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-25
Intel® PXA270 Processor
Pin Listing and Signal Definitions
H4 B1 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
J4 B3 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
AC3 B6 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
AB2 B9 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
L4 F2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
T4 H2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
V4 L2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
AA5 P2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
AA8 T2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
AA9 V2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
D9 AA1 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
N4 AA6 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
R2 AA9 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
C5 AB1 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
Y4 AB2 VSS_ME
MPS VSS_MEM VSS_MEM — — Input Input
AA13 AB11 VSS_BB PS VSS_BB VSS_BB — — Input Input
AD20 AA19 VSS_PLL PS VSS_PLL VSS_PLL — — Input Input
B2 E5 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
A2 E7 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
B1 E9 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
A1 G5 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
J21 J5 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
D10 E14 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
Table 4-1. Pin Usage Summary (Sheet 16 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
4-26 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
AA15 E16 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
M21 E18 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
U3 G18 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
AA7 J18 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
P21 P5 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
K21 T5 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
G21 V5 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
D21 V7 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
D12 V9 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
D8 P18 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
W4 T18 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
AA12 V14 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
B5 V16 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
D7 V18 VSS_CO
RE PS VSS_CORE VSS_CORE — — Input Input
Table 4-1. Pin Usage Summary (Sheet 17 of 17)
VF-BGA
Ball#
(13x13)
PBGA
Ball#
(23x23) Name Type Function
After
Reset
Primary
Function
Secondary
Alternate
Function
Third
Alternate
Function
Reset
State Sleep
State
NOTE: Refer to Table 4-2 for Numbered Notes on Reset and Sleep States.
Electrical, Mechanical, and Thermal Specification 4-27
Intel® PXA270 Processor
Pin Listing and Signal Definitions
4.3 Signal Types
Table 4-2. Pin Usage and Mapping Notes
Note Description
[1]
GPIO reset/deep sleep operation: After any reset is asserted or if the PXA270 processor is in deep sleep mode, these
pins are configured as GPIO inputs by default. The input buffers for these pins are disabled to prevent current drain and
must be enabled prior to use by clearing the read disable hold bit, PSSR[RDH]. Until RDH is cleared, each pin is pulled
high (Pu-1), pulled low (Pd-0), or floated (Hi-Z).
[2]
Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators and are not affected by either
reset or sleep. For more information, see the “Clocks and Power” chapter in the Intel® PXA27x Processor Family
Developer’s Manual.
[3]
GPIO sleep operation: During the transition into sleep mode, the configuration of these pins is determined by the
corresponding GPIO setting. This pin is not driven during sleep if the direction of the pin is selected to be an input. If the
direction of the pin is selected as an output, the value contained in the Power Manager GPIO Sleep-State register
(PGSR0/1/2/3) is driven out onto the pin and held while the PXA270 processor is in sleep mode.
Upon exit from sleep mode, GPIOs that are configured as outputs continue to hold the standby, sleep, or deep-sleep state
until software clears the peripheral control hold bit, PSSR[PH]. Software must clear this bit (by writing 0b1 to it) after the
peripherals have been fully configured, as described in Note[1], but before the process actually uses them.
GPIOs that are configured as inputs immediately after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
[4]
Static memory control pins: During sleep mode, these pins can be programmed either to drive the value in the Power
Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state,
software must set PCFR[FS]. If FS is not set, these pins function as described in Note[3] during the transition to sleep
mode.
[5]
PCMCIA control pins: During sleep mode, these pins can be programmed either to drive the value in the Power Manager
GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state, software
must set PCFR[FP]. If FP is not set, these pins function as described in Note[3] during the transition to sleep mode.
[6] (reserved)
[7]
When the power manager overrides the GPIO alternate function, the Power Manager GPIO Sleep-State registers
(PGSR0/1/2/3) and the PSSR[RDH] bit are ignored. Pullup and pulldown are disabled immediately after the power
manager overrides the GPIO function.
[8] Output functions during sleep mode
[9] Pull-up always enabled
[10] (reserved)
[11] Pins do not function during sleep mode if the OS timer is active
[12] Pins must be floated by software during sleep mode (floating does not happen automatically)
[13] (reserved)
[14] (reserved)
[15] The pin is three-stateable (Hi-Z) based on the value of PCFR[FS]. There is no PGSR0/1/2/3 setting associated with the
pin because it is not a GPIO.
[16] PWR_EN goes high during reset, between the assertion of the reset pin and the de-assertion of internal reset within the
PXA270 processor, after SYS_EN is driven high.
[17] GPIOs 114 and115: The alternate function configuration of these pins is ignored when either PUCR[USIM114] or
PUCR[USIM115] bits are set. Setting these bits forces the USIM enable signal onto these GPIOs.
[18] When software sets the OSCC[PIO_EN] or OSCC[TOUT_EN] bits, then any GPIO alternate function setting applied to
GPIO<9> or GPIO <10> is overridden with the CLK_PIO function on GPIO<9> and CLK_TOUT on GPIO<10>.
[19] Refer to Ta b l e 4 - 4 .
4-28 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
4.4 Memory Controller Reset and Initialization
On reset, the SDRAM interface is disabled. Reset values for the boot ROM are determined by
BOOT_SEL (see the Intel® PXA27x Processor Family Developers Manual, Memory Controller
chapter). Boot ROM is immediately available for reading upon exit from reset, and all memory
interface control registers are available for writing.
On hardware reset, the memory pins and controller are in the state shown in Table 4-4.
Table 4-3. Signal Types
Type Description
IC CMOS input
OC CMOS output
OCZ CMOS output, three-stateable
ICOCZ CMOS bidirectional, three-stateable
IA Analog input
OA Analog output
IAOA Analog bidirectional
IAOAZ Analog bidirectional - three-stateable
PS Power supply
Table 4-4. Memory Controller Pin Reset Values (Sheet 1 of 2)
Pin Name Reset, Sleep, Standby, Deep-Sleep, Frequency
Change, and Manual Self-Refresh Mode Values
SDCLK <31:0> 0b000
SDCKE 0
DQM <3:0> 0b0000
nSDCS <3:2> GPIO (memory controller drives 0b11)†
nSDCS <1:0> 0b11
nWE 1
nSDRAS 1
nSDCAS 1
nOE 1
MA <25:0> 0x0000_00001
RDnWR 0
MD <31:0> 0x0000_00002
nCS <0> 1
nCS <5:1> GPIO (memory controller drives 0b11111)
nPIOIR GPIO (memory controller drives high)
nPIOIW GPIO (memory controller drives high)
Electrical, Mechanical, and Thermal Specification 4-29
Intel® PXA270 Processor
Pin Listing and Signal Definitions
The address signals are driven low and data signals are pulled low during sleep, standby, deep-
sleep, frequency-change modes, and manual self-refresh. All other memory control signals are in
the same state that they are in after a hardware reset. If the SDRAMs are in self-refresh mode, they
are kept there by driving SDCKE low.
4.5 Power-Supply Pins
Table 4-5 summarize the power-supply ball count.
§§
nPOE GPIO (memory controller drives high)
nPWE GPIO (memory controller drives high)
NOTE:
†This indicates that the GPIO pin, if configured for the alternate function
used by the memory controller during reset, drives the represented
value.
NOTE: SCLK<3> is only available on PXA270 processor family packages
1. MA pins are driven
2. MD pins are pulled low
Table 4-4. Memory Controller Pin Reset Values (Sheet 2 of 2)
Pin Name Reset, Sleep, Standby, Deep-Sleep, Frequency
Change, and Manual Self-Refresh Mode Values
Table 4-5. Discrete (13x1 3 VF- B G A) Power Supply Pin Summary
Name Number of Pac kage Balls
13x13 mm VF-BGA Number of Pachage Balls
23x23 mm PBGA
VCC_BATT 11
VCC_IO 33
VCC_USB 44
VCC_LCD 22
VCC_MEM 19 16
VCC_BB 11
VCC_PLL 11
VCC_SRAM 44
VCC_CORE 14 20
VCC_USIM 11
VSS 65
VSS_IO 99
VSS_MEM 17 17
VSS_BB 11
VSS_PLL 11
VSS_CORE 56 56
4-30 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Pin Listing and Signal Definitions
Electrical, Mechanical, and Thermal Specification 5-1
Electrical Specifications 5
5.1 Absolute Maximum Ratings
The absolute maximum ratings (shown in Table 5-1) define limitations for electrical and thermal
stresses. These limits prevent permanent damage to the Intel® PXA270 processor.
Note: Absolute maximum ratings are not operating ranges.
5.2 Operating Conditions
This section shows operating voltage, frequency, and temperature specifications for the PXA270
processor.
Table 5-1. Absolute Maximum Ratings
Symbol Description Min Max Units
TSStorage temperature –40 125 °C
VCC_OL1
Offset voltage between any of the following pins:
VCC_CORE –0.3 0.3 V
VCC_OL2
Offset voltage between any of the following pins:
VCC_SRAM –0.3 0.3 V
VCC_OH1
Offset voltage between any of the following pins:
VCC_MEM –0.3 0.3 V
VCC_OH2
Offset voltage between any of the following pins:
VCC_IO –0.3 0.3 V
VCC_OH3 Offset voltage between VCC_LCD<0> and VCC_LCD<1> –0.3 0.3 V
VCC_HV
Voltage applied to high-voltage supply pins
(VCC_BB, VCC_USB, VCC_USIM, VCC_MEM,
VCC_IO<, VCC_LCD)
VSS–0.3 VSS+4.0 V
VCC_LV
Voltage applied to low-voltage supply pins
(VCC_CORE, VCC_PLL, VCC_SRAM) VSS–0.3 VSS+1.45 V
VIP
Voltage applied to non-supply pins except PXTAL_IN,
PXTAL_OUT, TXTAL_IN, and TXTAL_OUT pins VSS–0.3 VSS+4.0 V
VIP_X
Voltage applied to XTAL pins
(PXTAL_IN, PXTAL_OUT, TXTAL_IN, TXTAL_OUT) VSS–0.3 VSS+1.45 V
VESD
Maximum ESD stress voltage, three stresses maximum:
• Any pin to any supply pin, either polarity, or
• Any pin to all non-supply pins together, either polarity
—2000 V
IEOS
Maximum DC input current (electrical overstress) for any
non-supply pin — 5 mA
5-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
Table 5-2 shows each power domains supported voltages (except for VCC_MEM and
VCC_CORE). Table 5-3 shows all of the supported memory voltages and frequency operating
ranges (VCC_MEM). Table Note: shows all of the supported core voltage and frequency ranges
(VCC_CORE).
The operating temperature specification is a function of voltage and frequency.
Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2)
Symbol Description Min Typical Max Units
Operating Temperature
Tc a s e
Package operating temperature†
(Standard Temp) -25 —+85
°C
Package operating temperature†
(Extended Temp - PBGA ONLY) -40 —+85
Theta Jc
Junction-to-case temperature gradient
(VF-BGA) —2 —
°C /
watt
Junction-to-case temperature gradient
(PBGA) —1.4 —
VCC_BATT Voltage
VVCC0 Voltage applied on VCC_BATT @3.0V 2.25 3.00 3.75 V
VVDF1
Voltage difference between VCC_BATT
and VCC_IO during power-on reset or
deep-sleep wake-up (from the assertion
of SYS_EN to the de-assertion of
nRESET_OUT)
0 — 0.30 V
VVDF2 Voltage difference between VCC_BATT
and VCC_IO when VCC_IO is enabled 0 — 0.20 V
Tbramp Ramp Rate —10 12 mV/uS
VCC_PLL Voltage
VVCC1 Voltage applied on VCC_PLL @1.3V
(+10 / -10%) 1.17 1.30 1.43 V
Tpwrramp Ramp Rate —10 12 mV/uS
VCC_BB Voltages
VVCC2a Voltage applied on VCC_BB @1.8V
(+20 / -5%) 1.71 1.80 2.16 V
VVCC2b Voltage applied on VCC_BB @2.5V
(+10 / -10%) 2.25 2.50 2.75 V
VVCC2c Voltage applied on VCC_BB @3.0V
(+10 / -10%) 2.70 3.0 3.30 V
VVCC2d Voltage applied on VCC_BB @3.3V
(+10 / -10%) 2.97 3.3 3.63 V
Tsysramp Ramp Rate —10 12 mV/uS
VCC_LCD Voltages
VVCC3a Voltage applied on VCC_LCD @1.8V
(+20 / -5%) 1.71 1.80 2.16 V
Electrical, Mechanical, and Thermal Specification 5-3
Intel® PXA270 Processor
Electrical Specifications
Table 5-3 shows the supported memory frequency and memory supply voltage operating ranges for
the PXA270 processor.
VVCC3b Voltage applied on VCC_LCD @2.5V
(+10 / -10%) 2.25 2.50 2.75 V
VVCC3c Voltage applied on VCC_LCD @3.0V
(+10 / -10%) 2.70 3.0 3.30 V
VVCC3d Voltage applied on VCC_LCD @3.3V
(+10 / -10%) 2.97 3.3 3.63 V
Tsysramp Ramp Rate —10 12 mV/uS
VCC_IO Voltages
VVCC4a Voltage applied on VCC_IO @3.0V
(+10 / -10.3%) 2.69175 3.0 3.30 V
VVCC4b Voltage applied on VCC_IO @3.3V
(+10 / -10%) 2.97 3.3 3.63 V
Tsysramp Ramp Rate —10 12 mV/uS
NOTE: VCC_IO must be maintained at a voltage as high as or higher than, all other supplies except for
VCC_BATT and VCC_USB
VCC_USIM Voltages
VVCC5a Voltage applied on VCC_USIM @1.8V
(+20 / -5%) 1.71 1.80 2.16 V
VVCC5b Voltage applied on VCC_USIM @3.0V
(+10 / -10%) 2.70 3.0 3.30 V
Tsysramp Ramp Rate —10 12 mV/uS
NOTE: If the system does NOT use the USIM module, VCC_USIM can be tied to VCC_IO (at any supported
VCC_IO voltage level). This allows the GPIO’s on VCC_USIM to be used at the same voltage level as
VCC_IO GPIO’s. NOTE: Software must NOT configure USIM signals to be used if this is done.
VCC_SRAM Voltage
VVCC6 Voltage applied on VCC_SRAM @1.1V
(+10 / -10%) 0.99 1.10 1.21 V
Tpwrramp Ramp Rate —10 12 mV/uS
VCC_USB Voltage
VVCC7a Voltage applied on VCC_USB @3.0V
(+10 / -10%) 2.70 3.00 3.30 V
VVCC7b Voltage applied on VCC_USB @3.3V
(+10 / -10%) 2.97 3.30 3.63 V
Tsysramp Ramp Rate —10 12 mV/uS
†System design must ensure that the device case temperature is maintained within the specified limits. In
some system applications it may be necessary to use external thermal management (for example, a
package-mounted heat spreader) or configure the device to limit power consumption and maintain
acceptable case temperatures.
Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2)
Symbol Description Min Typical Max Units
5-4 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
Table 5-3. Memory Voltage and Frequency Electrical Specifications
Table 5-4 shows the supported core frequency and core supply voltage operating ranges for the
PXA270 processor. Each frequency range is specified in the following format:
(core frequency/internal system bus frequency/memory controller frequency/SDRAM frequency)
Note: Refer to the “Clocks and Power” section of the Intel® PXA27x Processor Family Developers
Manual for supported frequencies, clock register settings as listed in Table 5-4.
Symbol Description Min Typical Max Units
Memory Voltage and Frequency Range 1
VMEM1 Voltage applied on VCC_MEM 1.71 1.80 2.16 V
fSM1A External synchronous memory frequency,
SDCLK1, SDCLK2 13 —104 MHz
fSM1B External synchronous memory frequency,
SDCLK0 13 —104 MHz
Tsysramp Ramp Rate —10 12 mV/uS
Memory Voltage and Frequency Range 2
VMEM2 Voltage applied on VCC_MEM 2.25 2.50 2.75 V
fSM2A External synchronous memory frequency,
SDCLK1, SDCLK2 13 —104 MHz
fSM2B External synchronous memory frequency,
SDCLK0 13 —104 MHz
Tsysramp Ramp Rate —10 12 mV/uS
Memory Voltage and Frequency Range 3
VMEM3 Voltage applied on VCC_MEM 2.70 3.0 3.3 V
fSM3A External synchronous memory frequency,
SDCLK1, SDCLK2 13 —104 MHz
fSM3B External synchronous memory frequency,
SDCLK0 13 —104 MHz
Tsysramp Ramp Rate —10 12 mV/uS
Memory Voltage and Frequency Range 4
VMEM4 Voltage applied on VCC_MEM 2.97 3.30 3.63 V
fSM4A External synchronous memory frequency,
SDCLK1, SDCLK2 13 —104 MHz
fSM4B External synchronous memory frequency,
SDCLK0 13 —104 MHz
Tsysramp Ramp Rate —10 12 mV/uS
Table 5-4. Core Voltage and Frequency Electrical Specifications (Sheet 1 of 2)
Symbol Description Min Typical Max Units
Core Voltage and Frequency Range 1 (13/13/13/13)
VVCCC1 Voltage applied on VCC_CORE 0.8075 0.85 1.705 V
fCORE1 Core operating frequency 13 —13 MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Electrical, Mechanical, and Thermal Specification 5-5
Intel® PXA270 Processor
Electrical Specifications
Core Voltage and Frequency Range 2 (91/45.5/91/45.5) and (104/104/104/104)
VVCCC2 Voltage applied on VCC_CORE 0.855 0.9 1.705 V
fCORE2 Core operating frequency 91 —104 MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 3 (156/104/104/104)
VVCCC3 Voltage applied on VCC_CORE 0.95 1.00 1.705 V
fCORE3 Core operating frequency —156 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 4 (208/208/208/104)
VVCCC4 Voltage applied on VCC_CORE 1.0925 1.15 1.705 V
fCORE4 Core operating frequency —208 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 4a (208/104/104/104)
VVCCC4a Voltage applied on VCC_CORE 0.9975 1.05 1.705 V
fCORE4a Core operating frequency —208 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 5 (312/208/208/104)
VVCCC5 Voltage applied on VCC_CORE 1.1875 1.25 1.705 V
fCORE5 Core operating frequency —312 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 5a (312/104/104/104)
VVCCC5a Voltage applied on VCC_CORE 0.99 1.1 1.705 V
fCORE5a Core operating frequency —312 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 6 (416/208/208/104)
VVCCC6 Voltage applied on VCC_CORE 1.2825 1.35 1.705 V
fCORE6 Core operating frequency —416 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 7 (520/208/208/104)
VVCCC7 Voltage applied on VCC_CORE 1.3775 1.45 1.705 V
fCORE7 Core operating frequency —520 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
Core Voltage and Frequency Range 8 (624/208/208/104)†
VVCCC8 Voltage applied on VCC_CORE 1.4725 1.55 1.705 V
fCORE8 Core operating frequency —624 —MHz
Tpwrramp Ramp Rate —10 12 mV/uS
†Core operating frequency not offered in PBGA package.
Table 5-4. Core Voltage and Frequency Electrical Specifications (Sheet 2 of 2)
5-6 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
5.2.1 Internal Power Domains
The external power supplies are used to generate several internal power domains, which are shown
in Table 5-5. Refer to the Power Manager / Internal Power Domain Block Diagram in the “Clocks
and Power” section of the Intel® PXA27x Processor Family Developers Manual for more
information on internal power domains.
Table 5-5. Internally Generated Power Domain Descriptions
Table 5-6 shows the recommended core voltage specification for each of the lower power modes.
Table 5-6. Core Voltage Specifications For Lower Power Modes
5.3 Power-Consumption Specifications
Power consumption depends on the operating voltage and frequency, peripherals enabled, external
switching activity, and external loading and other factors.
Table 5-7 contains the power consumption information. There are three sets of data: Active Power
Consumption, Idle Power Consumption and Low Power Modes Power Consumption. Data was
taken at room temperature. For Active Power Consumption data, no peripherals are enabled except
for UART.
Name Units Generation Tolerance
VCC_REG IO associated with deep-sleep-
active units Switched between VCC_BATT and VCC_IO -
VCC_OSC Oscillator power supplies Generated from VCC_REG +/- 30%
VCC_RTC RTC and power manager
supply
Switched between VCC_OSC and
VCC_CORE -
VCC_PI Power manager I2C supply Switched between VCC_OSC and
VCC_CORE -
VCC_CPU CPU core Independent power-down from VCC_CORE -
VCC_PER Peripheral units Independent power-down from VCC_CORE -
VCC_Rx Particular internal SRAM unit Switched between VCC_OSC and
VCC_SRAM -
Mode Description Min Typical Max Units
Standby Voltage applied on VCC_CORE 1.045 1.1 1.21 V
Deep-Idle Voltage applied on VCC_CORE 0.8075 0.85 0.935 V
Electrical, Mechanical, and Thermal Specification 5-7
Intel® PXA270 Processor
Electrical Specifications
Table 5-7. Power-Consumption Specifications (Sheet 1 of 2)
Parameter Description Typical Units Conditions
Active Power Consumption
624 MHz Active Power (208 MHz System bus) 925 mW
VCC_CORE = 1.55V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
520 MHz Active Power (208 MHz System bus) 747 mW
VCC_CORE = 1.45V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
416 MHz Active Power (208 MHz System bus) 570 mW
VCC_CORE = 1.35V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
312 MHz Active Power (208 MHz System bus) 390 mW
VCC_CORE = 1.25V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
312 MHz Active Power (104 MHz System bus) 375 mW
VCC_CORE = 1.1V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
208 MHz Active Power (208 MHz System bus) 279 mW
VCC_CORE = 1.15V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
104 MHz Active Power (104 MHz System bus) 116 mW
VCC_CORE = 0.9V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
13 MHz Active Power (CCCR[CPDIS=1) 44.2 mW
VCC_CORE = 0.85V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
Idle Power Consumption
624 MHz Idle Power (208 MHz System bus) 260 mW
VCC_CORE = 1.55V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
520 MHz Idle Power (208 MHz System bus) 222 mW
VCC_CORE = 1.45V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
416 MHz Idle Power (208 MHz System bus) 186 mW
VCC_CORE = 1.35V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
312 MHz Idle Power (208 MHz System bus) 154 mW
VCC_CORE = 1.25V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
312 MHz Idle Power (104 MHz System bus) 109 mW
VCC_CORE = 1.1V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
208 MHz Idle Power (208 MHz System bus) 129 mW
VCC_CORE = 1.15V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
104 MHz Idle Power (104 MHz System bus) 64 mW
VCC_CORE = 0.9V VCC_SRAM = 1.1V
VCC_PLL = 1.3V VCC_MEM, VCC_BB,
VCC_USIM, VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
5-8 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
5.4 DC Specification
The DC characteristics for each pin include input sense levels, output drive levels, and currents.
These parameters can be used to determine maximum DC loading and to determine maximum
transition times for a given load. Table 5-8 shows the DC operating conditions for the high- and
low-strength input, output, and I/O pins.
Note: VCC_IO must be maintained at a voltage as high as or higher than all other supplies except
VCC_BATT and VCC_USB and VCC_USB.
Low Power modes Power Consumption
13 MHz Idle Mode1 Power (LCD on) 15.4 mW
VCC_CORE, VCC_SRAM, VCC_PLL = 0.85V
VCC_MEM, VCC_BB, VCC_USIM,
VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
13 MHz Idle Mode1 Power (LCD off) 8.5 mW
VCC_CORE, VCC_SRAM, VCC_PLL = 0.85V
VCC_MEM, VCC_BB, VCC_USIM,
VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
Deep-Sleep mode 0.1014 mW
VCC_CORE, VCC_SRAM, VCC_PLL = 0V
VCC_MEM, VCC_BB, VCC_USIM,
VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
Sleep mode 0.1630 mW
VCC_CORE, VCC_SRAM, VCC_PLL = 0V
VCC_MEM, VCC_BB, VCC_USIM,
VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
Standby mode 1.7224 mW
VCC_CORE, VCC_SRAM, VCC_PLL = 1.1V
VCC_MEM, VCC_BB, VCC_USIM,
VCC_LCD = 1.8V
VCC_IO, VCC_BATT, VCC_USB= 3.0V
NOTE: 1) 13 MHz Idle Mode (CCCR[CPDIS] =1 (CCCR[PPDIS] = 1)
Table 5-7. Power-Consumption Specifications (Sheet 2 of 2)
Parameter Description Typical Units Conditions
Table 5-8. Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet 1 of 2)
Symbol Description Min Max Unit
s
Testing Conditions
/ Notes
Input DC Operating Conditions (VCC = 1.8V, 2.5, 3.0, 3.3 Typical)
VIH1
Input high voltage, all standard input and I/O
pins, relative to applicable VCC (VCC_IO,
VCC_MEM, VCC_BB, VCC_LCD, VCC_USB,
or VCC_USIM)
0.8 * VCC VCC + 0.1 V —
VIL1
Input low voltage, all standard input and I/O
pins, relative to applicable VSS (VSS_IO,
VSS_MEM, or VSS_BB) and VCC (VCC_IO,
VCC_MEM, VCC_BB, VCC_LCD, VCC_USB,
or VCC_USIM)
VSS - 0.1 0.2 * VCC V —
OS DC Overshoot voltage / duration —+1 VMax duration of 4nS
US DC Undershoot voltage / duration —-1 VMax duration of 4nS
Output DC Operating Conditions (VCC = 1.8, 2.5, 3.0, 3.3 Typical)
Electrical, Mechanical, and Thermal Specification 5-9
Intel® PXA270 Processor
Electrical Specifications
5.5 Oscillator Electrical Specifications
The PXA270 processor contains two oscillators: a 32.768-kHz oscillator and a 13.000-MHz
oscillator. Each oscillator requires a specific crystal.
5.5.1 32.768-kHz Oscillator Specifications
The 32.768-kHz oscillator is connected between the TXTAL_IN (amplifier input) and
TXTAL_OUT (amplified output). Table 5-9 and Table 5-10 list the appropriate 32.768-kHz
specifications.
To drive the 32.768-kHz crystal pins from an external source:
1. Drive the TXTAL_IN pin with a digital signal that has low and high levels as listed in
Table 5-10. Do not exceed VCC_PLL or go below VSS_PLL by more than 100 mV. The
minimum slew rate is 1 volt per 1 µs. The maximum current drawn from the external clock
source when the clock is at its maximum positive voltage is typically 1 mA.
2. Float the TXTAL_OUT pin or drive it in complement to the TXTAL_IN pin, with the same
voltage level and slew rate.
Caution: The TXTAL_IN and TXTAL_OUT pins must not be driven from an external source if the PXA270
processor sleep / deep sleep DC-DC converter is enabled.
VOH1
Output high voltage, all standard output and I/
O pins, relative to applicable VCC (VCC_IO,
VCC_MEM, VCC_BB, VCC_LCD, VCC_USB,
or VCC_USIM)
VCC - 0.3 VCC VIOH = -4 mA2,
-3 mA3
VOL1Output low voltage, all standard output and I/O
pins, relative to applicable VSS (VSS_IO,
VSS_MEM, or VSS_BB)
VSS VSS + 0.3 VIOH = 4 mA2,
3 mA3
NOTES:
1. Programmable drive strengths set to 0x5 for memory and LCD programmable signals.
2. The current for the high-strength pins are MA<25:0>, MD<31:0>, nOE, nWE, nSDRAS, nSDCAS, DQM<3:0>, nSDCS<3:0>,
SDCKE<1>, SDCLK<3:0>, RDnWR, nCS<5:0>, and nPWE.
3. The current for all other output and I/O pins are low strength.
Table 5-8. Standard Input, Output, and I/O Pin DC Operating Conditions (Sheet 2 of 2)
Symbol Description Min Max Unit
s
Testing Conditions
/ Notes
Table 5-9. Typical 32.768-kHz Crystal Requirements (Sheet 1 of 2)
Parameter Minimum Typical Maximum Units
Frequency range — 32.768 — kHz
Frequency tolerance –30 — +30 ppm
Frequency stability, parabolic coefficient — — –0.04 ppm/
(∆°C)2
Drive level — — 1.0 uW
Load capacitance (CL) — 12.5 — pf
Shunt capacitance (CO)—0.9—pf
5-10 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
Motional capacitance (CI)—2.1—fF
Equivalent series resistance (RS)—1835k Ω
Insulation resistance at 100 VDC 100 — — M Ω
Aging, at operating temperature per year — — ±3.0 ppm
Table 5-9. Typical 32.768-kHz Crystal Requirements (Sheet 2 of 2)
Parameter Minimum Typical Maximum Units
Electrical, Mechanical, and Thermal Specification 5-11
Intel® PXA270 Processor
Electrical Specifications
5.5.2 13.000-MHz Oscillator Specifications
The 13.000-MHz oscillator is connected between the PXTAL_IN (amplifier input) and
PXTAL_OUT (amplified output). Table 5-11 and Table 5-12 list the 13.000-MHz specifications.
To drive the 13.000-MHz crystal pins from an external source:
1. Drive the PXTAL_IN pin with a digital signal with low and high levels as listed in Table 5-12.
Do not exceed VCC_PLL or go below VSS_PLL by more than 100 mV. The minimum slew
rate is 1 volt / 100 ns. The maximum current drawn from the external clock source when the
clock is at its maximum positive voltage typically is 1 mA.
2. Float the PXTAL_OUT pin or drive it in complement to the PXTAL_IN pin, with the same
voltage level, slew rate, and input current restrictions.
Caution: The PXTAL_IN and PXTAL_OUT pins must not be driven from an external source if the PXA270
processor sleep / deep sleep DC-DC converter is enabled.
Table 5-10. Typical External 32.768-kHz Oscillator Requirements
Symbol Description Min Typical Max Units
Amplifier Specifications
VIH_X Input high voltage, TXTAL_IN 0.99 1.10 1.21 V
VIL_X Input low voltage, TXTAL_IN –0.10 0.00 0.10 V
IIN_XT Input leakage, TXTAL_IN — — 1 µA
CIN_XT Input capacitance, TXTAL_IN/
TXTAL_OUT —18 25 pf
tS_XT Stabilization time — — 10 s
Board Specifications
RP_XT Parasitic resistance, TXTAL_IN/
TXTAL_OUT to any node 20 — — MΩ
CP_XT Parasitic capacitance, TXTAL_IN/
TXTAL_OUT, total — — 5 pf
COP_XT Parasitic shunt capacitance,
TXTAL_IN to TXTAL_OUT — — 0.4 pf
Table 5-11. Typical 13.000-MHz Crystal Requirements
Parameter Minimum Typical Maximum Units
Frequency range 12.997 13.000 13.002 MHz
Frequency tolerance at 25°C –50 — +50 ppm
Oscillation mode — Fnd — —
Maximum change over temperature range –50 — +50 ppm
Drive level — 10 100 uW
Load capacitance (CL)—10—pf
Maximum series resistance (RS)—50—Ω
Aging per year, at operating temperature — — ±5.0 ppm
5-12 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
5.6 CLK_PIO and CLK_TOUT Specifications
CLK_PIO can be used to drive a buffered version of the PXTAL_IN oscillator input or can be used
as a clock input alternative to PXTAL_IN. Refer to Table 5-13 for CLK_PIO specifications.
A buffered and inverted version of the TXTAL_IN oscillator output is driven out on CLK_TOUT.
Refer to Table 5-14 for CLK_TOUT specifications.
Note: CLK_TOUT and CLK_PIO are only available when software sets the OSCC[PIO_EN] and
OSCC[TOUT_EN] bits.
Table 5-12. Typical External 13.000-MHz Oscillator Requirements
Symbol Description Min Typical Max Units
Amplifier Specifications
VIH_X Input high voltage, PXTAL_IN 0.99 1.10 1.21 V
VIL_X Input low voltage, PXTAL_IN –0.10 0.00 0.10 V
IIN_XP Input leakage, PXTAL_IN — — 10 µA
CIN_XP Input capacitance, PXTAL_IN/PXTAL_OUT —40 50 pf
tS_XP Stabilization time — — 67.8 ms
Board Specifications
RP_XP Parasitic resistance, PXTAL_IN/PXTAL_OUT to
any node 20 — — MΩ
CP_XP Parasitic capacitance, PXTAL_IN/PXTAL_OUT,
total — — 5 pf
COP_XP Parasitic shunt capacitance, PXTAL_IN to
PXTAL_OUT — — 0.4 pf
Table 5-13. CLK_PIO Specifications
Parameter Specifications
Frequency 13 MHz
Frequency Accuracy (derived from 13 MHz crystal) +/-200ppm
Symmetry/Duty Cycle variation 30/70 to 70/30% at VCC
Jitter +/-20pS max
Load capacitance (CL)50pf max
Rise and Fall time (Tr & Tf) 15nS max with 50pF load
Table 5-14. CLK_TOUT Specifications
Parameter Specifications
Frequency 32KHz
Frequency Accuracy (derived from 32 kHz crystal) +/-200ppm
Symmetry/Duty Cycle variation 30/70 to 70/30% at VCC
Electrical, Mechanical, and Thermal Specification 5-13
Intel® PXA270 Processor
Electrical Specifications
5.7 48 MHz Output Specifications
Software may configure GPIO<11> or GPIO<12> alternate functions to enable the 48-MHz clock
output. The 48-MHz output clock is a divided-down output generated from the 312-MHz
peripheral PLL. Refer to Table 5-15 for the 48-MHz output specifications. Refer to Section 3 of
this document for GPIO alternate functions in the pin usage table.
Jitter +/-20pS max
Load capacitance (CL) 50pf max
Rise and Fall time (Tr & Tf) 15nS max with 50pF load
Table 5-14. CLK_TOUT Specifications
Parameter Specifications
Table 5-15. 48 MHz Output Specifications
Parameter Specifications
Frequency (derived from 13 MHz crystal) 48 MHz
Frequency Accuracy (derived from 13 MHz crystal) +/-200ppm (maximum)
Symmetry/Duty Cycle variation 30/70 to 70/30% at VCC
Jitter +/-20pS max
Load capacitance (CL) 50pf max
Rise and Fall time (Tr & Tf) 15nS max with 50pF load
5-14 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Electrical Specifications
Electrical, Mechanical, and Thermal Specification 6-1
AC Timing Specifications 6
A pin’s alternating-current (AC) characteristics include input and output capacitance. These factors
determine the loading for external drivers and other load analyses. The AC characteristics also
include a derating factor, which indicates how much the AC timings might vary with different
loads.
Note: The timing diagrams in this chapter show bursts that start at 0 and proceed to 3 or 7. However, the
least significant address (0) is not always received first during a burst transfer, because the Intel®
PXA270 processor requests the critical word first during burst accesses.
Table 6-1 shows the AC operating conditions for the high- and low-strength input, output, and I/O
pins. All AC specification values are valid for the device’s entire temperature range.
6.1 AC Test Load Specifications
Figure 6-1 represents the timing reference load used in defining the relevant timing parameters of
the part. It is not intended to be either a precise representation of the typical system environment
nor a depiction of the actual load presented by a production tester. System designers use IBIS or
other simulation tools to correlate the timing reference load to system environment. Manufacturers
correlate to their production test conditions (generally a coaxial transmission line terminated at the
tester electronics).
Table 6-1. Standard Input, Output, and I/O-Pin AC Operating Conditions
Symbol Description Min Typical Max Units
CIN
Input capacitance, all standard input and
I/O pins — — 10 pf
COUT_H
Output capacitance, all standard high-
strength output and I/O pins 20 —50 pf
tdF_H
Output derating, falling edge on all
standard, high-strength output and I/O
pins, from 50-pf load.
—TBD —ns/pf
tdR_H
Output derating, rising edge on all
standard, high-strength output and I/O
pins, from 50-pf load.
—TBD —ns/pf
COUT_L
Output capacitance, all standard low-
strength output and I/O pins 20 —50 pf
tdF_L
Output derating, falling edge on all
standard, low-strength output and I/O
pins, from 50-pf load.
—TBD —ns/pf
tdR_L
Output derating, rising edge on all
standard, low-strength output and I/O
pins, from 50-pf load.
—TBD —ns/pf
6-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.2 Reset and Power Manager Timing Specifications
The processor asserts the nRESET_OUT pin in one of several different modes:
•Power-on reset
•Hardware reset
•Watchdog reset
•GPIO reset
•Sleep mode
•Deep-sleep mode
The following sections give the timing and specifications for entry into and exit from these modes.
6.2.1 Power-On Timing Specifications
Power-on reset begins when a power supply is detected on the backup battery pin, VCC_BATT,
after the processor has been powered off. A power-on reset is equivalent to a hardware reset, in that
all units are reset to the same known state as with a hardware reset. A power-on reset is a complete
and total reset that occurs only at initial power on.
The external power-supply system must enable the power supplies for the processor in a specific
sequence to ensure proper operation. Figure 6-2 shows the timing diagram for a power-on reset
sequence. Table 6-2 details the timing.
The sequence for power-on reset is as follows:
1. VCC_BATT is established, then nRESET should be de-asserted to initiate power-on reset.
2. PWR_OUT is asserted. The processor asserts nRESET_OUT.
3. The external power-control subsystem de-asserts nBATT_FAULT to signal that the main
battery is connected and not discharged.
4. The processor asserts the SYS_EN signal to enable the power supplies VCC_IO, VCC_MEM,
VCC_BB, VCC_USB, and VCC_LCD. VCC_USIM can be established at this time also but
can be independently controlled through its own control signals. VCC_IO must be established
first. The other supplies can turn on in any order, but they must all be established within
125 milliseconds of the assertion of SYS_EN.
Figure 6-1. AC Test Load
I/O
50p
f
ΖΟ = 50Ω
Electrical, Mechanical, and Thermal Specification 6-3
Intel® PXA270 Processor
AC Timing Specifications
5. The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE,
VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be
established within 125 milliseconds of the assertion of PWR_EN.
6. The external power-control subsystem de-asserts nVDD_FAULT to signal that all system
power supplies have been properly established.
7. The processor de-asserts nRESET_OUT and enters run mode, executing code from the reset
vector.
Note: nBATT_FAULT must be high before nRESET is de-asserted. Otherwise, the processor will not
begin the power-on sequencing event. nVDD_FAULT is sampled only when the SYS_DEL and
PWR_DEL timers have expired. Refer to the Intel® PXA27x Processor Family Developer’s
Manual, “Initial Power On” and “Deep-Sleep Exit States” for a state diagram.
Figure 6-2. Power On Reset Timing
Table 6-2. Power-On Timing Specifications (Sheet 1 of 2)(OSCC[CRI] = 0)
Symbol Description Min Typical Max Units
t1
Delay from VCC_BATT assertion to
nRESET de-assertion 10 — — ms
t2
Delay from nRESET de-assertion to
SYS_EN assertion —101—ms
t3
Delay from SYS_EN assertion to
PWR_EN assertion —125 —ms
t4
Power supply stabilization time (time to
the deassertion of nVDD_FAULT after the
assertion of PWR_EN)
— — 120 ms
t5
Delay from the assertion of PWR_EN to
the de-assertion of nRESET_OUT —125 —ms
tbramp VCC_BATT power-on Ramp Rate —10 12 mV/uS
VCC_USB, VCC_IO, VCC_MEM,
VCC_BB, VCC_LCD, VCC_USI M
VCC_CORE, VCC_SRAM,
VCC_PLL
nBATT_FAULT
nRESET
SYS_EN
PWR_EN
nVDD_FAULT
VCC_BATT
nRESET_OUT
t1t3t5
t2
t4
tsysramp
tbramp
tpwrramp
6-4 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.2.2 Hardware Reset Timing
The timing sequences shown in Figure 6-3 for hardware reset and the specifications in Table 6-3
and Table 6-4 assume stable power supplies at the assertion of nRESET. Follow the timings
indicated in Section 6.2.1 if the power supplies are unstable.
tsysramp
Power-on Ramp Rate for all external high
-voltage power domains —10 12 mV/uS
tpwrramp
Power-on Ramp Rate for all external low
-voltage power domains (including
dynamic voltage changes on
VCC_CORE)
—10 12 mV/uS
NOTES:
1. If the OSCC[CRI] =1 then the delay from nRESET de-assertion to SYS_EN assertion is 3000mS
NOTE: This long delay is attributed to the fact that when the CRI bit is read as 1, (which indicates that the
CLK_REQ pin was floated during a hardware or power-on reset) the processor oscillator is supplied
externally. This then forces the system to wait for the 32 kHz oscillator and the 13 MHz oscillator to
stabilize.
Table 6-2. Power-On Timing Specifications (Sheet 2 of 2)(OSCC[CRI] = 0)
Symbol Description Min Typical Max Units
Figure 6-3. Hardware Reset Timing
Table 6-3. Hardware Reset Timing Specifications (OSCC[CRI] = 0)
Symbol Description Min Typical Max Units
t6
Delay between nRESET asserted and
nRESET_OUT asserted —< 100 ns 10 ms
t7Assertion time of nRESET 6 — — ms
t8
Delay between nRESET de-asserted and
nRESET_OUT de-asserted 256 —265 ms
nRESET
nRESET_OUT
t7
NOTE: nBATT_FAULT and nVDD_FAULT must be deasserted during the reset sequence.
t6 t8
Electrical, Mechanical, and Thermal Specification 6-5
Intel® PXA270 Processor
AC Timing Specifications
6.2.3 Watchdog Reset Timing
Watchdog reset is generated internally and therefore has no external pin dependencies. The
nRESET_OUT pin is the only indicator of watchdog reset; it stays asserted for tDHW_OUT. The
timing is similar to that for GPIO reset — see Figure 6-4 for details.
6.2.4 GPIO Reset Timing
GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies
based on the selected clock frequency. If the clocks and power manager is in a frequency-change
sequence when GPIO reset is asserted (see Section 5.5.1, “32.768-kHz Oscillator Specifications”
on page 5-9.), then Figure 6-4 shows the timing of GPIO reset, and Table 6-5 shows the GPIO reset
timing specifications.
Note: When bit GPROD is set in the Power Manager General Configuration register, nRESET_OUT is
not asserted during GPIO reset. For register details, see the “Clocks and Power Manager” chapter
in the Intel® PXA27x Processor Family Developer’s Manual.
Table 6-4. Hardware Reset Timing Specifications (OSCC[CRI] = 1)
Symbol Description Min Typical Max Units
t6
Delay between nRESET asserted and
nRESET_OUT asserted —< 100 ns 10 ms
t7Assertion time of nRESET 6 — — ms
t8
Delay between nRESET de-asserted and
nRESET_OUT de-asserted 2256 —3265 ms
Figure 6-4. GPIO Reset Timing
GP[1]
nRESET_OUT
nCS0
tA_GPIO<1>
tDHW_OUT_A
tDHW_OUT
tCS0
6-6 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.2.5 Sleep Mode Timing
Sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals.
Figure 6-5 and Table 6-6 show the required timing parameters for sleep mode.
Note: When bit SL_ROD is set in the Power Manager Sleep Configuration register, nRESET_OUT, is
not asserted during GPIO reset. See the “Clocks and Power Manager” chapter in the Intel®
PXA27x Processor Family Developer’s Manual for register details.
Table 6-5. GPIO Reset Timing Specifications
Symbol Description Min Typical Max Units
tA_GPIO<1> Minimum assert time of GPIO<1>1 in
13.000-MHz input clock cycles 44— — cycles
tDHW_OUT_A
Delay between GPIO<1> asserted and
nRESET_OUT asserted in 13.000-MHz
input clock cycles
64— 8 cycles
tDHW_OUT
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, run or
turbo mode2230 — — nsec
tDHW_OUT_F
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, during
frequency change sequence35 — 380 µs
tCS05Delay between nRESET_OUT de-
assertion and nCS0 assertion 1000 — — ns
NOTES:
1. GPIO<1> is not recognized as a reset source again until configured to do so in software. Software must
check the state of GPIO<1> before configuring as a reset to ensure that no spurious reset is generated. For
details, see the “Clocks and Power Manager” chapter in the Intel® PXA27x Processor Family Developer’s
Manual.
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 13.000-MHz input clock.
3. Time during the frequency-change sequence depends on the state of the PLL lock detector at the assertion
of GPIO reset. The lock detector has a maximum time of 350 µs plus synchronization.
4. In standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power
mode.
5. The tCS0 specification is also applicable to Power-On reset, Hardware reset, Watchdog reset and Deep-
Sleep/Sleep mode exit.
Electrical, Mechanical, and Thermal Specification 6-7
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-5. Sleep Mode Timing
6.2.6 Deep-Sleep Mode Timing
Deep-sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals.
Figure 6-6 and Table 6-7 show the required timing parameters for sleep mode. The timing
specifications listed are for software invoked (not battery or VDD fault) Deep-sleep entry, unless
specified.
Table 6-6. Sleep-Mode Timing Specifications
Symbol Description Min Typical Max3Units
tentry5Delay between MCR sleep command
issue to de-assertion of PWR_EN 0.56 —2.51msec
texit
Delay between wakeup event and run
mode 0.50 —136.652,4 msec
tpwrdelay
Delay between assertion of PWR_EN to
PLL enable20 — 125 msec
NOTES:
1. -1mS if not using DC2DC and -0.94mS if any internal SRAM banks are not powered
2. 0.15ms less time if exiting from sleep mode to 13M mode
3. Add 0.1ms if the wake up event is external
4. Oscillator start/crystal stable times are programmable (300uS-11mS)
NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which
counts until the oscillator is stable. (Typical stabilization is 500µs. Maximum can be upto 5ms)
5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode
SYS_EN
VCC_USB, VCC_IO,
VCC_BB,VCC_MEM,
VCC_LCD, VCC_USIM
PWR_EN
nVDD_FAULT
VCC_CORE, VCC_SRAM,
VCC_PLL
nRESET_OUT
(High)
(Enabled)
Wakeup Event
SLEEP (ENTRY) SLEEP SLEEP (EXIT) NORMAL
Intel® PXA27x State:
Tentry
Texit
Tpwrdelay
6-8 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-6. Deep-Sleep-Mode Timing
VCC_USB, VCC_IO,
VCC_BB, VCC_MEM,
VCC_LCD, VCC_USIM
VCC_CORE, VCC_SRAM,
VCC_PLL
NORMAL
SYS_EN
PWR_EN
nVDD_FAULT
nRESET_OUT
Wakeup Event
DEEP SLEEP (ENTRY) DEEP SLEEP DEEP SLEEP (EXIT)Intel® PXA27x State:
Tdentry
Tdexit
Tdpwr_delay
Deep-Sleep Command
Tdsys_delay
Tenable
Table 6-7. Deep-Sleep Mode Timing Specifications
Symbol Description Min Typical Max3Units
tdentry5Delay between deep-sleep command
issue to de-assertion of SYS_EN 0.66 —1.661msec
tenable
Delay between de-assertion of PWR_EN
and SYS_EN —30 —usec
tdexit
Delay between wakeup event and run
mode 0.60 —261.752,4 msec
tdsysdelay
Delay between assertion of SYS_EN to
PWR_EN20 — 125 msec
tdpwrdelay
Delay between assertion of PWR_EN to
PLL enable20 — 125 msec
NOTE: Timing specifications for nBATT_FAULT and/or nVDD_FAULT asserted deep-sleep mode entry are
below:
Fault assert
Delay between nBATT_FAULT or
nVDD_FAULT assertion (during all
modes of operation including sleep
mode) and deep-sleep mode entry6(The
de-assertion of SYS_EN defines when
the processor is in deep-sleep mode)
0.33 —1.56 msec
NOTES:
1. -1ms if not using DC2DC
2. 0.15ms less time if exiting from Deep-sleep mode to 13M mode
3. Add 0.1ms if the wake up event is external
4. Oscillator start/crystal stable times are programmable (300uS-11mS)
NOTE: 6ms is user programmable using the OSCC[OSD] bit. The remaining 5ms is an internal timer which
counts until the oscillator is stable. (Typical stabilization is 500µs. Maximum can be upto 5ms)
5. nRESET_OUT and nVDD_FAULT are programmable during sleep mode
6. Assumes PMCR[BIDAE or VIDAE] bits are set to zero (default state) - The PMCR[BIDAE or VIDAE] bits
are only read by the processor if nBATT_FAULT or nVDD_FAULT signals are asserted
Electrical, Mechanical, and Thermal Specification 6-9
Intel® PXA270 Processor
AC Timing Specifications
6.2.6.1 GPIO states in Deep-Sleep mode
If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD,
VCC_USB, VCC_USIM) remain powered on during deep-sleep, the PGSR values are driven onto
all the GPIO pins (that are configured as outputs) for a finite time period, then the pins default to
the reset state (Pu/Pd) as described in Chapter 2 of this manual. This sequence occurs for either
software initiated or fault initiated deep-sleep entry.
Note: GPIOs<0,1,3,4,9,10> never float. They are powered from VCC_BATT so when the system and the
core power domains are removed (controlled by SYS_EN and PWR_EN), the Pu/Pd resistors are
still enabled due to VCC_BATT remaining on.
The delay between the initiation of deep-sleep mode and enabling the GPIO Pu/Pd states, is system
dependant because the processor is performing an unpredictable workload and requires an
unknown amount of time to complete current processes. Refer to the deep-sleep mode, “Clocks and
Power” section of the Intel® PXA27x Processor Family Developers Manual for a description on
deep-sleep mode entry sequence.
Table 6-8 shows the time period that the GPIO pull-up/pull-downs are enabled. Listed below are
the regulators and converter naming conventions:
L1 = Sleep/Deep-Sleep Linear Regulator
L2 = High-Current Linear Regulator
DC2DC = Sleep/Deep-Sleep DC-DC Converter
Note: If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD,
VCC_USB, VCC_USIM) are powered off during deep-sleep mode, the GPIOs behave the same as
described above; however, they float after the supplies are removed.
Table 6-8. GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode
Description L2 L1 DC2DC Units
Duration of the GPIO Pu/Pd states being
enabled and the de-assertion of
PWR_EN
0.1 0.13 1.13 msec
6-10 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.2.7 Standby-Mode Timing
6.2.8 Idle-Mode Timing
6.2.9 Frequency-Change Timing
Table 6-9. Standby-Mode Timing Specifications
Symbol Description Min Typical Max Units
—13M mode to standby mode entry —0.34 —msec
—Standby mode exit to 13M mode10.28 —11.282msec
—Run mode to standby mode entry —0.34 —msec
—Standby mode exit to run mode10.43 0.39 11.432msec
NOTES:
1. The 13M oscillator is programmable
2. Add 0.1ms if the wake up event is external
Table 6-10. Idle-Mode Timing Specifications
Symbol Description Min Typical Max Units
—13M mode to deep idle mode entry — 1 — µs
—Deep idle mode exit to 13M mode — 1 — µs
—Run mode to idle run mode entry — 1 — µs
—Idle run mode exit to run mode — 1 — µs
Table 6-11. Frequency-Change Timing Specifications
Symbol Description Min Typical Max Units
—Delay between MCR command to
frequency change sequence completion —1501—µs
—Delay to change between turbo, half-
turbo and run modes — 12—µs
—Delay to enter 13M mode from any Run
mode 3— 1 — µs
—Delay to exit 13M mode to any Run mode — 24—µs
NOTES:
1. Any change to the CCCR[2N or L] bits followed by a write to CLFCFG[F] to initiate a frequency change
sequence, results in a PLL restart
2. Changing between turbo, half-turbo and run modes does not require a PLL restart
3. Software can only change into 13M mode from any run mode
4. Assuming software uses the PLL early enable feature (CCCR[PLL_EARLY_EN] prior to a frequency
change sequence
Electrical, Mechanical, and Thermal Specification 6-11
Intel® PXA270 Processor
AC Timing Specifications
6.2.10 Voltage-Change Timing
The PWR I2C uses the regular I2C protocol. The PWR I2C is clocked at 40 kHz (160 kHz fast-
mode operation is supported). Software controls the time required for initiating the voltage change
sequence through completion. The voltage-change timing is a product of the number of commands
issued plus the number of software programmed delays. Table 6-12 shows the timing of a 1 byte
command issued to the power manager IC.
Set the I2C programmable output ramp rate with a default/reset ramp rate of 10mV/µs (refer to
VCC_CORE ramp rate specification in the Electrical Section) to support VCC_CORE dynamic
voltage management.
Table 6-12. Voltage-Change Timing Specification for a 1-Byte Command
6.3 GPIO Timing Specifications
Table 6-13 shows the general-purpose I/O (GPIO) AC timing specifications.
Symbol Description Min Typical Max Units
—Delay between voltage change sequence
start1 to command received by PMIC —18 —cycles2
NOTES:
1. Write 1 to PWRMODE[VC]
2. 40 kHz cycles
Table 6-13. GPIO Timing Specifications
Symbol Parameter Min Max Units Notes
taGPIO1Assertion time required to detect
GPIO edge 154 —ns run, idle, or sense power modes
taGPIOLP2Assertion time required to detect
GPIO low-power edge 62.5 —µs standby, sleep, or deep-sleep
power modes
tdGPIO1De-assertion time required to
detect GPIO edge 154 —ns run, idle, or sense power modes
tdGPIOLP2De-assertion time required to
detect GPIO low-power edge 62.5 —µs standby, sleep, or deep-sleep
power modes
tdiGPIO3Time it takes for a GPIO edge to
be detected internally 231 —ns run, idle, or sense power modes
tdiGPIOLP4Time it takes for a GPIO low-
power edge to be detected
internally
93.75 —µs standby, sleep, or deep-sleep
power modes
NOTES:
1. Period equal to two 13-MHz cycles
2. Period equal to two 32-kHz cycles
3. Period equal to three 13-MHz cycles
4. Period equal to three 32-kHz cycles
Note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally
(2 cycles for assertion (note 2) and 1 additional cycle for detection).
6-12 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4 Memory and Expansion-Card Timing Specifications
Interfaces with the following memories must observe the AC timing requirements given in the
following subsections:
•Section 6.4.1, “Internal SRAM Read/Write Timing Specifications”
•Section 6.4.2, “SDRAM Parameters and Timing Diagrams”
•Section 6.4.3, “ROM Parameters and Timing Diagrams”
•Section 6.4.4, “Flash Memory Parameters and Timing Diagrams”
•Section 6.4.5, “SRAM Parameters and Timing Diagrams”
•Section 6.4.6, “Variable-Latency I/O Parameters and Timing Diagrams”
•Section 6.4.7, “Expansion-Card Interface Parameters and Timing Diagrams”
Note: The diagrams in this section use the following conventions:
•Input signals to the processor are represented using dashed waveforms.
•Outputs and bidirectional signals are represented using solid waveforms.
•Fixed parameters are shown using double arrows in grey (black and white print) or green
(color print).
•Programmable parameters are shown using bold single arrows.
•The processor register that is used to change a specific timing is given in the corresponding
timing table.
6.4.1 Internal SRAM Read/Write Timing Specifications
6.4.2 SDRAM Parameters and Timing Diagrams
Table 6-15 shows the timing parameters used in Figure 6-7. Also see Section 6.4.3 and Figure 6-11
for additional SDRAM bus tenure information. See Figure 6-10 for SDRAM fly-by bus tenures.
Table 6-14. SRAM Read/Write AC Specification
Symbols Parameters MIN TYP MAX Units
tsramRD 4-beat read transfer — 9 — system bus
clocks
tsramWR 4-beat write transfer — 7 — system bus
clocks
Electrical, Mechanical, and Thermal Specification 6-13
Intel® PXA270 Processor
AC Timing Specifications
Table 6-15. SDRAM Interface AC Specifications (Sheet 1 of 2)
Symbols Parameters
VCC_MEM =
1.8V +20% / –5%3VCC_MEM =
2.5V +/- 10%4VCC_MEM =
3.3V +/- 10%5
Units
Notes
MIN TYP MAX MIN TYP MAX MIN TYP MAX
tsdCLK SDCLK1, SDCLK2
period 9.6 — 76.9 9.6 — 76.9 9.6 — 76.9 ns 1,
2
tsdCMD
nSDCAS,
nSDRAS, nWE,
nSDCS assert time
1—11—11—1SDCLK —
tsdCAS
nSDCAS to
nSDCAS assert
time
2——2——2——SDCLK —
tsdRCD
nSDRAS to
nSDCAS assert
time
1MDCNFG
[DTCx] 31MDCNFG
[DTCx] 31MDCNFG
[DTCx] 3SDCLK 6
tsdRP nSDRAS Pre
charge 2MDCNFG
[DTCx] 32MDCNFG
[DTCx] 32MDCNFG
[DTCx] 3SDCLK 6
tsdCL nSDRAS to
nSDCAS delay 2MDCNFG
[DTCx] 32MDCNFG
[DTCx] 32MDCNFG
[DTCx] 3SDCLK 6
tsdRAS nSDRAS active
time 3MDCNFG
[DTCx] 73MDCNFG
[DTCx] 73MDCNFG
[DTCx] 7SDCLK 6
tsdRC nSDRAS cycle
time 4MDCNFG
[DTCx] 11 4MDCNFG
[DTCx] 11 4MDCNFG
[DTCx] 11 SDCLK 6
tsdWR
write recovery time
(time from last data
in the
PRECHARGE)
2—22—22—2SDCLK —
tsdSDOS
MA<24:10>,
MD<31:0>,
DQM<3:0>,
nSDCS<3:0>,
nSDRAS,
nSDCAS, nWE,
nOE, SDCKE1,
RDnWR output
setup time to
SDCLK<2:1> rise
TBD ——TBD —TBD ——ns —
tsdSDOH
MA<24:10>,
MD<31:0>,
DQM<3:0>,
nSDCS<3:0>,
nSDRAS,
nSDCAS, nWE,
nOE, SDCKE1,
RDnWR output
hold time from
SDCLK<2:1> rise
TBD ——TBD —TBD ——ns —
VCC_CORE = 0.85 V +/–
10%, with 1.71 V<=
VCC_MEM <= 3.63 V
VCC_CORE = 1.1 V +/–
10%, with 1.71 V <=
VCC_MEM <= 3.63 V
VCC_CORE = 1.3 V +/–
10%, with 1.71 V <=
VCC_MEM <= 3.63 V
6-14 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
tsdSDIS
MD<31:0> read
data input setup
time from
SDCLK<2:1> rise
TBD ——0.5 ——0.5 ——ns —
tsdSDIH
MD<31:0> read
data input hold
time from
SDCLK<2:1> rise
TBD ——1.8 ——1.8 ——ns —
NOTES:
1. SDCLK for SDRAM slowest period is accomplished by divide-by-2 of the 26-MHz CLK_MEM. The fastest possible SDCLK is
accomplished by configuring CLK_MEM at 104 MHz and not setting MDREFR[KxDB2].
2. SDCLK1 and SDCLK2 frequencies are configured to be CLK_MEM frequency divided by 1 or 2, depending on the bit fields
MDREFR[K1DB2] and MDREFR[K2DB2] settings.
3. These numbers are for VCC_MEM = 1.8 V +20% / –5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the
system memory buffer strength registers (BSCNTRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK<2:1>
divide-by-2 and divide-by-4 register bits MDREFR[KxDB2] clear.
4. These numbers are for VCC_MEM = 2.5 V +/– 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-
by-2 and divide-by-4 register bit MDREFR[KxDB2] clear.
5. These numbers are for VCC_MEM = 3.3 V +/– 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK<2:1> divide-
by-2 and divide-by-4 register bit MDREFR[KxDB2] clear.
6. Refer to the “Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for register configuration.
Table 6-15. SDRAM Interface AC Specifications (Sheet 2 of 2)
Symbols Parameters
VCC_MEM =
1.8V +20% / –5%3VCC_MEM =
2.5V +/- 10%4VCC_MEM =
3.3V +/- 10%5
Units
Notes
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Electrical, Mechanical, and Thermal Specification 6-15
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-7. SDRAM Timing
nop act
nop
read nop pre nop act nop write nop pre nop
0b0000 0 1 2 3
tsdRCD
tsdRAS
tsdCMD
tsdRP
tsdRC
tsdCMD
tsdCL
tWR
tsdSDOH
tsdSDOS
tsdIH
tsdSDIS
tsdCLK
mask data values
SDCLK<1>
SDCKE<1>
command
nSDCS<0>
nSDRAS
nSDCAS
nWE
MD<31:0> read
MD<31:0> write
DQM<3:0>
RDnWR
6-16 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-8. SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing
read(0) pre(1) nop act(1) nop write(1) nop
col bank row col
rd0_0 rd0_1 rd0_2 rd0_3
wd1_0 wd1_1 wd1_2 wd1_3
0b0000 0 1 2 3
1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk), MDCNFG[STACK] = 0b00
mask data bytes
SDCLK<1>
SDCKE<1>
command
nSDCS<0>
nSDCS<1>
nSDRAS
nSDCAS
MA<24:10>
nWE
MD<31:0> (read)
MD<31:0> (write)
DQM<3:0>
RDnWR
2. See the SDRAM timing diagram.
NOTES:
Electrical, Mechanical, and Thermal Specification 6-17
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-9. SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing
nop write(0) nop write(0) nop
col col
wd0_0 wd0_1 wd0_2 wd0_3 wd0_4 wd0_5 wd0_6 wd0_7
mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7
mask data bytes
1. MDCNFG[DTC] = 0b01 (CL = 2, tRP = 2 clks)
SDCLK<1>
SDCKE<1>
command
nSDCS<0>
nSDRAS
nSDCAS
MA<24:10>
nWE
MD<31:0>
DQM<3:0>
RDnWR
2. See the SDRAM timing diagram.
NOTES:
6-18 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4.3 ROM Parameters and Timing Diagrams
Table 6-16 lists the timings for ROM reads. See Figure 6-11, Figure 6-12, Figure 6-13, and
Figure 6-14 for timings diagrams representing burst and non-burst ROM reads.
Note: Table 6-16 lists programmable register items. See the “Memory Controller” chapter in the Intel®
PXA27x Processor Family Developer’s Manual for register configurations for more information on
these items.
Figure 6-10. SDRAM Fly-by DMA Timing
read pre nop act nop write nop
col bank row col
rd0 rd1 rd2 rd3 wd0 wd1 wd2 wd3
0b0000 mask0 mask1 mask2 mask3
drive data wd3
drive data wd2
drive data wd1
drive data wd0
latch DVAL[1] asserted
latch data rd3
latch data rd2
latch data rd1
latch data rd0
1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk)
mask data bytes
Latch data on rising edge of SDCLK<1> when
DVAL<0> is asserted.
Using DVAL<1> driven two clocks early,
drive data on rising edge of SDCLK<2>.
SDCLK<1>
SDCLK<2>
SDCKE<1>
command
nSDCS<0>
nSDCS<2>
nSDRAS
nSDCAS
MA<24:10>
nWE
MD<31:0>
DQM<3:0>
RDnWR
DVAL<0>
DVAL<1>
2. See the SDRAM timing diagram.
NOTES:
Table 6-16. ROM AC Specification (Sheet 1 of 2)
Symbols Parameters MIN TYP MAX Units†Notes
tromAS Address setup to nCS assert 1 — 1 clk_mem —
tromCES nCS setup to nOE asserted — — 0 clk_mem —
tromCEH nCS hold from nOE deasserted — — 0 clk_mem —
tromDSOH MD setup to address valid 1.5 — — clk_mem —
Electrical, Mechanical, and Thermal Specification 6-19
Intel® PXA270 Processor
AC Timing Specifications
tromDOH MD hold from address valid 0 — — clk_mem —
tromAVDVF Address valid to data valid for the
first read access 2MSCx[RDF]+2 32 clk_mem —
tromAVDVS
Address valid to data valid for
subsequent reads of non-burst
devices
1MSCx[RDF]+1 31 clk_mem —
tflashAVDVS Address valid to data valid for
subsequent reads of burst devices 1MSCx[RDN]+1 31 clk_mem —
tromCD nCS deasserted after a read of next
nCS or nSDCS asserted (minimum) 1MSCx[RRR]*2+
115 clk_mem —
†Numbers shown as integer multiples of the clk_mem period are ideal. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall). For more information, refer to the “Memory Control” chapter in the Intel® PXA27x
Processor Family Developer’s Manual.
Table 6-16. ROM AC Specification (Sheet 2 of 2)
Symbols Parameters MIN TYP MAX Units†Notes
6-20 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-11. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing
0 1 2 3
0b00
0b00 / 0b01 / 0b10 / 0b11
0b00
corresponding mask value
tromCD
tromAVDVS
tromAVDVS
tromAVDVS
tromAVDVF
tromAS
tromDOH
tromDSOH
tromDOH
tromDSOH
tromDOH
tromDSOH
tromDOH
tromDSOH
tromCEHtromCES
NOTE: MSC0[RDF0] = 4, MSC0[RRR0] = 1
CLK_MEM
nCS<0>
MA<25:2>
MA<1:0>(SA1110x='0')
MA<1:0>(SA1110x='1')
nADV(nSDCAS)
nOE
nWE
RDnWR
MD<31:0>
DQM<3:0>(SA1110x='0')
DQM<3:0>(SA1110x='1')
nCSx or nSDCSx
Electrical, Mechanical, and Thermal Specification 6-21
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-12. 32-Bit Burst-of-Eight ROM or Flash Read Timing
0 1 2 3 4 5 6 7
0b00
0b00 / 0b01 / 0b10 / 0b11
0b0000
corresponding mask value
tromCD
tromAVDVS
tromAVDVF
tDOH
tDSOH
tCEHtCES
tAS
NOTE: MSC0[RDF0] = 4, MSC0[RDN0] = 1, MSC0[RRR0] = 1
CLK_MEM
nCS<0>
MA<25:5>
MA<4:2>
MA<1:0>(SA1110x='0')
MA<1:0>(SA1110x='1')
nADV(nSDCAS)
nOE
nWE
RDnWR
MD<31:0>
DQM<3:0>(SA1110x='0')
DQM<3:0>(SA1110x='1')
nCSx or nSDCSx
6-22 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-13. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing
address
0 1 2 3 0 1 2 3
0b0
0b0 / 0b1
0b00
0b00 or 0b10/0b01
tromCD
tromAVDVS
tromAVDVF
tromAVDVS
tromAVDVF
tromDOH
tromDSOH
tromDOH
tromDSOH
tromCEHtromCES
tromAS
NOTE: MSC0[RDF0] = 4, MSC0[RDN0] = 1, MSC0[RRR0] = 0
CLK_MEM
nCS<0>
MA<25:4>
MA<3>
MA<2:1>
MA<0>(SA1110x='0')
MA<0>(SA1110x='1')
nADV(nSDCAS)
nOE
nWE
RDnWR
MD<15:0>
DQM<1:0>(SA1110x='0')
DQM<1:0>(SA1110x='1')
nCSx or nSDCSx
Electrical, Mechanical, and Thermal Specification 6-23
Intel® PXA270 Processor
AC Timing Specifications
6.4.4 Flash Memory Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for asynchronous
and synchronous flash-memory interfaces with the memory controller.
6.4.4.1 Flash Memory Read Parameters and Timing Diagrams
Section 6.4.4.1.1 describes asynchronous flash reads. Section 6.4.4.1.2 describes synchronous
flash reads.
6.4.4.1.1 Asynchronous Flash Read Parameters and Timing Diagrams
The timings listed in Table 6-16 for ROM reads also apply to asynchronous flash reads. See
Figure 6-11, Figure 6-12, Figure 6-13, and Figure 6-14 for timings diagrams representative of an
asynchronous flash read.
Figure 6-14. 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing
addr addr + 1 addr addr addr addr + 1
0 0 0 0
0/1 0/1 0/1 0/1
0b00 0b00 0b00 0b00
mask mask mask mask
tflashAVDVS
tromAVDVFtromAVDVFtromAVDVFtromAVDVS
tromAVDVF
tromCD
tromCD
tromCD
tromDOH
tromDSOH
tromDOH
tromDSOH
tromDOH
tromDSOH
tromDOH
tromDSOH
tromDOH
tromDSOH
tromDOH
tromDSOH
tromCES
tromCES
tromCES
tromCEH
tromCES
tromAS
tromAS
tromAStromAS
32-bit read
NOTE: MSC0[RDF0] = 2, MSC0[RDN0] = 1, MSC0[RRR0] = 1
16-bit read 8-bit read
Applies to:
16-bit ROM or
non-burst flash
16-bit SRAM
Applies to:
16-bit ROM or
non-burst flash
16-bit SRAM
16-bit burst flash
Applies to:
16-bit ROM or
non-burst flash
16-bit SRAM
16-bit burst flash
32-bit Read
Applies to:
16-bit Burst Flash
CLK_MEM
nCS<0>
MA<25:1>
MA<0>(SA1110x='0')
MA<0>(SA1110x='1')
nADV(nSDCAS)
nOE
nWE
RDnWR
MD<15:0>
DQM<1:0>(SA1110x='0')
DQM<1:0>(SA1110x='1')
6-24 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4.4.1.2 Synchronous Flash Read Parameters and Timing Diagrams
Table 6-17 lists the timing parameters used in Figure 6-15, and, for stacked flash packages,
Figure 6-16.
Table 6-17. Synchronous Flash Read AC Specifications (Sheet 1 of 2)
Symbols Parameters MIN TYP MAX MIN TYP MAX MIN TYP MAX Units
Notes
Divide by 12Divide by 23Divide by 44
tffCLK SDCLK0 period 9.6 —38.5 19.
2—76.9 38.5 —154 ns 1
tffAS
MA<25:0> setup to
nSDCAS (as
nADV) asserted
1 — 1 1 — 2 1 — 4 CLK_MEM —
tffCES
nCS setup to
nSDCAS (as
nADV) asserted
1 — 1 1 — 2 1 — 4 CLK_MEM —
tffADV nSDCAS (as
nADV) pulse width 1 — 1 3 — 3 7 — 7 CLK_MEM —
tffOS
nSDCAS (as
nADV) deassertion
to nOE assertion
1
FCC – 1
(for
FCC<5)
FCC – 2
(for
FCC>=5)
13 2
(FCC – 1)
* 2
(for
FCC<5)
(FCC – 2)
* 2
(for
FCC>=5)
26 7
(FCC * 4)
– 7
(for
FCC<5)
(FCC – 2)
* 4
(for
FCC>=5)
52 CLK_MEM 5
tffCEH nOE deassertion to
nCS deassertion 4 — 4 8 — 8 16 —16 CLK_MEM —
tffDS CLK to data valid 2FCC 15 2FCC 15 2FCC 15 CLK_MEM 5
VCC_MEM =
1.8V +20% / -5%6VCC_MEM =
2.5V +/- 10%7VCC_MEM =
3.3V +/- 10%8
tffSDOS
MA<25:0>,
MD<31:0>,
DQM<3:0>,
nCS<3:0>,
nSDCAS (nADV),
nWE, nOE,
RDnWR output
setup time to
SDCLK<2:1> rise
TBD — — TB
D— — TBD — — ns —
tffSDOH
MA<25:0>,
MD<31:0>,
DQM<3:0>,
nCS<3:0>,
nSDCAS (nADV),
nWE, nOE,
RDnWR output
hold time from
SDCLK<2:1> rise
TBD — — TB
D— — TBD — — ns —
VCC_CORE = 0.85 V +/
– 10%, with 1.71 V<=
VCC_MEM <= 3.63 V
VCC_CORE = 1.1 V +/–
10%, with 1.71 V <=
VCC_MEM <= 3.63 V
VCC_CORE = 1.3 V +/–
10%, with 1.71 V <=
VCC_MEM <= 3.63 V
Electrical, Mechanical, and Thermal Specification 6-25
Intel® PXA270 Processor
AC Timing Specifications
tffSDIS
MD<31:0> read
data input setup
time from
SDCLK<2:0> rise
TBD — — 0.5 — — 0.5 — — ns —
tffSDIH
MD<31:0> read
data input hold time
from SDCLK<2:0>
rise
TBD — — 1.8 — — 1.8 — — ns —
NOTES:
1. SDCLK0 may be configured to be CLK_MEM divided by 1, 2 or 4. SDCLK0 for synchronous flash memory can be at the slowest,
divide-by-4 of the 26-MHz CLK_MEM. The fastest possible SDCLK0 is accomplished by configuring CLK_MEM at 104 MHz and
clearing the MDREFR[K0DB2] or MDREFR[K0DB4] bit fields.
2. SDCLK0 frequency equals CLK_MEM frequency (MDREFR[K0DB4] and MDREFR[K0DB2] bit fields are clear)
3. SDCLK0 frequency equals CLK_MEM/2 frequency (MDREFR[K0DB2] is set and MDREFR[K0DB4] is clear).
4. SDCLK0 frequency equals CLK_MEM/4 frequency (MDREFR[K0DB4] is set).
5. Use SXCNFG[SXCLx] to configure the value for the frequency configuration code (FCC).
6. These numbers are for VCC_MEM = 1.8 V +20% / -5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the
system memory buffer strength registers (BSCN TRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK0 divide-
by-2 and divide-by-4 register bits (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding
output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period.
7. These numbers are for VCC_MEM = 2.5 V +/– 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2
and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output
setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period.
8. These numbers are for VCC_MEM = 3.3 V +/– 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2
and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output
setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period.
Table 6-17. Synchronous Flash Read AC Specifications (Sheet 2 of 2)
Symbols Parameters MIN TYP MAX MIN TYP MAX MIN TYP MAX Units
Notes
6-26 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-15. Synchronous Flash Burst-of-Eight Read Timing
0b00
0b00/0b01/0b10/0b11
0b0000
corresponding mask value
CODE+1
CODE
NOTES: 1) SXCNFG[CL] = 0b100 (CL = 5, frequency code configuration = 4)
2) CODE = frequency configuration code
CLK_MEM
SDCLK<0>
MA<19:2>
MA<1:0>(SA1110x=0)
MA<1:0>(SA1110x=1)
nCS<0>
nADV(nSDCAS)
nOE
nWE
MD<31:0>
DQM<3:0>(SA1110x=0)
DQM<3:0>(SA1110x=1)
Electrical, Mechanical, and Thermal Specification 6-27
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-16. Synchronous Flash Stacked Burst-of-Eight Read Timing
0b00
0b00/0b01/0b10/0b11
0b0000
corresponding mask value
CODE+1
CODE
NOTE: SXCNFG[CL] = 0b100 (CL = 5, frequency code configuration = 4)
SA1110CR[SXSTACK] = 0b01
CLK_MEM
SDCLK<3>
MA<19:2>
MA<1:0>(SA1110x=0)
MA<1:0>(SA1110x=1)
nCS<0>
nADV(nSDCAS)
nOE
nWE
MD<31:0>
DQM<3:0>(SA1110x=0)
DQM<3:0>(SA1110x=1)
6-28 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-17 indicates which clock data would be latched following the assertion of
nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in
the diagram indicated by different frequency configuration codes (Fcodes or FCCs) is equal to the
number of SDCLK0 cycles between the READ command and the clock edge on which data is
driven onto the bus.
Figure 6-17. First-Access Latency Configuration Timing
Valid Address
0b0000
Beat 0 Beat 1 Beat 2
Beat 3
Beat 4 Beat 5
Beat 0 Beat 1 Beat 2 Beat 3 Beat 4
Beat 0 Beat 1 Beat 2 Beat 3
Beat 0 Beat 1 Beat 2
Beat 0 Beat 1
Beat 0
Code 7
Code 6
Code 5
Code 4
Code 3
Code 2
NOTE: CODE = Frequ ency Configuration Code
SDCLK<0>
nCS<0>
MA<19:0>
nSDCAS
DQM<3:0>
MD (Code = 2)
MD (Code = 3)
MD (Code = 4)
MD (Code = 5)
MD (Code = 6)
MD (Code = 7)
Electrical, Mechanical, and Thermal Specification 6-29
Intel® PXA270 Processor
AC Timing Specifications
The burst read example shown in Figure 6-18 represents waveforms that result when
SXCNFG[SXCLx] is configured as 0b0100, representing a frequency configuration code equal to
3. The following example can be used to help determine the appropriate setting for
SXCNFG[SXCLx].
Parameters defined by the processor:
•tffSDOH (max) = SDCLK<0> to CE# (nCE), ADV# (nADV), or address valid, whichever
occurs last
•tffSDIS (min) = Data setup to SDCLK<0>
Parameters defined by flash memory:
•tVLQV (min) = ADV# low to output delay
•tVLCH (min) = ADV# low to clock
•tCHQV (max) = SDCLK<0> to output valid
Use the following equations when calculating the frequency configuration code:
(1) SDCLK period = (1 / frequency)
(2) n (SDCLK period) ≥ tVLQV - tVLCH - tCHQV
(3) n = (tVLQV - tVLCH - tCHQV) / SDCLK period, where
n = frequency configuration code rounded up to integer value
(4) SDCLK period ≥ tCHQV + tffSDIS
Example
The timing information below is only an example. See Table 6-17 for actual synchronous AC
timings.
SDCLK<0> frequency = 50 MHz
tVLQV = 70 ns (typical timing from synchronous flash memory)
tVLCH = 10 ns (min)
tCHQV = 14 ns (min)
From Eq.(1): 1 / 50 (MHz) = 20 ns
From Eq.(2): n(20 ns) ≥ 70 ns - 10 ns - 14 ns
n(20 ns) ≥ 46 ns
n = (46 / 20) ns = 2.3 ns
n = 3
Use equation 4 to help verify the maximum possible frequency at which the synchronous flash
memory can run with the memory controller. The following example uses equation 4:
SDCLK<0> frequency = 66 MHz
tCHQV = 11 ns (max)
tffSDIS = 3 ns (min)
From Eq. (1): 1 / 66 (MHz) = 15.15 ns
From Eq. (4): 15.15 ns ≥ 11 ns + 3 ns
15.15 ns ≥ 14 ns
The results from this example indicate that the 66-MHz memory works without problems with the
memory controller.
Note: All AC timings must be considered to avoid timing violations in the memory-to-memory-controller
interface.
6-30 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4.4.2 Flash Memory Write Parameters and Timing Diagrams
Table 6-18 lists the AC specification for both burst and non-burst flash writes shown in Figure 6-19
and, for stacked flash packages, Figure 6-20.
Figure 6-18. Synchronous Flash Burst Read Example
Valid Address
Beat 0 Beat1
tCHQV
tffSDOH
tffSDOH
tffSDOH
tffSDIS
tVLQV
tAVCH
SDCLK<0>
nCS<0>
nSDCAS (ADV#)
MA
MD
Table 6-18. Flash Memory AC Specification (Sheet 1 of 2)
Symbols Parameters MIN TYP MAX Units1Notes
tflashAS Address setup to nCS assert 1 — 1 clk_mem —
tflashAH Address hold from nWE de-asserted 1 — 1 clk_mem —
tflashASW Address setup to nWE asserted 1 — 3 clk_mem 2
tflashCES nCS setup to nWE asserted 2 — 2 clk_mem —
tflashCEH nCS hold from nWE de-asserted 1 — 1 clk_mem —
tflashWL nWE asserted time 1MSCx[RDF]+1 31 clk_mem —
tflashDSWH MD/DQM setup to nWE de-asserted 2MSCx[RDF]+2 32 clk_mem —
tflashDH MD/DQM hold from nWE de-
asserted 1 — 1 clk_mem —
tflashDSOH MD setup to address valid 1.5 — — clk_mem —
Electrical, Mechanical, and Thermal Specification 6-31
Intel® PXA270 Processor
AC Timing Specifications
tflashDOH MD hold from address valid 0 — — clk_mem —
tflashCD
nCS de-asserted after a read/write to
next nCS or nSDCS asserted
(minimum)
1MSCx[RRR]*2 +
115 clk_mem —
NOTES:
1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall).
2. On the first data beat of burst transfer, the tflashASW is 3 CLK_MEM periods. On subsequent data beats, the tflashASW is 1
CLK_MEM period.
Figure 6-19. 32-Bit Flash Write Timing
Table 6-18. Flash Memory AC Specification (Sheet 2 of 2)
Symbols Parameters MIN TYP MAX Units1Notes
command address data address
0b00 0b00
CMD DATA
0b0000 0b0000
tflashCD
tflashDSWHtflashDSWH
tflashWLtflashWL
tflashCD
tflashDHtflashDH
tflashAH
tflashCEH
tflashCES
tflashASW
tflashAH
tflashCEH
tflashCES
tflashASW
tflashAStflashAS
NOTE: MSC0[RDF0] = 2, MSC0[RRR0] = 2
First Bus Cycle Second Bus Cycle
CLK_MEM
nCS<0>
MA<25:2>
MA<1:0>
nWE
nOE
RDnWR
MD<31:0>
DQM<3:0>
nADV(nSDCAS)
nCSx or nSDCSx
6-32 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-20. 32-Bit Stacked Flash Write Timing
command address data address
0b00 0b00
CMD DATA
0b0000 0b0000
tflashCD
tflashDSWHtflashDSWH
tflashWLtflashWL
tflashCD
tflashDHtflashDH
tflashAH
tflashCEH
tflashCES
tflashASW
tflashAH
tflashCEH
tflashCES
tflashASW
tflashAStflashAS
* MSC0[RDF0] = 2, MSC0[RRR0] = 2, SA1110{SXSTACK] = 00
First Bus Cycle Second Bus Cycle
CLK_MEM
nWE
MA<25:2>
MA<1:0>
nCS<0> or nCS<1>
nOE
RDnWR
MD<31:0>
DQM<3:0>
nADV(nSDCAS)
nCSx
Electrical, Mechanical, and Thermal Specification 6-33
Intel® PXA270 Processor
AC Timing Specifications
6.4.5 SRAM Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for SRAM
interfaces with the memory controller.
6.4.5.1 SRAM Read Parameters and Timing Diagrams
The timing for a read access is identical to that for a non-burst ROM read (see Figure 6-11). The
timings listed in Table 6-16 for ROM reads are also used for SRAM reads. See Figure 6-11 and
Figure 6-14 for timings diagrams representing 16-bit SRAM transferring four, two, and one byte(s)
during read-bus tenures.
6.4.5.2 SRAM Write Parameters and Timing Diagrams
Figure 6-22 and Figure 6-23 show the timing for 32-bit and 16-bit SRAM writes. Table 6-19 lists
the timings used in Figure 6-22 and Figure 6-23.
Figure 6-21. 16-Bit Flash Write Timing
addr
0b0
Bytes 1:0
0b00
tflashCD
tflashDSWH
tflashWL
tflashDH
tflashCEH
tflashCES
tflashAS
Applies to:
16-bit Non-Burst Flash
16-bit Burst Flash
NOTE: MSC1[RDN2] = 2, MSC1[RDF2] = 1, MSC1[RRR2] = 2
CLK_MEM
nCS<2>
MA<25:1>
MA<0>
nWE
nOE
RDnWR
MD<15:0>
DQM<1:0>
nADV(nSDCAS)
nCSx or nSDCSx
6-34 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
During writes, data pins are actively driven by the processor and are not three-stated, regardless of
the states of the individual DQM signals. For SRAM writes, the DQM signals are used as byte
enables.
Note: Table 6-19 lists programmable register items. See the “Memory Controller”chapter in the Intel®
PXA27x Processor Family Developer’s Manual for register configurations for more information on
these items.
Table 6-19. SRAM Write AC Specification
Symbols Parameters MIN TYP MAX Units1Notes
tsramAS Address setup to nCS assert 1 — 1 clk_mem —
tsramAH Address hold from nWE de-asserted 1 — 1 clk_mem —
tsramASW Address setup to nWE asserted 1 — 3 clk_mem 2
tsramCES nCS setup to nWE asserted 2 — 2 clk_mem —
tsramCEH nCS hold from nWE de-asserted 1 — 1 clk_mem —
tsramWL nWE asserted time 1MSCx[RDN]+1 31 clk_mem —
tsramDSWH MD/DQM setup to nWE de-asserted 2MSCx[RDN]+2 32 clk_mem —
tsramDH MD/DQM hold from nWE de-
asserted 1 — 1 clk_mem —
tramCD nCS de-asserted after a read to next
nCS or nSDCS asserted (minimum) 1MSCx[RRR]*2+
115 clk_mem —
NOTES:
1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall).
2. On the first data beat of burst transfer, the tsramASW is 3 CLK_MEM periods. On subsequent data beats, the tsramASW is 1
CLK_MEM period.
Electrical, Mechanical, and Thermal Specification 6-35
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-22. 32-Bit SRAM Write Timing
0 1 2 3
byte addr byte addr byte addr byte addr
D0 D1 D2 D3
mask0 mask1 mask2 mask3
tsramCD
tsramWL
tsramWL
tsramWL
tsramWL
tsramDOH
tsramDH
tsramDSWH
tsramCEHW
tsramAH
tsramASW
tsramAH
tsramASW
tsramCESW
tsramAS
NOTE: 4-Beat burst, MSC0[RDN0] = 2, MSC0[RRR0] = 1
CLK_MEM
nCS<0>
MA<25:2>
MA<1:0>
nWE
nOE
RDnWR
MD<31:0>
DQM<3:0>
nCSx or nSDCSx
nADV(nSDCAS)
6-36 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4.6 Variable-Latency I/O Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for VLIO memory
interfaces with the memory controller.
Table 6-20 lists the timing-information references for both the read and the write timing diagrams.
Note: Table 6-20 lists programmable register items. For more information on these items, see the
“Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for
register configurations.
Figure 6-23. 16-bit SRAM Write for 4/2/1 Byte(s) Timing
addr addr+1 addr addr
'0' '0' '0' '0' or '1'
Bytes 1:0 Bytes 3:2 Bytes 1:0 Byte 0 OR 1
0b00 0b00 0b01 / 0b10
tsramCD
tsramDSWH
tsramDSWH
tsramDSWH
tsramWLtsramWLtsramWL
tsramWL
tsramCDtsramCD
tsramDH
tsramDH
tsramDSWH
tsramDH
tsramDH
tsramCEH
tsramCES
tsramCEH
tsramCEStsramCEH
tsramWL
tsramASW
tsramAH
tsramCES
tramAStramAStramAS
32-bit Write 16-bit Write 8-bit Write
NOTE: MSC1[RDF2]=1, MSC1[RDN]=2, MSC1[RRR2]=2
CLK_MEM
nCS<2>
MA<25:1>
MA<0>
nWE
nOE
RDnWR
MD<15:0>
DQM<1:0>
nADV(nSDCAS)
n
CSx or nSDCSx
Electrical, Mechanical, and Thermal Specification 6-37
Intel® PXA270 Processor
AC Timing Specifications
6.4.6.1 Variable Latency I/O Read Timing
Figure 6-24 shows the timing for 32-bit variable-latency I/O (VLIO) memory reads. Table 6-20
lists the timing parameters used in these diagrams.
Table 6-20. VLIO Timing
Symbols Parameters MIN TYP MAX2Units1Notes
tvlioAS Address setup to nCS asserted 1 — 1 clk_mem —
tvlioAH Address hold from nPWE/nOE de-
asserted 2MSCx[RDN] 30 clk_mem —
tvlioASRW0 Address setup to nPWE/nOE
asserted (1st access) 3 — 3 clk_mem —
tvlioASRWn Address setup to nPWE/nOE
asserted (next access(es)) 2MSCx[RDN] 30 clk_mem —
tvlioCES nCS setup to nPWE/nOE asserted 2 — 2 clk_mem —
tvlioCEH nCS hold from nPWE/nOE de-
asserted 1 — 1 clk_mem —
tvlioDSWH MD/DQM setup (minimum) to nPWE
de-asserted 5MSCx[RDF]+2 32 clk_mem —
tvlioDH MD/DQM hold from nPWE de-
asserted 1 — 1 clk_mem —
tvlioDSOH MD setup to address changing 1.5 —clk_mem —
tvlioDOH MD hold from address changing 0 — ns —
tvlioRDYH RDY hold from nPWE/nOE de-
asserted 0 — — ns —
tvlioRWA nPWE/nOE assert period between
writes 4MSC[RDF]+1 +
Waits
31 +
Waits clk_mem —
tvlioRWD nPWE/nOE de-asserted period
between writes 4MSCx[RDN*2] 60 clk_mem 3
tvlioCD
nCS de-asserted after a read/write to
next nCS or nSDCS asserted
(minimum)
1MSCx[RRR]*2 +
115 clk_mem —
NOTES:
1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall).
2. Maximum values reflect the register dynamic ranges.
3. Depending on the programmed value of MSC[RDN] and the clk_mem speed, this can be a significant amount of time.
Processor does not drive the data bus during this time between transfers. If the VLIO does not drive the data bus during this
time between transfers, the data bus is not driven for this period of time. If MSC[RDN] is programmed to 60 (which equals 60
CLK_MEM cycles), then the data bus could potentially not be driven for 30*2 = 60 CLK_MEM cycles.
6-38 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4.6.2 Variable-Latency I/O Write Timing
Figure 6-25 shows the timing for 32-bit VLIO memory writes. Table 6-20 list the timing
parameters used in Figure 6-25.
Figure 6-24. 32-Bit VLIO Read Timing
addr addr + 1 addr + 2 addr + 3
0b00
0b00/0b01/0b10/0b11
0b0000
corresponding mask value tvlioCD
tvlioRWA
tvlioRWD
tvlioRWA
tvlioRWD
tvlioRWA
tvlioRWD
tvlioDOH
tvlioDSOH
tvlioDOH
tvlioDSOH
tvlioDOH
tvlioDSOH
tvlioDOH
tvlioDSOH
tvlioRDYHtvlioRDYH
tvlioRDYH
tvlioRDYH
tvlioCEH
tvlioAH
tvlioASRWn
tvlioAH
tvlioASRWn
tvlioAH
tvlioASRWn
tvlioAH
tvlioASRW0
tvlioCES
tvlioAS
0 Waits 1 Wait 2 Waits 3 Waits
NOTE: MSC0[RDF0] = 3, MSC0[RDN0 = 2, MSC0[RRR0] = 1
CLK_MEM
nCS<0>
MA<25:2>
MA<1:0>(SA1110x='0')
MA<1:0>(SA1110x='1')
nOE
nPWE
RDnWR
RDY
RDY_sync
MD<31:0>
DQM<3:0>(SA1110x='0')
DQM<3:0>(SA1110x='1')
nCSx or nSDCSx
Electrical, Mechanical, and Thermal Specification 6-39
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-25. 32-Bit VLIO Write Timing
addr addr + 1 addr + 2 addr + 3
0b00
D0 D1 D2 D3
mask0 mask1 mask2 mask3
tvlioCD
tvlioRWA
tvlioRWD
tvlioRWA
tvlioRWD
tvlioRWA
tvlioRWD
tvlioRWA
tvlioDHtvlioDH
tvlioDSWH
tvlioDH
tvlioDSWH
tvlioDH
tvlioDSWH
tvlioDSWH
tvlioRDYHtvlioRDYH
tvlioRDYH
tvlioRDYH
tvlioCEH
tvlioAH
tvlioASRWn
tvlioAH
tvlioASRWn
tvlioAH
tvlioASRWn
tvlioAH
tvlioASRW0
tvlioCES
tvlioAS
0 Waits
NOTE: MSC0[RDF0] = 3, MSC0[RDN0] = 2, MSC0[RRR0] = 1
1 Wait 2 Waits 3 Waits
CLK_MEM
nCS<0>
MA<25:2>
MA<1:0>
nPWE
nOE
RDnWR
RDY
RDY_sync
MD<31:0>
DQM<3:0>
nCSx or nSDCSx
6-40 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.4.7 Expansion-Card Interface Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for CompactFlash*
and PC Card* (expansion card) memory interfaces with the memory controller.
Table 6-21 shows the timing parameters used in the timing diagrams, Figure 6-26 and Figure 6-27.
Note: Table 6-21 lists programmable register items. See the “Memory Controller” chapter in the Intel®
PXA27x Processor Family Developer’s Manual for register configurations for more information on
these items.
Table 6-21. Expansion-Card Interface AC Specifications
Symbols Parameters MIN TYP MAX Units Notes
tcdAVCL Address Valid to CMD Low 2MCx[SET] 127 CLK_MEM 1,2,3,4
tcdCHAI CMD High to Address Invalid 0MCx[HOLD] 63 CLK_MEM 1,2,3,5
tcdDVCL Write Data Valid to CMD Low — 1 — CLK_MEM 1,3
tcdCHWDI CMD High to Write Data Invalid — 4 — CLK_MEM 1,3
tcdDVCH Read Data Valid to CMD High 2 — — CLK_MEM 1,3
tcdCHRDI CMD High to Read Data Invalid 0 — — ns 3
tcdCMD CMD Assert During Transfers —
tcdCLPS +
tcdPHCH +
nPWAIT
assertion
—CLK_MEM 1,3
tcdILCL nIOIS16 Low to CMD Low 4 — — CLK_MEM 1,3
tcdCHIH CMD High to nIOIS16 High 2 — — CLK_MEM 1,3
tcdCLPS CMD Low to nPWAIT Sample —x_ASST_WAIT —CLK_MEM 1,3,6,7
tcdPHCH nPWAIT High to CMD High —x_ASST_HOLD —CLK_MEM 1,3,6,8
NOTES:
1. All numbers shown are ideal, integer multiples of the CLK_MEM period. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall).
2. Includes signals MA[25:0], nPREG, and nPSKTSEL.
3. CMD refers to signals nPWE, nPOE, nPIOW, and nPIOR
4. Refer to the Intel® PXA27x Processor Family Developer’s Manual, Expansion Memory Timing Configuration registers to
change the assertion of CMD using the MCx[SET] bit fields.
5. Refer to the Intel® PXA27x Processor Family Developer’s Manual, Expansion Memory Timing Configuration registers to
increase the assertion of CMD using the MCx[HOLD] bit fields.
6. Refer to the Intel® PXA27x Processor Family Developer’s Manual, Expansion Memory Timing Configuration registers to
increase timings. The timings are changed by programming the MCx[ASST] respective bit fields. Refer to the PC Card
Interface Command Assertion Code table to see the effect of MCx[ASST].
7. tcdCLPS equals CLK_MEM * x_ASST_WAIT. Refer to the PC Card Interface Command Assertion Code table in the Intel®
PXA27x Processor Family Developer’s Manual for the correlation between x_ASST_WAIT and the MCx[ASST] bit field.
8. tcdPHCH equals CLK_MEM * x_ASST_HOLD. Refer to the PC Card Interface Command Assertion Code table in the Intel®
PXA27x Processor Family Developer’s Manual for the correlation between x_ASST_HOLD and the MCx[ASST] bit field.
Electrical, Mechanical, and Thermal Specification 6-41
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-26. Expansion-Card Memory or I/O 16-Bit Access Timing
Read Data Latch
tcdCMD
tcdPHCH
tcdCLPS
tcdAVCL
tcdCHAI
tcdCHRDI
tcdDVCH
tcdCHWDItcdDVCL
tcdCHIHtcdILCL
CLK_MEM
nPCE[2],nPCE[1]
MA[25:0],nPREG,PSKTSEL
nPWE,nPOE,nPIOW,nPIOR
nIOIS16
MD[15:0] (write)
RDnWR
nPWAIT
MD[15:0] (read)
6-42 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
Figure 6-27. Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing
Low Byte High Byte
Read Data LatchRead Data Latch
tcdPHCH
tcdCLPS
tcdPHCH
tcdCLPS
tcdCMD
tcdCHAI
tcdAVCL
tcdCMD
tcdCHAI
tcdAVCL
tcdCHWDI
tcdCHWDI
tcdDVCL
tcdCHRDI
tcdDVCH
tcdCHRDI
tcdDVCH
tcdCHIHtcdILCL
CLK_MEM
MA<25:1>,nPREG,PSKTSEL
MA<0>
nPCE<2>
nPCE<1>
nPIOW (or) nPIOR
RDnWR
nIOIS16
nPWAIT
MD<7:0> (read)
MD<7:0> (write)
Electrical, Mechanical, and Thermal Specification 6-43
Intel® PXA270 Processor
AC Timing Specifications
6.5 LCD Timing Specifications
Figure 6-28 describes the LCD timing parameters. The LCD pin timing specifications are
referenced to the pixel clock (L_PCLK_WR). Table 6-22 gives the values for the parameters.
Figure 6-28. LCD Timing Definitions
Table 6-22. LCD Timing Specifications
Symbol Description Min Max Units Notes
Tpclkdv L_PCLK_WR rise/fall to L_LDD<17:0>
driven valid —14 ns 1
Tpclklv L_PCLK_WR fall to L_LCLK_A0 driven
valid —14 ns 2
Tpclkfv L_PCLK_WR fall to L_FCLK_RD driven
valid —14 ns 2
Tpclkbv L_PCLK_WR rise to L_BIAS driven valid —14 ns 2
NOTES:
1. The LCD data pins can be programmed to be driven on either the rising or falling edge of the pixel clock
(L_PCLK_WR).
2. These LCD signals can toggle when L_PCLK_WR is not clocking (between frames). At this time, they are
clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK_WR pin.
L_LDD[17:0]
(rise)
L_LDD[17:0]
(fall)
L_PCLK_WR
L_LCLK_A0
L_BIAS
L_FCLK_RD
Tpclkdv
Tpclklv
Tpclkfv
Tpclkbv
Tpclkdv
6-44 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
6.6 SSP Timing Specifications
Figure 6-29 describes the SSP timing parameters. The SSP pin timing specifications are referenced
to SSPCLK. Table 6-23 gives the values for the parameters.
Note: In Figure 6-29, read the term “tSFMV” as “TSTXV.”
Figure 6-30. Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral
Figure 6-29. SSP Master Mode Timing Definitions
Table 6-23. SSP Master Mode Timing Specifications
Symbol Description Min Max Units Notes
Ts f m v SSPSCLK rise to SSPSFRM driven valid 21 ns
Trxds SSPRXD valid to SSPSCLK fall (input setup) 11 ns
Trxdh SSPSCLK fall to SSPRXD invalid (input hold) 0ns
Ts f m v SSPSCLK rise to SSPTXD valid 22 ns
SSPSCLK
SSPSFRM
SSPTXD
SSPRXD
Tsfmv
Tsfmv
Trxds Trxdh
PXA27x processor transmitting data
SSPSCLK
(from Peripheral)
SSPTXD
(from SSP)
PXA27x SSP (Slave Mode) transmitting data to external peripheral
SSPSFRM
(from Peripheral)
tSCLK2TXD_output_delay
tSFRM2TXD_output_delay
PXA27x processor transmitting data
SSPSCLK
(from Peripheral)
SSPTXD
(from SSP)
PXA27x SSP (Slave Mode) transmitting data to external peripheral
SSPSFRM
(from Peripheral)
tSCLK2TXD_output_delay
tSFRM2TXD_output_delay
Electrical, Mechanical, and Thermal Specification 6-45
Intel® PXA270 Processor
AC Timing Specifications
Table 6-24. Timing Specification SSP Slave Mode Transmitting Data to External Peripheral
Figure 6-31. Timing Diagram for SSP Slave Mode Receiving Data from External Peripheral
Table 6-25. Timing Specification for SSP Slave Mode Receiving Data from External Peripheral
6.7 JTAG Boundary Scan Timing Specifications
Table 6-26 shows the AC specifications for the JTAG boundary-scan test-signals. Figure 6-32
shows the timing diagram.
Parameter Description Min Typ Max Units
tSFRM2TXD_output_delay Frame to TX Data Out 10.58 ns
tSCLK2TXD_output_delay Clock to Tx Data Out 10.52 ns
Parameter Description Min Typical Max Units
tSFRM_input_delay Frame to Rx Data Capture 5.21 ns
tSCLK_input_delay Clock to Rx Data Capture 5.04 ns
tRXD_input_delay Rx Data Setup to Capture 4.81 ns
PXA27 processor receiving data
SSPSCLK
(from Peripheral)
SSPRXD
(from Peripheral)
SSPSFRM
(from Peripheral)
PXA27x SSP (Slave Mode receiving data from external peripheral
Data Capture
tSCLK_input_delay
tSFRM_input_delay
tRXD_input_delay
Data Capture
PXA27 processor receiving data
SSPSCLK
(from Peripheral)
SSPRXD
(from Peripheral)
SSPSFRM
(from Peripheral)
PXA27x SSP (Slave Mode receiving data from external peripheral
Data Capture
tSCLK_input_delay
tSFRM_input_delay
tRXD_input_delay
Data Capture
Table 6-26. Boundary Scan Timing Specifications (Sheet 1 of 2)
Symbol Parameter Min Max Units Notes
TBSF TCK Frequency 0.0 33.33 MHz —
TBSCH TCK High Time 15.0 —ns Measured at 1.5 V
TBSCL TCK Low Time 15.0 —ns Measured at 1.5 V
TBSCR TCK Rise Time —5.0 ns 0.8 V to 2.0 V
TBSCF TCK Fall Time —5.0 ns 2.0 V to 0.8 V
6-46 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
AC Timing Specifications
§§
TBSIS1 Input Setup to TCK TDI, TMS 4.0 —ns —
TBSIH1 Input Hold from TCK TDI, TMS 6.0 —ns —
TBSIS2 Input Setup to TCK nTRST 25.0 —ns —
TBSIH2 Input Hold from TCK nTRST 3.0 —ns —
TnTRST Assertion time of nTRST 6 — ms —
TBSOV1 TDO Valid Delay 1.5 6.9 ns Relative to falling edge of TCK
TOF1 TDO Float Delay 1.1 5.4 ns Relative to falling edge of TCK
Figure 6-32. JTAG Boundary-Scan Timing
Table 6-26. Boundary Scan Timing Specifications (Sheet 2 of 2)
Symbol Parameter Min Max Units Notes
Capture-IR
Shift-IR Run-Test/Idle
TOF1
TBSOV1
TBSOV1
TBSOV1
TBSOV1
TBSOV1
TBSOV1
TBSOV1
TBSIH1
TBSIS1
TBSIH1
TBSIS1
TBSIH2TBSIS2
TBSCL
TBSCH
TBSF
TCK
nTRST
TMS
TDI
TDO
Controller State
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Exit1-IR
Update-IR
Test-Logic-Reset
TnTRST
Electrical, Mechanical, and Thermal Specification Glossary-1
Glossary
3G: An industry term used to describe the next, still-to-come generation of wireless applications. It represents a
move from circuit-switched communications (where a device user has to dial in to a network) to broadband,
high-speed, packet-based wireless networks (which are always on). The first generation of wireless
communications relied on analog technology, followed by digital wireless communications. The third generation
expands the digital capabilities by including high-speed connections and increased reliability.
802.11: Wireless specifications developed by the IEEE, outlining the means to manage packet traffic over a
network and ensure that packets do not collide, which could result in the loss of data, when travelling from device
to device.
8PSK: 8 phase shift key modulation scheme. Used in the EDGE standard.
AC ’97 AC-link standard serial interface for modem and audio
ACK: Handshake packet indicating a positive acknowledgment.
Active device: A device that is powered and is not in the suspended state.
Air interface: the RF interface between a mobile cellular handset and the base station
AMPS: Advanced Mobile Phone Service. A term used for analog technologies, the first generation of wireless
technologies.
Analog: Radio signals that are converted into a format that allows them to carry data. Cellular phones and other
wireless devices use analog in geographic areas with insufficient digital networks.
ARM* V5te: An ARM* architecture designation indicating the processor is conforms to ARM* architecture
version 5, including “Thumb” mode and the “El Segundo” DSP extensions.
Asynchronous Data: Data transferred at irregular intervals with relaxed latency requirements.
Asynchronous RA: The incoming data rate, Fs i, and the outgoing data rate, Fs o, of the RA process are
independent (i.e., there is no shared master clock). See also rate adaptation.
Asynchronous SRC: The incoming sample rate, Fsi, and outgoing sample rate, Fso, of the SRC process are
independent (i.e., there is no shared master clock). See also sample rate conversion.
Audio device: A device that sources or sinks sampled analog data.
AW G # : The measurement of a wire’s cross-section, as defined by the American Wire Gauge standard.
Babble: Unexpected bus activity that persists beyond a specified point in a (micro)frame.
Backlight Inverter: A device to drive cold cathode fluorescent lamps used to illuminate LCD panels.
Bandwidth: The amount of data transmitted per unit of time, typically bits per second (b/s) or bytes per second
(B/s). The size of a network “pipe” or channel for communications in wired networks. In wireless, it refers to the
range of available frequencies that carry a signal.
Base Station:The telephone company’s interface to the Mobile Station
Glossary-2 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
BGA: Ball Grid Array
BFSK: binary frequency shift keying. A coding scheme for digital data.
Bit: A unit of information used by digital computers. Represents the smallest piece of addressable memory within a
computer. A bit expresses the choice between two possibilities and is typically represented by a logical one (1) or
zero (0).
Bit Stuffing: Insertion of a “0” bit into a data stream to cause an electrical transition on the data wires, allowing a
PLL to remain locked.
Blackberry: A two-way wireless device (pager) made by Research In Motion (RIM) that allows users to check
e-mail and voice mail translated into text, as well as page other users of a wireless network service. It has a
miniature “qwerty” keyboard that can be used by your thumbs, and uses SMS protocol. A Blackberry user must
subscribe to the proprietary wireless service that allows for data transmission.
Bluetooth: A short-range wireless specification that allows for radio connections between devices within a 30-foot
range of each other. The name comes from 10th-century Danish King Harald Blatand (Bluetooth), who unified
Denmark and Norway.
BPSK: binary phase shift keying. A means of encoding digital data into a signal using phase-modulated
communications.
b/s: Transmission rate expressed in bits per second.
B/s: Transmission rate expressed in bytes per second.
BTB: Branch Target Buffer
BTS: Base Transmitter Station
Buffer: Storage used to compensate for a difference in data rates or time of occurrence of events, when transmitting
data from one device to another.
Bulk Transfer: One of the four USB transfer types. Bulk transfers are non-periodic, large bursty communication
typically used for a transfer that can use any available bandwidth and can also be delayed until bandwidth is
available. See also transfer type.
Bus Enumeration: Detecting and identifying USB devices.
Byte: A data element that is eight bits in size.
Capabilities: Those attributes of a USB device that are administrated by the host.
CAS: Cycle Accurate Simulator
CAS-B4-RAS: See CBR.
CBR: CAS Before RAS. Column Address Strobe Before Row Address Strobe. A fast refresh technique in which
the DRAM keeps track of the next row it needs to refresh, thus simplifying what a system would have to do to
refresh the part.
CDMA: Code Division Multiple Access U.S. wireless carriers Sprint PCD and Verizon use CDMA to allocate
bandwidth for users of digital wireless devices. CDMA distinguishes between multiple transmissions carried
simultaneously on a single wireless signal. It carries the transmissions on that signal, freeing network room for the
Electrical, Mechanical, and Thermal Specification Glossary-3
Intel® PXA270 Processor
Glossary
wireless carrier and providing interference-free calls for the user. Several versions of the standard are still under
development. CDMA should increase network capacity for wireless carriers and improve the quality of wireless
messaging. CDMA is an alternative to GSM.
CDPD: Cellular Digital Packet Data Telecommunications companies can use DCPD to transfer data on unused
cellular networks to other users. IF one section, or “cell” of the network is overtaxed, DCPD automatically allows
for the reallocation of services.
Cellular: Technology that senses analog or digital transmissions from transmitters that have areas of coverage
called cells. As a user of a cellular phone moves between transmitters from one cell to another, the users’ call
travels from transmitter to transmitter uninterrupted.
Circuit Switched: Used by wireless carriers, this method lets a user connect to a network or the Internet by dialing
in, such as with a traditional phone line. Circuit switched connections are typically slower and less reliable than
packet-switched networks, but are currently the primary method of network access for wireless users in the U.S.
CF: Compact Flash memory and I/O card interface
Characteristics: Those qualities of a USB device that are unchangeable; for example, the device class is a device
characteristic.
Client: Software resident on the host that interacts with the USB System Software to arrange data transfer between
a function and the host. The client is often the data provider and consumer for transferred data.
CML: Current mode logic
Configuring Software: Software resident on the host software that is responsible for configuring a USB device.
This may be a system configuration or software specific to the device.
Control Endpoint: A pair of device endpoints with the same endpoint number that are used by a control pipe.
Control endpoints transfer data in both directions and, therefore, use both endpoint directions of a device address
and endpoint number combination. Thus, each control endpoint consumes two endpoint addresses.
Control Pipe: Same as a message pipe.
Control Transfer: One of the four USB transfer types. Control transfers support configuration/command/status
type communications between client and function. See also transfer type.
CRC: See Cyclic Redundancy Check.
CSP: Chip Scale Package.
CTE: Coefficient of thermal expansion
CTI: Computer Telephony Integration.
Cyclic Redundancy Check (CRC): A check performed on data to see if an error has occurred in transmitting,
reading, or writing the data. The result of a CRC is typically stored or transmitted with the checked data. The stored
or transmitted result is compared to a CRC calculated for the data to determine if an error has occurred.
D-cache: Data cache
DECT: the Digital European Cordless Telecommunications standard
Default Address: An address defined by the USB Specification and used by a USB device when it is first powered
or reset. The default address is 00H.
Glossary-4 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
Default Pipe: The message pipe created by the USB System Software to pass control and status information
between the host and a USB device’s endpoint zero.
Device: A logical or physical entity that performs a function. The actual entity described depends on the context of
the reference. At the lowest level, “device” may refer to a single hardware component, as in a memory device. At a
higher level, it may refer to a collection of hardware components that perform a particular function, such as a USB
interface device. At an even higher level, device may refer to the function performed by an entity attached to the
USB; for example, a data/FAX modem device. Devices may be physical, electrical, addressable, and logical. When
used as a non-specific reference, a USB device is either a hub or a function.
Device Address: A seven-bit value representing the address of a device on the USB. The device address is the
default address (00H) when the USB device is first powered or the device is reset. Devices are assigned a unique
device address by the USB System Software.
Device Endpoint: A uniquely addressable portion of a USB device that is the source or sink of information in a
communication flow between the host and device. See also endpoint address.
Device Resources: Resources provided by USB devices, such as buffer space and endpoints. See also Host
Resources and Universal Serial Bus Resources.
Device Software: Software that is responsible for using a USB device. This software may or may not also be
responsible for configuring the device for use.
DMA: Direct Memory Access
Downstream: The direction of data flow from the host or away from the host. A downstream port is the port on a
hub electrically farthest from the host that generates downstream data traffic from the hub. Downstream ports
receive upstream data traffic.
DQPSK: Differential Quadrature Phase Shift Keying a modulation technique used in TDMA.
Driver: When referring to hardware, an I/O pad that drives an external load. When referring to software, a program
responsible for interfacing to a hardware device, that is, a device driver.
DSP: Digital Signal Processing
DSTN Passive LCD Panel.
Dual band mobile phone: A phone that supports both analog and digital technologies by picking up analog signals
when digital signals fade. Most mobile phones are not dual-band.
DWORD: Double word. A data element that is two words (i.e., four bytes or 32 bits) in size.
Dynamic Insertion and Removal: The ability to attach and remove devices while the host is in operation.
E2PROM: See Electrically Erasable Programmable Read Only Memory.
EAV: End of active video
EDGE: Enhanced Data GSM Environment. A faster version of the GSM standard. It is faster because it can carry
messages using broadband networks that employ more bandwidth than standard GSM networks.
EEPROM: See Electrically Erasable Programmable Read Only Memory.
Electrically Erasable Programmable Read Only Memory (EEPROM): Non-volatile re-writable memory
storage technology.
Electrical, Mechanical, and Thermal Specification Glossary-5
Intel® PXA270 Processor
Glossary
End User: The user of a host.
Endpoint: See device endpoint.
Endpoint Address: The combination of an endpoint number and an endpoint direction on a USB device. Each
endpoint address supports data transfer in one direction.
Endpoint Direction: The direction of data transfer on the USB. The direction can be either IN or OUT. IN refers to
transfers to the host; OUT refers to transfers from the host.
Endpoint Number: A four-bit value between 0H and FH, inclusive, associated with an endpoint on a USB device.
Envelope detector: An electronic circuit inside a USB device that monitors the USB data lines and detects certain
voltage related signal characteristics.
EOF: End-of-(micro)Frame.
EOP: End-of-Packet.
EOTD: Enhanced Observed Time Difference
ETM: Embedded Trace Macrocell, the ARM* real-time trace capability
External Port: See port.
Eye pattern: A representation of USB signaling that provides minimum and maximum voltage levels as well as
signal jitter.
FAR: Fault Address Register, part of the ARM* architecture.
False EOP: A spurious, usually noise-induced event that is interpreted by a packet receiver as an EOP.
FDD: The Mobile Station transmits on one frequency; the Base Station transmits on another frequency
FDM: Frequency Division Multiplexing. Each Mobile station transmits on a different frequency (within a cell).
FDMA: Frequency Division Multiple Access. An analog standard that lets multiple users access a group of radio
frequency bands and eliminates interference of message traffic.
FHSS: See Frequency Hopping Spread Spectrum.
FIQ: Fast Interrupt Request. See Interrupt Request.
Frame: A 1 millisecond time base established on full-/low-speed buses.
Frame Pattern: A sequence of frames that exhibit a repeating pattern in the number of samples transmitted per
frame. For a 44.1 kHz audio transfer, the frame pattern could be nine frames containing 44 samples followed by one
frame containing 45 samples.
Frequency Hopping Spread Spectrum: A method by which a carrier spreads out packets of information (voice or
data) over different frequencies. For example, a phone call is carried on several different frequencies so that when
one frequency is lost another picks up the call without breaking the connection.
Fs: See sample rate.
FSR: Fault Status Register, part of the ARM* architecture.
Glossary-6 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
Full-duplex: Computer data transmission occurring in both directions simultaneously.
Full-speed: USB operation at 12 Mb/s. See also low-speed and high-speed.
Function: A USB device that provides a capability to the host, such as an ISDN connection, a digital microphone,
or speakers.
GMSK: Gaussian Minimum Shift Keying. A modulation scheme used in GSM.
GPRS: General Packet Radio Service A technology that sends packets of data across a wireless network at speeds
up to 114 Kbps. Unlike circuit-switched networks, wireless users do not have to dial in to networks to download
information; GPRS wireless devices are “always on” in that they can send and receive data without dial-ins. GPRS
works with GSM.
GPS: Global Positioning Systems
GSM: Global System for Mobile Communications. A standard for how data is coded and transferred through the
wireless spectrum. The European wireless standard, also used in parts of Asia, GSM is an alternative to CDMA.
GSM digitizes and compresses data and sends it across a channel with two other streams of user data. GSM is based
on TDMA technology.
Hamming Distance: The distance (number of bits) between encoded values that can change without causing a
decode into the wrong value.
Handshake Packet: A packet that acknowledges or rejects a specific condition. For examples, see ACK and NAK.
HDML: Handheld Device Markup Language. HDML uses hypertext transfer protocol (HTTP) to display text
versions of web pages on wireless devices. Unlike WML, HDML is not based on XML. HDML does not allow
scripts, while WML uses a variant of JavaScript. Web site developers using HDML must re-code their web pages in
HDML to be viewed on the smaller screen sizes of handheld devices.
HARP: Windows CE standard development platform spec (Hardware Adaptation Reference Platform)
High-bandwidth endpoint: A high-speed device endpoint that transfers more than 1024 bytes and less than 3073
bytes per microframe.
High-speed: USB operation at 480 Mb/s. See also low-speed and full-speed.
Host :The host computer system where the USB Host controller is installed. This includes the host hardware
platform (CPU, bus, and so forth.) and the operating system in use.
Host Controller: The host’s USB interface.
Host Controller Driver (HCD): The USB software layer that abstracts the Host controller hardware. The Host
controller driver provides an SPI for interaction with a Host controller. The Host controller driver hides the
specifics of the Host controller hardware implementation.
Host Resources: Resources provided by the host, such as buffer space and interrupts. See also Device Resources
and Universal Serial Bus Resources.
HSTL: High-speed transceiver logic
Hub: A USB device that provides additional connections to the USB.
Hub Tier: One plus the number of USB links in a communication path between the host and a function.
Electrical, Mechanical, and Thermal Specification Glossary-7
Intel® PXA270 Processor
Glossary
IMMU: Instruction Memory Management Unit, part of the Intel XScale® core.
I-Mode: A Japanese wireless service for transferring packet-based data to handheld devices created by NTT
DoCoMo. I-Mode is based on a compact version of HTML and does not currently use WAP.
I-cache: Instruction cache
IBIS: I/O Buffer Information Specification is a behavioral description of the I/O buffers and package
characteristics of a semiconductor device. IBIS models use a standard format to make it easier to import data into
circuit simulation software packages.
iDEN: Integrated Digital Enhanced Network. A technology that allows users to access phone calls, two-way radio
transmissions, paging and data transmissions from one wireless device. iDEN was developed by Motorola and
based on TDMA.
Interrupt Request (IRQ): A hardware signal that allows a device to request attention from a host. The host
typically invokes an interrupt service routine to handle the condition that caused the request.
Interrupt Transfer: One of the four USB transfer types. Interrupt transfer characteristics are small data,
non-periodic, low-frequency, and bounded-latency. Interrupt transfers are typically used to handle service needs.
See also transfer type.
I/O Request Packet: An identifiable request by a software client to move data between itself (on the host) and an
endpoint of a device in an appropriate direction.
IrDA: Infrared Development Association
IRP: See I/O Request Packet.
IRQ: See Interrupt Request.
ISI: Inter-signal interference. Data ghosting caused when multi-path delay causes previous symbols to interfere
with the one currently being processed.
ISM: Industrial, Scientific, and Medical band. Part of the wireless spectrum that is less regulated, such as 802.11.
Isochronous Data: A stream of data whose timing is implied by its delivery rate.
Isochronous Device: An entity with isochronous endpoints, as defined in the USB Specification, that sources or
sinks sampled analog streams or synchronous data streams.
Isochronous Sink Endpoint : An endpoint that is capable of consuming an isochronous data stream that is sent by
the host.
Isochronous Source Endpoint: An endpoint that is capable of producing an isochronous data stream and sending
it to the host.
Isochronous Transfer: One of the four USB transfer types. Isochronous transfers are used when working with
isochronous data. Isochronous transfers provide periodic, continuous communication between host and device. See
also transfer type.
Jitter: A tendency toward lack of synchronization caused by mechanical or electrical changes. More specifically,
the phase shift of digital pulses over a transmission medium.
kb/s: Transmission rate expressed in kilobits per second. A measurement of bandwidth in the U.S.
Glossary-8 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
kB/s: Transmission rate expressed in kilobytes per second.
Little endian: Method of storing data that places the least significant byte of multiple-byte values at lower storage
addresses. For example, a 16-bit integer stored in little endian format places the least significant byte at the lower
address and the most significant byte at the next address.
LOA: Loss of bus activity characterized by an SOP without a corresponding EOP.
Low-speed: USB operation at 1.5 Mb/s. See also full-speed and high-speed.
LSb: Least significant bit.
LSB: Least significant byte.
LVDS: Low-voltage differential signal
MAC: Multiply Accumulate unit
Mb/s: Transmission rate expressed in megabits per second.
MB/s: Transmission rate expressed in megabytes per second.
MC: Media Center. A combination digital set-top box, video and music jukebox, personal video recorder and an
Internet gateway and firewall that hooks up to a broadband connection.
Message Pipe: A bidirectional pipe that transfers data using a request/data/status paradigm. The data has an
imposed structure that allows requests to be reliably identified and communicated.
Microframe: A 125 microsecond time base established on high-speed buses.
MMC: Multimedia Card - small form factor memory and I/O card
MMX Technology: The Intel® MMX™ technology comprises a set of instructions that are designed to greatly
enhance the performance of advanced media and communications applications. See chapter 10 of the Intel®
Architecture Software Developers Manual, Volume 3: System Programming Guide, Order #245472.
Mobile Station: Cellular Telephone handset
M-PSK: multilevel phase shift keying. A convention for encoding digital data in which there are multiple states.
MMU: Memory Management Unit, part of the Intel XScale® core.
MSb: Most significant bit.
MSB: Most significant byte.
MSL: Mobile Scalable Link.
NAK: Handshake packet indicating a negative acknowledgment.
Non Return to Zero Invert (NRZI): A method of encoding serial data in which ones and zeroes are represented by
opposite and alternating high and low voltages where there is no return to zero (reference) voltage between encoded
bits. Eliminates the need for clock pulses.
NRZI: See Non Return to Zero Invert.
Object: Host software or data structure representing a USB entity.
Electrical, Mechanical, and Thermal Specification Glossary-9
Intel® PXA270 Processor
Glossary
OFDM: See Orthogonal Frequency Division Multiplexing.
Orthogonal Frequency Division Multiplexing: A special form of multi-carrier modulation. In a multi-path
channel, most conventional modulation techniques are sensitive to inter-symbol interference unless the channel
symbol rate is small compared to the delay spread of the channel. OFDM is significantly less sensitive to
inter-symbol interference, because a special set of signals is used to build the composite transmitted signal. The
basic idea is that each bit occupies a frequency-time window that ensures little or no distortion of the waveform. In
practice, it means that bits are transmitted in parallel over a number of frequency-nonselective channels.
Packet: A bundle of data organized in a group for transmission. Packets typically contain three elements: control
information (for example, source, destination, and length), the data to be transferred, and error detection and
correction bits. Packet data is the basis for packet-switched networks, which eliminate the need to dial-in to send or
receive information, because they are “always on.”
Packet Buffer: The logical buffer used by a USB device for sending or receiving a single packet. This determines
the maximum packet size the device can send or receive.
Packet ID (PID): A field in a USB packet that indicates the type of packet, and by inference, the format of the
packet and the type of error detection applied to the packet.
Packet Switched Network: Networks that transfer packets of data.
PCMCIA: Personal Computer Memory Card Interface Association (PC Card)
PCS: Personal Communications services. An alternative to cellular, PCD works like cellular technology because it
sends calls from transmitter to transmitter as a caller moves. But PCS uses its own network, not a cellular network,
and offers fewer “blind spots” than cellular, where calls are not available. PCS transmitters are generally closer
together than their cellular counterparts.
PDA: Personal Digital Assistant. A mobile handheld device that gives users access to text-based information. Users
can synchronize their PDAs with a PC or network; some models support wireless communication to retrieve and
send e-mail and get information from the Internet.
Phase: A token, data, or handshake packet. A transaction has three phases.
Phase Locked Loop (PLL): A circuit that acts as a phase detector to keep an oscillator in phase with an incoming
frequency.
Physical Device: A device that has a physical implementation; for example, speakers, microphones, and CD
players.
PID: See Packet ID or Process ID.
PIO: Programmed input/output
Pipe: A logical abstraction representing the association between an endpoint on a device and software on the host.
A pipe has several attributes; for example, a pipe may transfer data as streams (stream pipe) or messages (message
pipe). See also stream pipe and message pipe.
PLL: See Phase Locked Loop.
PM: Phase Modulation.
Polling: Asking multiple devices, one at a time, if they have any data to transmit.
POR: See Power On Reset.
Glossary-10 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
Port: Point of access to or from a system or circuit. For the USB, the point where a USB device is attached.
Power On Reset (POR): Restoring a storage device, register, or memory to a predetermined state when power is
applied.
Process ID: Process identifier
Programmable Data Rate: Either a fixed data rate (single-frequency endpoints), a limited number of data rates
(32 kHz, 44.1 kHz, 48 kHz, …), or a continuously programmable data rate. The exact programming capabilities of
an endpoint must be reported in the appropriate class-specific endpoint descriptors.
Protocol: A specific set of rules, procedures, or conventions relating to format and timing of data transmission
between two devices.
PSP: Programmable Serial Protocol
PWM: Pulse Width Modulator
QBS: Qualification By Similarity. A technique allowed by JEDEC for part qualification when target parameters are
fully understood and data exist to warrant omitting a specific test.
QAM: quadrature amplitude modulation. A coding scheme for digital data.
QPSK: quadrature phase shift keying. A convention for encoding digital data into a signal using phase-modulated
communications.
RA: See rate adaptation.
Radio Frequency Device: These devices use radio frequencies to transmit data. One typical use is for bar code
scanning of products in a warehouse or distribution center, and sending that information to an ERP database.
Rate Adaptation: The process by which an incoming data stream, sampled at Fs i, is converted to an outgoing data
stream, sampled at Fs o, with a certain loss of quality, determined by the rate adaptation algorithm. Error control
mechanisms are required for the process. Fs i and Fs o can be different and asynchronous. Fs i is the input data rate
of the RA; Fs o is the output data rate of the RA.
Request: A request made to a USB device contained within the data portion of a SETUP packet.
Retire: The action of completing service for a transfer and notifying the appropriate software client of the
completion.
RGBT: Red, Green, Blue, Transparency
ROM: Read Only Memory.
Root Hub: A USB hub directly attached to the Host controller. This hub (tier 1) is attached to the host.
Root Port: The downstream port on a Root Hub.
RTC: Real-Time Clock
SA-1110: StrongARM* based applications processor for handheld products
Intel® StrongARM* SA-1111: Companion chip for the Intel® SA-1110 processor
SAD: Sum of absolute differences
Electrical, Mechanical, and Thermal Specification Glossary-11
Intel® PXA270 Processor
Glossary
Sample: The smallest unit of data on which an endpoint operates; a property of an endpoint.
Sample Rate (Fs): The number of samples per second, expressed in Hertz (Hz).
Sample Rate Conversion (SRC): A dedicated implementation of the RA process for use on sampled analog data
streams. The error control mechanism is replaced by interpolating techniques. Service A procedure provided by a
System Programming Interface (SPI).
Satellite Phone: Phones that connect callers by satellite. Users have a world-wide alternative to terrestrial
connections. Typical use is for isolated users, such as crews of deep-see oil rigs with phones configured to connect
to a satellite service.
SAV: Start of active video
SAW: Surface Acoustic Wave filter
SDRAM: Synchronous Dynamic Random Access Memory.
Service Interval: The period between consecutive requests to a USB endpoint to send or receive data.
Service Jitter: The deviation of service delivery from its scheduled delivery time.
Service Rate: The number of services to a given endpoint per unit time.
SIMD: Single Instruction Multiple Data (a parallel processing architecture).
Smart Phone: A combination of a mobile phone and a PDA, which allow users to communicate as well as perform
tasks; such as, accessing the Internet and storing contacts in a database. Smart phones have a PDA-like screen.
SMROM: Synchronous Mask ROM
SMS: Short Messaging Service. A service through which users can send text-based messages from one device to
another. The message can be up to 160 characters and appears on the screen of the receiving device. SMS works
with GSM networks.
SOC: System On Chip
SOF: See Start-of-Frame.
SOP: Start-of-Packet.
SPI: See System Programming Interface. Also, “Serial Peripheral Interface protocol.
SPI: Serial Peripheral Interface
Split transaction: A transaction type supported by host controllers and hubs. This transaction type allows full- and
low-speed devices to be attached to hubs operating at high-speed.
Spread Spectrum: An encoding technique patented by actress Hedy Lamarr and composer George Antheil, which
broadcasts a signal over a range of frequencies.
SRAM: Static Random Access Memory.
SRC: See Sample Rate Conversion.
SSE: Streaming SIMD Extensions
Glossary-12 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
SSE2: Streaming SIMD Extensions 2: for Intel Architecture machines, 144 new instructions, a 128-bit SIMD
integer arithmetic and 128-bit SIMD double precision floating point instructions, enabling enhanced multimedia
experiences.
SSP: Synchronous Serial Port
SSTL: Stub series terminated logic
Stage: One part of the sequence composing a control transfer; stages include the Setup stage, the Data stage, and
the Status stage.
Start-of-Frame (SOF): The first transaction in each (micro)frame. An SOF allows endpoints to identify the start of
the (micro)frame and synchronize internal endpoint clocks to the host.
Stream Pipe: A pipe that transfers data as a stream of samples with no defined USB structure
SWI: Software interrupt.
Synchronization Type: A classification that characterizes an isochronous endpoint’s capability to connect to other
isochronous endpoints.
Synchronous RA: The incoming data rate, Fsi, and the outgoing data rate, Fso, of the RA process are derived from
the same master clock. There is a fixed relation between Fsi and Fso.
Synchronous SRC: The incoming sample rate, Fsi, and outgoing sample rate, Fso, of the SRC process are derived
from the same master clock. There is a fixed relation between Fsi and Fso.
System Programming Interface (SPI): A defined interface to services provided by system software.
TC: Temperature Cycling
TDD: Time Division Duplexing The Mobile Station and the Base Station transmit on same frequency at different
times.
TDM: See Time Division Multiplexing.
TDMA: Time Division Multiple Access. TDMA protocol allows multiple users to access a single radio frequency
by allocating time slots for use to multiple voice or data calls. TDMA breaks down data transmissions, such as a
phone conversation, into fragments and transmits each fragment in a short burst, assigning each fragment a time
slot. With a cell phone, the caller would not detect this fragmentation. TDMA works with GSM and digital cellular
services.
TDR: See Time Domain Reflectometer.
Termination: Passive components attached at the end of cables to prevent signals from being reflected or echoed.
TFT: Thin Film Twist, a type of active LCD panel.
Three-state: a high-impedance state in which the output is floating and is electrically isolated from the buffer's
circuitry.
Time Division Multiplexing (TDM): A method of transmitting multiple signals (data, voice, and/or video)
simultaneously over one communications medium by interleaving a piece of each signal one after another.
Time Domain Reflectometer (TDR): An instrument capable of measuring impedance characteristics of the USB
signal lines.
Electrical, Mechanical, and Thermal Specification Glossary-13
Intel® PXA270 Processor
Glossary
Time-out: The detection of a lack of bus activity for some predetermined interval.
Token Packet: A type of packet that identifies what transaction is to be performed on the bus.
TPV: Third Party Vendor
Transaction: The delivery of service to an endpoint; consists of a token packet, optional data packet, and optional
handshake packet. Specific packets are allowed/required based on the transaction type.
Transaction translator: A functional component of a USB hub. The Transaction Translator responds to special
high-speed transactions and translates them to full/low-speed transactions with full/low-speed devices attached on
downstream facing ports.
Transfer: One or more bus transactions to move information between a software client and its function.
Transfer Type: Determines the characteristics of the data flow between a software client and its function. Four
standard transfer types are defined: control, interrupt, bulk, and isochronous.
TS: Thermal Shock
Turn-around Time: The time a device needs to wait to begin transmitting a packet after a packet has been received
to prevent collisions on the USB. This time is based on the length and propagation delay characteristics of the cable
and the location of the transmitting device in relation to other devices on the USB.
UART: Universal Asynchronous Receiver/Transmitter serial port
Universal Serial Bus Driver (USBD): The host resident software entity responsible for providing common
services to clients that are manipulating one or more functions on one or more Host controllers.
Universal Serial Bus Resources: Resources provided by the USB, such as bandwidth and power. See also Device
Resources and Host Resources.
Upstream: The direction of data flow towards the host. An upstream port is the port on a device electrically closest
to the host that generates upstream data traffic from the hub. Upstream ports receive downstream data traffic.
USBD: See Universal Serial Bus Driver.
USB-IF: USB Implementers Forum, Inc. is a nonprofit corporation formed to facilitate the development of USB
compliant products and promote the technology.
VBI: Vertical Blanking Interval, also known as the “backporch”.
Virtual Device: A device that is represented by a software interface layer. An example of a virtual device is a hard
disk with its associated device driver and client software that makes it able to reproduce an audio.WAV file.
VLIO: Variable Latency Input/Output interface.
YUV: A method of characterizing video signals typically used in digital cameras and PAL television specifying
luminance and chrominance.
WA P : Wireless Application Protocol. WAP is a set of protocols that lets users of mobile phones and other digital
wireless devices access Internet content, check voice mail and e-mail, receive text of faxes and conduct
transactions. WAP works with multiple standards, including CDMA and GSM. Not all mobile devices support
WAP.
Glossary-14 Electrical, Mechanical, and Thermal Specification
Intel® PXA270 Processor
Glossary
W-CDMA: Wideband CDMA, a third generation wireless technology under development that allows for
high-speed, high-quality data transmission. Derived from CDMA, W-CDMA digitizes and transmits wireless data
over a broad range of frequencies. It requires more bandwidth than CDMA, but offers faster transmission because it
optimizes the use of multiple wireless signals, instead of one, as does CDMA.
Wireless LAN: A wireless LAN uses radio frequency technology to transmit network messages through the air for
relatively short distances, like across an office building or a college campus. A wireless LAN can serve as a
replacement for, or an extension to, a traditional wired LAN.
Wireless Spectrum: A band of frequencies where wireless signals travel carrying voice and data information.
Word: A data element that is four bytes (32 bits) in size.
WML: Wireless Markup Language, a version of HDML is based on XML. Wireless applications developers use
WML to re-target content for wireless devices.
§§
Intel® PXA270 Processor Index-1
Index
A
About This Document ........................................................1
AC Timing Specifications ..................................................1
AC Test Load Specifications .....................................1
GPIO Timing Specifications ....................................11
JTAG Boundary Scan Timing Specifications ..........45
LCD Timing Specifications .....................................43
Memory and Expansion-Card Timing Specifications 12
Flash Memory Parameters and
Timing Diagrams .............................23
SRAM Parameters and Timing Diagrams .......33
Variable-Latency I/O Parameters and
Timing Diagrams .............................36
Reset and Power Manager Timing Specifications .....2
Deep-Sleep Mode Timing ..................................7
Frequency-Change Timing ..............................10
GPIO Reset Timing ............................................5
Hardware Reset Timing .....................................4
Idle-Mode Timing ............................................10
Sleep Mode Timing ............................................6
Standby-Mode Timing .....................................10
Voltage-Change Timing ...................................11
Watchdog Reset Timing ....................................5
SSP Timing Specifications ......................................44
Applicable Documents .......................................................2
E
Electrical Specifications .....................................................1
Absolute Maximum Ratings ......................................1
CLK_PIO and CLK_TOUT Specifications .............12
DC Specification ........................................................8
Operating Conditions .................................................1
Oscillator Electrical Specifications ............................9
Oscillator Electrical Specs
13.000-MHz Oscillator Specifications .............11
32.768-kHz Oscillator Specifications ................9
Power-Consumption Specifications ...........................6
Expansion-Card Interface Parameters and Timing Diagrams
40
F
Flash Memory Read Parameters and Timing Diagrams ..23
Flash Memory Write Parameters and Timing Diagrams .30
Functional Overview ..........................................................1
G
GPIO states in Deep-Sleep mode ...................................... 9
I
Internal SRAM Read/Write Timing Specifications ......... 12
Introduction ....................................................................... 1
About This Document ............................................... 1
Applicable Documents .............................................. 2
Number Representation ............................................. 1
Typographical Conventions ....................................... 1
J
Junction To Case Temperature Thermal Resistance ......... 7
N
Number Representation ..................................................... 1
P
Package Information .......................................................... 1
Pinlist ................................................................................. 1
Power-On Timing Specifications ...................................... 2
Processor Markings ........................................................... 7
Processor Materials ............................................................ 6
R
ROM Parameters and Timing Diagrams ......................... 18
S
SDRAM Parameters and Timing Diagrams .................... 12
SRAM Read Parameters and Timing Diagrams .............. 33
SRAM Write Parameters and Timing Diagrams ............. 33
T
Tray Drawing ..................................................................... 8
Typographical Conventions ............................................... 1
V
Variable Latency I/O Read Timing ................................. 37
Variable-Latency I/O Write Timing ................................ 38
Index-2 Intel® PXA270 Processor
