ISL7457SRHQF - Intersil Corporation

FN6874.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL7457SRH

Radiation Hardened, SEE Hardened,

Non-Inverting, Quad CMOS Driver

The ISL7457SRH is a radiation hardened, SEE hardened,

high speed, non-inverting, quad CMOS driver. It is capable

of running at clock rates up to 40MHz and features 2A

typical peak drive capability and a nominal on-resistance of

just 3.5Ω. The ISL7457SRH is ideal for driving highly

capacitive loads, such as storage and vertical clocks in CCD

applications. It is also well suited to level-shifting and

clock-driving applications.

Each output of the ISL7457SRH can be switched to either

the high (VH) or low (VL) supply pins, depending on the

related input pin. The inputs are compatible with both 3.3V

and 5V CMOS logic. The output enable (OE) pin can be

used to put the outputs into a high-impedance state. This is

especially useful in CCD appl ications, where the driver

should be disabled during power down.

The ISL7457SRH also fe atures very fast rise and fall times

which are typically matched to within 1n s. The propagation

delay is also matched betwee n rising and falling edges to

typically within 1.5ns.

The ISL7457SRH is available in a 16 lead ceramic flatpack

package and specified for operation over the full -55°C to

+125°C ambient temperature range .

Specifications for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

Detailed Electrical Specifications for these devices are

contained in SMD 5962-08230. A “hot-link” is provided

on our website for downloading.

Pinouts

Features

• Electrically Screened to SMD 5962-08230

• QML Qualified pe r MIL-PRF-38535 Requirements

• Full Mil-temp Range Operation . . . .TA = -55°C to +125°C

• Radiation Hardness

- TID [50-300 rad(Si)/s]. . . . . . . . . . . . . . . 10krad(Si) min

• SEE Hardness

- LET (SEL and SEB Immunity) . . . . 40MeV/mg/cm2 min

- LET [SET = ΔVOUT < 15V, Δt < 500ns] 40MeV/mg/cm2

min

• 4 Channels

• Clocking Speeds up to 40MH z

• 11ns/12ns Typical tR/tF with 1nF Load (15V bias)

• 1ns Typical Rise and Fal l Time Match (15V bias)

• 1.5ns Typical Prop Delay Match (15V bias)

• Low Quiescent Current - < 1mA Typical

• Fast Output Enable Function - 12ns T y pical (15V bias)

• Wide Output Voltage Range

-0V ≤ VL ≤ 8V

-2.5V ≤ VH ≤ 16.5V

• 2A Typical Peak Drive Current (15V Bias)

•3.5Ω Typical On-Resistance (15V bias)

• Input Level Shifters

• 3.3V/5V CMOS Compatible Inputs

Applications

• CCD Drivers, Clock/line Drivers, Level-Shifters

ISL7457SRH

16 LD FLATPACK

TOP VIEW

INA

INB

GND

INC

IND

116

VS+

OUTA

OUTB

OUTC

OUTD

VS-

Data Sheet March 16, 2009

2FN6874.0

March 16, 2009

Ordering Information

ORDERING

NUMBER PART

NUMBER

TEMP.

RANGE

(°C) PACKAGE PKG.

DWG. #

5962D0823001QXC ISL7457SRHQF -5 5 t o + 1 2 5 16 L d Fl a t p a c k K1 6 .A

5962D0823001VXC ISL7457SRHVF -5 5 t o + 1 2 5 16 Ld F l a t p a c k K1 6 .A

5962D0823001V9A ISL7457SRHVX -5 5 t o + 1 2 5 Di e

ISL7457SRHF/PROTO ISL7457SRHF/PROTO -5 5 t o + 1 2 5 16 Ld F l a t p a c k K1 6 .A

ISL7457SRHX/SAMPLE ISL7457SRHX/SAMPLE -5 5 t o + 1 2 5 Di e

ISL7457SRH

3FN6874.0

March 16, 2009

Electrical Specifications Typical values reflect VS+ = VH = 5V, VS- = VL= 0V, OE = VS+, TA = +25°C unless otherwise specified.

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

VIH Logic “1” Input Voltage 1.3 V

IIH Logic “1” Input Current INx = VS+0.1µA

VIL Logic “0” Input Voltage 1.23 V

IIL Logic “0” Input Current INx = 0V 0.1 µA

CIN Input Capacitance 5.7 pF

RIN Input Resistance 50 MΩ

OUTPUT

ROH ON Resistance VH to OUTx INx = VS+, IOUTx = -100mA 8 Ω

ROL ON Resistance VL to OUTx INx = 0V, IOUTx = +100mA 6 Ω

ILEAK+ Positive Output Leakage Current INx = VS+, OE = 0V, OUTx = VS+0.1µA

ILEAK- Negative Output Leakage Current INx = VS+, OE = 0V, OUTx = VS-0.1µA

POWER SUPPLY

IS+ VS+ Supply Current INx = 0V and VS+0.2mA

IS- VS- Supply Current INx = 0V and VS+-0.2mA

IHVH Supply Current INx = 0V and VS+0.1µA

ILVL Supply Current INx = 0V and VS+0.1µA

SWITCHING CHARACTERISTICS

tRRise Time INx = 0V to 4.5V step, CL = 1nF 23 ns

tFFall Time INx = 4.5V to 0V step, CL = 1nF 20 ns

tRFΔtR, tF Mismatch CL = 1nF 3 ns

tD+ Turn-On Delay Time INx = 0V to 4.5V step, CL = 1nF 20 ns

tD- Turn-Off Delay Time INx = 4.5V to 0V step, CL = 1nF 22 ns

tDD tD+, tD- Mismatch CL = 1nF 2 ns

tENABLE Enable Delay Time INx = VS+, OE = 0V to 4.5V step, RL = 1kΩ21 ns

tDISABLE Disable Delay Time INx = VS+, OE = 4.5V to 0V step, RL = 1kΩ46 ns

ISL7457SRH

4FN6874.0

March 16, 2009

Electrical Specifications Typical values reflect VS+ = VH = 15V, VS- = VL= 0V, OE = VS+, TA = +25°C unless otherwise specified.

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

VIH Logic “1” Input Voltage 1.63 V

IIH Logic “1” Input Current INx = VS+0.1µA

VIL Logic “0” Input Voltage 1.4 V

IIL Logic “0” Input Current INx = 0V 0.1 µA

CIN Input Capacitance 5.7 pF

RIN Input Resistance 50 MΩ

OUTPUT

ROH ON Resistance VH to OUTx INx = VS+, IOUTx = -100mA 3.5 Ω

ROL ON Resistance VL to OUTx INx = 0V, IOUTx = +100mA 3 Ω

ILEAK+ Positive Output Leakage Current INx = VS+, OE = 0V, OUTx = VS+0.1µA

ILEAK- Negative Output Leakage Current INx = VS+, OE = 0V, OUTx = VS-0.1µA

POWER SUPPLY

IS+ VS+ Supply Current INx = 0V and VS+0.8mA

IS- VS- Supply Current INx = 0V and VS+-0.8mA

IHVH Supply Current INx = 0V and VS+0.1µA

ILVL Supply Current INx = 0V and VS+0.1µA

SWITCHING CHARACTERISTICS

tRRise Time INx = 0V to 5V step, CL = 1nF 11 ns

tFFall Time INx = 5V to 0V step, CL = 1nF 12 ns

tRFΔtR, tF Mismatch CL = 1nF 1 ns

tD+ Turn-On Delay Time INx = 0V to 5V step, CL = 1nF 11.5 ns

tD- Turn-Off Delay Time INx = 5V to 0V step, CL = 1nF 13 ns

tDD tD+, tD- Mismatch CL = 1nF 1.5 ns

tENABLE Enable Delay Time INx = VS+, OE = 0V to 5V step, RL = 1kΩ12 ns

tDISABLE Disable Delay Time INx = VS+, OE = 5V to 0V step, RL = 1kΩ27 ns

ISL7457SRH

5FN6874.0

March 16, 2009

Typical Performance Curves (Pre-rad)

FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

FIGURE 3. “ON” RESISTANCE vs SUPPLY VOLTAGE FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE

FIGURE 5. RISE/FALL TIME vs TEMPERATURE FIGURE 6. PROPAGATION DELAY TIME vs SUPPLY VOLTAGE

TA = +25°C HIGH LIMIT = 2.4V

LOW LIMIT = 0.8V

HYSTERESIS

1.8

1.6

1.4

1.2

1.0

5.0 7.0 10 12 15

SUPPLY VOLTAGE (V)

INPUT VOLTAGE (V)

TA = +25°C

ALL INPUTS = 0V

ALL INPUTS = VS+

2.0

1.6

1.2

0.8

05 7 10 12 15

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0.4

IOUT = 100mA

TA = +25°C

VL TO OUT

25 7 10 12 15

SUPPLY VOLTAGE (V)

“ON” RESISTANCE (Ω)

VH TO OUT

CL = 1nF

TA = +25°C

55 7 10 12 15

SUPPLY VOLTAGE (V)

RISE/FALL TIME (ns)

CL = 1nF

VS+ = 15V

-50 0 50 100 125

TEMPERATURE (°C)

RISE/FALL TIME (ns)

25 75-25

5.051015

SUPPLY VOLTAGE (V)

PROPAGATION DELAY TIME (ns)

127

tD-

tD+

CL = 1nF

TA = +25°C

ISL7457SRH

6FN6874.0

March 16, 2009

FIGURE 7. PROPAGATION DELAY TIME vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE

FIGURE 9. SUPPLY CURRENT PER CHANNEL vs LOAD

CAPACITANCE FIGURE 10. OPERA TING FREQUENCY vs LOAD

CAPACITANCE DERATING CURVES

Typical Performance Curves (Pre-rad) (Continued)

CL = 1nF

VS+ = 15V

-50 0 50 100 125

TEMPERATURE (°C)

PROPAGATION DELAY TIME (ns)

25 75-25

tD-

tD+

140

120

100

100 1k 4.7k 10k

LOAD CAPACITANCE (pF)

RISE/FALL TIME (ns)

tFtR

2.2k470

VS+ = 15V

TA = +25°C

VS+ = VH = 10V

VS- = VL = 0V

f = 100kHz

100 1k 10k

LOAD CAPACITANCE (pF)

SUPPLY CURRENT (mA)

TA = +25°C

VS+ = 15V

0 400 800 1000

LOAD CAPACITANCE (pF)

600200

OPERATING FREQUENCY (MHz)

TJ = +150°C

TJ = +125°C

ISL7457SRH

7FN6874.0

March 16, 2009

Timing Diagram

Standard Test Configuration

TABLE 1. OPERATING VOLTAGE RANGE

PIN MIN MAX

VS+ to VS- 4.5V 16.5V

VS- to GND 0V 0V

VHVS- + 2.5V VS+

VLVS-V

S+

VH to VL0V 16.5V

VL to VS-0V 8V

90%

10%

OUTPUT

2.5V

INPUT

tD+

tD-

8 9

4.7µF 0.1µF

INA

INB

INC

IND

10kΩ

VS+

OUTD

OUTC

OUTB

OUTA

VS+

1nF

0.1µF 4.7µF

1nF

0.1µF 4.7µF

ISL7457SRH

8FN6874.0

March 16, 2009

Block Diagram

Pin Descriptions

16 LD

FLATPACK NAME FUNCTION EQUIVALENT CIRCUIT

1 INA Input Channel A

CIRCUIT 1

2 OE Output enable (Reference Circuit 1)

3 INB Input Channel B (Reference Circuit 1)

LLow voltage input pin

5 GND Input logic ground

6, 13 NC No connection

7 INC Input Channel C (Reference Circuit 1)

8 IND Input Channel D (Reference Circuit 1)

S- Negative supply voltage

10 OUTD Output Channel D

CIRCUIT 2

11 OUTC Output Channel C (Reference Circuit 2)

12 VHHigh voltage input pin

14 OUTB Output Channel B (Reference Circuit 2)

15 OUTA Output Channel A (Reference Circuit 2)

16 VS+ Positive supply voltage

VS-VS-

VS+

INx

VS-

VS+

OUTx

VS-

3-STATE

CONTROL

LEVEL

SHIFTER OUTx

INx

VS+

GND

VS-

ISL7457SRH

9FN6874.0

March 16, 2009

Application Information

Product Descr iption

The ISL7457SRH is a high performance, high speed quad

CMOS driver. Each channel of the ISL7457SRH consists of

a single P-channel high side driver and a single N-Channel

low side driver. These 3.5Ω devices will pull the output

(OUTx) to either the high or low voltage, on VH and VL

respectively, depending on the input logic sign al (INx). It

should be noted that there is only on e set of high and low

voltage pins.

A common output enable (OE) pin is available on the

ISL7457SRH. When this pin is pulled low, it will put all

outputs in a high impedance state.

Supply Voltage Range and Input Compatibility

The ISL7457SRH is designed to operate on nominal 5V to

15V supplies with ±10% tolerance. Table 1 on page 7 shows

the specifications for the relationship between the VS+, VS-,

VH, VL, and GND pins. The ISL7457SRH does not contain a

true analog switch and therefore VL should always be less

than VH.

All input pins are compatible with both 3.3V and 5V CMOS

signals.

PCB Layout Guidelines

1. A ground plane must be used, preferably located on layer

#2 of the PCB.

2. Connect the GND and VS- pi ns directly to the ground

plane.

2. The VS+, VH and VL pins should be bypassed directly to

the ground plane using a low-ESR, 4.7µF solid tantalum

capacitor in parallel with a 0.1µF ceramic capacitor. Locate

all bypass capacitors as close as possible to the respective

pins of the IC.

3. Keep all input and output connections to the IC as short as

possible.

4. For high frequency operation above 1MHz, consider use

of controlled impedance traces terminated into 50Ω on all

inputs and outputs.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads, the

ISL7457SRH drive capability is limited by the rise in die

temperature brought about by internal power dissipation. For

reliable operation die temperature must be kept below

TJMAX (+150°C).

Power dissipation may be calculated as shown in

Equation 1:

where:

PD is the power dissipated in the device.

VS is the total power supply to the ISL7457SRH (from VS+

to VS-).

IS is the quiescent supply current.

CINT is the internal load capacitance (80pF max).

f is the operating frequency.

CL is the load capacitance.

VOUT is the swing on the ou tp ut (VH - VL).

Junction Temperature Calculation

Once the power dissipation for the application is determined,

the maximum junction temperature can be calculated as

shown in Equation 2:

where:

TJMAX is the maximum operating junction temperature

(150°C).

TSMAX is the maximum operating sink temperature of the

PCB.

θJC is the thermal resistance, junction-to-case, of the

package.

θCS is the thermal resistance, case-to-sink, of the PCB.

PD is the power dissipation calculated in Equation 1.

PCB Thermal Management

To minimize the case-to-sink thermal resistance, it is

recommended that multiple vias be placed on the top layer

of the PCB directly underneath the IC. The vias should be

connected to the ground plane, which functions as a

heatsink. A gap filler material (i.e. a Sil-Pad or thermally

conductive epoxy) may be used to insure good thermal

contact between the bottom of the IC and the vias.

PDVSIS

×()CINT VS

×f×()CLVOUT

×f×()+

∑

+= (EQ. 1)

TJMAX TSMAX Θ( JC ΘCS)PD

×++=(EQ. 2)

ISL7457SRH

10 FN6874.0

March 16, 2009

Die Characteristics

DIE DIMENSIONS:

2390 µm x 2445 µm (94.1 mils x 96.3 mils)

Thickness:13.0 mils ±0.5 mil

INTERFACE MATERIALS

Glassivation

Type: PSG and Silicon Nitride

Thickness: 0.5 µm ± 0.05 µm to 0.7 µm +/- 0.05 µm

Top Metallization

Type: AlCuSi (1%/0 .5%)

Thickness: 1.0 µm +/-0.1 µm

Substrate:

Type: Silicon

Isolation: Junction

Backside Finish:

Silicon

ASSEMBLY RELATED INFORMATION

Substrate Potential:

Vs-

ADDITIONAL INFORMATION

Worst Case Current Density:

< 2 x 105 A/cm2 (See Figure 10)

Transistor Count:

1142

Metallization Mask Layout ISL7457SRH

INA

INB

GND

INC

VS-

OUTD

OUTC

OUTB

OUTA

IND

VS+

DELAY

ISL7457SRH

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third pa rties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6874.0

March 16, 2009

ISL7457SRH

Layout Characteristics

Step and Repeat: 2390 µm x 2445 µm

The DELAY pad is not bonded.

TABLE 1. LAYOUT X-Y COORDINATES

PAD NAME X

(µm) Y

(µm) DX

(µm) DY

(µm) PROBES

PER PAD

IND 675 190 140 140 1

VS- 995 190 140 140 1

OUTD 2118 490 122 133 1

OUTC 2118 795 122 133 1

VH2118 1039 122 345 2

2118 1211

OUTB 2118 1554 122 133 1

OUTA 2118 1861 122 133 1

VS+ 1015 2140 140 140 1

INA 608 2140 140 140 1

OE 213 1993 140 140 1

INB 213 1673 140 140 1

VL213 1331 140 345 2

213 1159

GND 213 864 140 140 1

DELAY 213 585 140 140 0

INC 213 213 140 140 1

12 FN6874.0

March 16, 2009

ISL7457SRH

Ceramic Metal Seal Flatpack Packages (Flatpack)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark. Alternately, a tab (dimension k)

may be used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the lim-

its of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass

overrun.

4. Dimensions b1 and c1 apply to lead base metal only . Dimension

M applies to lead plating and finish thickness. The maximum lim-

its of lead dimensions b and c or M shall be measured at the cen-

troid of the finished lead surfaces, when solder dip or tin plate

lead finish is applied.

5. N is the maximum number of terminal positions.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead packages, no organic or polymeric mate-

rials shall be molded to the bottom of the package to cover the

leads.

8. Dimension Q shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension Q minimum

shall be reduced by 0.0015 inch (0.038mm) maximum when sol-

der dip lead finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH

-D-

-C-

0.004 H A - B

S S

-A- -B-

0.036 H A - B

S S

SEATING AND

LE2

E3 E3

BASE PLANE

-H-

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

PIN NO. 1

ID AREA

K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B)

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.045 0.115 1.14 2.92 -

b 0.015 0.022 0.38 0.56 -

b1 0.015 0.019 0.38 0.48 -

c 0.004 0.009 0.10 0.23 -

c1 0.004 0.006 0.10 0.15 -

D - 0.440 - 11.18 3

E 0.245 0.285 6.22 7.24 -

E1 -0.315-8.003

E2 0.130 - 3.30 - -

E3 0.030 - 0.76 - 7

e 0.050 BSC 1.27 BSC -

k 0.008 0.015 0.20 0.38 2

L 0.250 0.370 6.35 9.40 -

Q 0.026 0.045 0.66 1.14 8

S1 0.005 - 0.13 - 6

M - 0.0015 - 0.04 -

N16 16-

Rev. 1 2-20-95