NanoAmp Solutions, Inc. 670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035 ph: 408-935-7777, FAX: 408-935-7770 www.nanoamp.com N16D1633LPA Advance Information 512K x 16 Bits x 2 Banks Low Power Synchronous DRAM DESCRIPTION These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Features * Auto refresh and self refresh. * All inputs and outputs referenced to the positive edge of the system clock. * All pins are compatible with LVTTL interface. * Data mask function by DQM. * 4K refresh cycle / 64ms. * Internal dual banks operation. * Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. * Burst Read Single Write operation. * JEDEC standard 3.0V/3.3V power supply. * Programmable CAS Latency : 2,3 clocks. * Special Function Support. -PASR (Partial Array Self Refresh) -Auto TCSR(Temperature Compensated Self Refresh) * Programmable Driver Strength Control. - Full Strength or 1/2, 1/4 of Full Strength * Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge * Deep Power Down Mode Table 1: Ordering Information PART NO. N16D1633LPAZ2-75I CLOCK Freq. Temperature VDD/VDDQ INTERLEAVE 133MHz N16D1633LPAZ2-10I 100MHz N16D1633LPAC2-60I 166MHz N16D1633LPAC2-75I 133MHz N16D1633LPAC2-10I 100MHz N16D1633LPAT2-60I 166MHz N16D1633LPAT2-75I 133MHz N16D1633LPAT2-10I 100MHz PACKAGE 48-Ball Green FBGA -25o C to 85o C 3.0V/3.0V or 3.3V/3.3V LVTTL 60-Ball Green WBGA 50-Pin Green TSOP II Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 1 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 1: Package Configuration (60-Ball WBGA) 6.4 0.1 3.9 1.25 1 2 3 4 5 6 0.65 7 A VSS DQ15 DQ0 VDD B DQ14 VSSQ VDDQ DQ1 C DQ13 VDDQ VSSQ DQ2 D DQ12 DQ11 DQ4 DQ3 E DQ10 VSSQ VDDQ DQ5 E F DQ9 VDDQ VSSQ DQ6 F G DQ8 NC NC DQ7 G H NC NC NC NC H J NC UDQM LDQM /WE J K NC CLK /RAS /CAS L CKE NC NC /CS M A11 A9 NC NC N A8 A7 A0 A10 P A6 A5 A2 A1 R VSS A4 A3 VDD Unit [mm] 0.65 A B C D 10.1 0.1 9.1 K L M N P R 0.3 0.05 7 6 5 4 3 2 [Top View] 1 1.0max 0.23 0.05 [Bottom View] Note: 1. All Dimensions in millimeters Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 2 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 2: Package Configuration (48-Ball FBGA) 6.0 0.1 1.125 3.75 Unit [mm] 0.75 4 5 6 A CLK /CS A0 A1 A2 /CAS B DQ8 NC A3 A4 CKE DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 /RAS A7 DQ3 VDDQ E VDD DQ12 NC NC DQ4 VSSQ F DQ14 DQ13 NC NC DQ5 DQ6 G DQ15 NC UDQM LDQM /WE DQ7 H NC A8 A9 A10 A11 NC A B C D 5.25 3 E F G 0.30 0.05 H 6 5 4 3 2 1 1.0max [Top View] 8 0.1 2 0.75 1 0.23 0.05 [Bottom View] Note: 1. All Dimensions in millimeters Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 3 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 3: Package Configuration (50-Pin TSOP II) 11.76 0.20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 Pin TSOP II 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND DQ15 DQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND 0.80 BSC 20.95 0.10 VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM /WE /CAS /RAS /CS A11 A10 A0 A1 A2 A3 VDD 0.49 0.27 1.03 MAX [Top View] 10.16 0.10 0.80 NOM 1.20 MAX 1.00 0.05 0.17 NOM 0o - 8o 0.15 0.05 0.50 0.10 NOTES: 1. All dimensions in millimeters unless otherwise noted 2. BSC = Basic lead spacing between centers 3. MAX / MIN Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 4 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 2: Pin Descriptions PIN PIN NAME DESCRIPTIONS CLK System Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of the CLK CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. /CS Chip Select A11 A0~A10 Bank Address Address Enable or disable all inputs except CLK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0~RA10 Column Address: CA0~CA7 Auto Precharge : A10 /RAS, /CAS, /WE Row Address Strobe, Column Address Strobe, Write Enable /RAS, /CAS and /WE define the operation Refer function truth table for details LDQM/UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection Multiplexed data input/output pin Power supply for internal circuits and input buffers Power Supply for output buffers No Connection Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 5 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 4: Functional Block Diagram EXTENDED MODE REGISTER CLK CLOCK CKE GENERATOR TCSR PASR ADDRESS ROW DECODER ROW DECODER ROW MODE REGISTER ADDRESS BUFFER & REFRESH COUNTER BANK B BANK A SENSE AMPLIFIER /CAS /WE CONTROL LOGIC /RAS COMMAND DECODER /CS COLUMN DECODER & LATCH CIRCUIT COLUMN ADDRESS BUFFER & BURST COUNTER DATA CONTROL CIRCUIT DQM LATCH CIRCUIT INPUT & OUTPUT BUFFER DQ Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 6 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 5: Simplified State Diagram EXTENDED SELF MODE REGISTER EM R SET REFRESH S LF SE SE LF MRS MODE CBR REF IDLE REGISTER IT EX REFRESH SET CK E D DP EX D DP POWER IT ACT DEEP CK E POWER DOWN DOWN CKE ROW DOWN W AU RIT TO E PR WIT EC H HA RG E READ WRITE READ CKE READ WRITE CKE CKE CKE CKE ON PRECHARGE READ A SUSPEND erm et n) atio min ter POWER CKE ina t ge har rec E(P PR CKE READ A ion ) WRITE A READ SUSPEND PR E(P rec har g WRITE A SUSPEND CKE E RG HA EC PR H IT TO AU ITE W WR PRE WRITE SUSPEND POWER BS T T BS WRITE ACTIVE CKE ACTIVE PRECHARGE Automatic Sequence Manual Input Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 7 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 6: Mode Register Definition A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 11 0 10 9 8 WB 0 0 7 6 5 4 CAS Latency 0 3 BT 2 1 0 Mode Register (Mx) Burst Length M9 Write Burst Mode M6 M5 M4 CAS Latency M3 Burst Type 0 Burst Read and Burst Write 0 0 0 Reserved 0 Sequential 1 Burst Read and Single Write 0 0 1 1 1 Interleave 0 1 0 0 1 1 0 1 Burst Length M2 M1 M0 0 0 0 1 1 2 0 0 1 2 2 1 3 0 1 0 4 4 0 Reserved 0 1 1 8 8 0 1 Reserved 1 0 0 Reserved Reserved 1 1 0 Reserved 1 0 1 Reserved Reserved 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved M3 = 0 M3 = 1 Note: M11(A11) must be sest to "0" to select mode Register (vs. the Extend Mode Register) Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 3 . Starting Column Address A2 A1 Full Page A0 Sequential Interleave 0-1 0 0-1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn+1. Cn+2, Cn+3, Cn+4... ...Cn-1, Cn... Not Supported 4 8 Order of Access Within a Burst 1 2 N=A0~7 (Location 0-256) 1. For full-page accesses: y = 256 2. For a burst length of two, A1-A7 select the block-oftwo burst; A0 selects the starting column within the block. Table 3: Burst Definition Burst Length Note : 3. For a burst length of four, A2-A7 select the block-offour burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 select the block-ofeight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0A7 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 8 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 7: Extended Mode Register A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 11 1 10 0 9 0 E6 E5 Driver Strength 0 0 Full Strength 0 1 1/2 Strength 1 0 1/4 Strength 1 1 Reserved 8 0 7 6 0 5 DS E4 4 3 2 TCSR E3 1 PASR 0 Extended Mode Register (Ex) Maximum Case Temp. 0 0 85 0 1 70 1 0 45 1 1 Auto E2 E1 E0 0 0 0 All Banks 0 0 1 One Bank (A11=0) 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Half of One Bank (A11=0, Row Address MSB=0) 1 1 0 Quarter of One Bank (A11=0, Row Address 2 MSB=0) 1 1 1 Reserved Self Refresh Coverage Note: 1. E11(A11) must be set to "1" to select Extend Mode Register (vs. the base Mode Register) Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 9 N16D1633LPA NanoAmp Solutions, Inc. Advance Information FUNCTIONAL DESCRIPTION In general, this 16Mb SDRAM (512K x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 8,388,608bit banks is organized as 2,048 rows by 256 columns by 16-bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (A11 select the bank, A0-A10 select the row). The address bits (A11 select the bank, A0-A7 select the column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Power up and Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command has been issued. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation. REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 should be set to zero. M11 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. EXTENDED MODE REGISTER The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed via the Mode Register Set command (A11=1) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with E7 through E10 set to "0". The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 10 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating /CS, /RAS and deasserting /CAS, /WE at the positive edge of the clock. The value on the A11 selects the bank, and the value on the A0-A10 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating /CS, /CAS, and deasserting /WE, /RAS at the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating /CS, /CAS, /WE and deasserting /RAS at the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 11 N16D1633LPA NanoAmp Solutions, Inc. Advance Information CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 8: CAS Latency T0 T1 T3 T2 CLK READ COMMAND NOP NOP tOH tLZ DQ Dout tAC CAS Latency=2 T0 T1 T3 T2 T4 CLK COMMAND READ NOP NOP tLZ DQ NOP tOH Dout tAC CAS Latency=3 DON'T CARE UNDEFINED Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 12 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 4: Command Truth Table COMMAND Command Inhibit (NOP) CKEn-1 CKEn CS RAS CAS WE DQM H X H X X X X ADDR A10 Note X No Operation (NOP) H X L H H H X X Mode Register Set H X L L L L X OP-CODE 4 Extended Mode Register Set H X L L L L X OP-CODE 4 Active (select bank and activate row) H X L L H H X Bank/Row Read H X L H L H L/H Bank/Col L 5 Read with Autoprecharge H X L H L H L/H Bank/Col H 5 Write H X L H L L L/H Bank/Col L 5 Write with Autoprecharge H X L H L L L/H Bank/Col H 5 Precharge All Banks H X L L H L X X H Precharge Selected Bank H X L L H L X Bank L Burst stop H H L H H L X Auto Refresh H H L L L H X X 3 Self Refresh Entry H L L L L H X X 3 Self Refresh Exit L H H X X X L H H H X X 2 Precharge Power Down Entry H L X X Precharge Down Exit L H X X Clock Suspend Entry H L X X Clock Suspend Exit L H X X Deep Power Down Entry H L X X Deep Power Down Exit L H X X H X X X L H H H H X X X L H H H H X X X L V V V X L H H X L X 6 Note : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previoys clock edge. H: High Level, L: Low Level, X: Don't Care, V: Valid 2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A mimum of two NOP commands must be provided during tXSR period. 3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended mode register set. 5. DQM "L" means the data Write/Ouput Enable and "H" means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK. 6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is assigned to the Deep Power Down function. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 13 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 5: Function Truth Table Current State IDLE ROW ACTIVE READ WRITE Command /CS /RAS /CAS /WE A11 A0-A10 L L L L OP CODE L L L H X L L H L BA L L H H BA L H L L L H L H L H H H H X X L L L L L L L Action Description Note Mode Register Set Set the Mode Register 14 X Auto or Self Refresh Start Auto or Self Refresh 5 X Precharge No Operation Row Addr Bank Active Activate the Specific Bank and Row BA Col Addr/A10 Write/Write AP ILLEGAL 4 BA Col Addr/A10 Read/Read AP ILLEGAL 4 X X NOP NOP 3 X X X Device Deselect NOP or Power Down 3 L OP CODE Mode Register Set ILLEGAL 13,14 L H X X Auto or Self Refresh ILLEGAL 13 L H L BA X Precharge Precharge 7 L H H BA Row Addr Bank Active ILLEGAL 4 6 6 L H L L BA Col Addr/A10 Write/Write AP Start Write : Optional AP(A10 = H) L H L H BA Col Addr/A10 Read/Read AP Start Read: Optional AP(A10 = H) L H H H X X NOP NOP H X X X X X Device Deselect NOP L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge Termination Burst : Start the Precharge L L H H BA Row Addr Bank Active ILLEGAL 4 8,9 8 L H L L BA Col Addr/A10 Write/Write AP Termination Burst: Start Write(AP) L H L H BA Col Addr/A10 Read/Read AP Termination Burst: Start Read(AP) L H H H X X NOP Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X Auto or Self Refresh ILLEGAL 13 X L L H L BA X Precharge Termination Burst : Start the Precharge L L H H BA Row Addr Bank Active ILLEGAL 4 8,9 8 L H L L BA Col Addr/A10 Write/Write AP Termination Burst: Start Write(AP) L H L H BA Col Addr/A10 Read/Read AP Termination Burst: Start Read(AP) L H H H X X NOP Continue the Burst H X X X X X Device Deselect Continue the Burst Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 14 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 5: Function Truth Table Current State READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE PRECHARGING ROW ACTIVATING Command /CS /RAS /CAS /WE A11 A0-A10 Action Description Note L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Addr Bank Active ILLEGAL 4,12 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 12 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 12 L H H H X X NOP Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Addr Bank Active ILLEGAL 4,12 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 12 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 12 L H H H X X NOP Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge No Operation: Bank(s) Idle after tRP L L H H BA Row Addr Bank Active ILLEGAL 4,12 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4,12 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 4,12 L H H H X X NOP No Operation: Bank(s) Idle after tRP H X X X X X Device Deselect No Operation: Bank(s) Idle after tRP L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,12 L L H H BA Row Addr Bank Active ILLEGAL 4, 11, 12 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4,12 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 4,12 L H H H X X NOP No Operation: Row Activated after tRCD H X X X X X Device Deselect No Operation: Row Activated after tRCD Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 15 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 5: Function Truth Table Current State WRITE RECOVERING Write Recovering with Auto Precharge REFRES HING Mode Register Accessing Command /CS /RAS /CAS /WE A11 A0-A10 Action Description Note L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Addr Bank Active ILLEGAL 4,12 L H L L BA Col Addr/A10 Write/Write AP Start Write : Optional AP(A10 = H) L H L H BA Col Addr/A10 Read/Read AP Start Write : Optional AP(A10 = H) L H H H X X NOP No Operation : Row Active after tDPL H X X X X X Device Deselect No Operation : Row Active after tDPL 9 L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 4,13 L L H H BA Row Addr Bank Active ILLEGAL 4,12 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4,12 4,9, 12 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL L H H H X X NOP No Operation : Precharge after tDPL H X X X X X Device Deselect No Operation : Precharge after tDPL L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Addr Bank Active ILLEGAL 13 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 13 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 13 L H H H X X NOP No Operation : Idle after tRC H X X X X X Device Deselect No Operation : Idle after tRC L L L L OP CODE Mode Register Set ILLEGAL 13,14 L L L H X X Auto or Self Refresh ILLEGAL 13 L L H L BA X Precharge ILLEGAL 13 L L H H BA Row Addr Bank Active ILLEGAL 13 L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 13 L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 13 L H H H X X NOP No Operation : Idle after 2 Clock Cycle H X X X X X Device Deselect No Operation : Idle after 2 Clock Cycle Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 16 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except A11. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 17 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 6: CKE Truth Table Current State Self Refresh CKE Deep Power Down All Bank Idle Any State other than listed above Action Note Prev Cycle Current Cycle /CS /RAS /CAS /WE A11 A0-A10 H X X X X X X X INVALID 2 3 L H H X X X X X Exit Self Refresh with Device Deselect L H L H H H X X Exit Self Refresh with No Operation 3 L H L H H L X X ILLEGAL 3 L H L H L X X X ILLEGAL 3 L H L L X X X X ILLEGAL 3 L L X X X X X X Maintain Self Refresh H X L Power Down Command L H H X X X X X X INVALID 2 H X X X X X L H H H X X Power Down Mode Exit, All Banks Idle 3 L X X X X X L X X X ILLEGAL 3 X X L X X L L L X X X X X X Maintain Power Down Mode H X X X X X X X INVALID 2 6 L H X X X X X X Deep Power Down Mode Set L L X X X X X X Maintain Deep Power Down Mode H H H X X X H H L H X X H H L L H X H H L L L H H H L L L L H L H X X X H L L H X X H L L L H X H L L L L H H L L L L L L X X X X X Refer to the Idle State section of the Current State Truth Table X X Op-Code X X 4 4 4 Auto Refresh Mode Register Set 5 Refer to the Idle State section of the Current State Truth Table 4 4 X Entry Self Refresh 5 Op-Code Mode Register Set X Power Down H H X X X X X X Refer to Operations of the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 4 5 18 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Note : 1. H: Logic High, L: Logic Low, X: Don't care 2. For the given current state CKE must be low in the previous cycle. 3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 4. The address inputs depend on the command that is issued. 5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 100usec. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 19 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 7: ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL Ambient Temperature (Industrial) RATING -25 ~ 85 TA Ambient Temperature (Commerical) Storage Temperature UNIT C 0 ~ 70 TSTG -55~150 C Voltage on Any Pin Relative to VSS VIN, VOUT -1.0~4.6 V Voltage on VDD Relative to VSS VDD, VDDQ -1.0~4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 8: Capacitance (TA = 25C, f = 1MHz, VDD = 3.0V or 3.3V) PARAMETER Input Capacitance PIN SYMBOL MIN MAX UNIT CLK Cl1 2 4 pF A0~A11, CKE, /CS /RAS, /CAS, /WE, L(U)DQM Cl2 2 4 pF DQ0~DQ15 CIO 3 5 pF Data Input / Output Capacitance Table 9: DC CHARACTERISTIC & OPERATION CONDITION (TA = -25 to 85C) PARAMETER Power Supply Voltage SYMBOL MIN TYP MAX UNIT NOTE VDD 2.7 3.0 3.6 V VDDQ 2.7 3.0 3.6 V 1 Input High Voltage VIH 2.2 -- VDDQ+0.3 V 2 Input Low Voltage VIL -0.3 0 0.5 V 3 Output Logic High Current VOH 2.4 -- -- V IOH = -0.1mA Output Logic Low Current VOL -- -- 0.4 V IOL = +0.1mA Input Leakage Current ILI -1 -- 1 A 4 Output Leakage Current ILO -1.5 -- 1.5 A 5 Note : 1. VDDQ must not exceed the level of VDD 2. VIH(max) = 5.3V AC. The overshoot voltage duration is 3ns 3. VIL(min) = -2.0V AC. The overshoot voltage duration is 3ns. 4. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs 5. DOUT is disabled, 0V VOUT VDDQ. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 20 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 10: AC OPERATNG CONDITION (TA = -25 to 85C, VDD=3.0V or 3.3V 0.3V, VSS = 0V) PARAMETER AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage SYMBOL TYP UNIT VIH / VIL 2.4/0.4 V Vtrip 0.5 x VDDQ V Input Rise / Fall Time tR / tF 1/1 ns Output Timing Measurement Reference Level Voutref 0.5 x VDDQ V CL 30 pF Output Load Capacitance for Access Time Measurement VTT=0.5 x VDDQ VDDQ 1200 Output 50 Output 870 Z0=50 30pF DC Output Load Circuit 30pF AC Output Load Circuit Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 21 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 11: DC CHARACTERISTIC (DC Operating Conditions Unless Otherwise Noted) PARAMETER SYM Operating Current Precharge Standby Current in Power Down Mode Self Refresh Current 2Bank 1Bank UNIT NOTE 10 mA 1 ICC2P CKE VIL (max), tCK=10ns 60 uA -- ICC2PS CKE & CLK VIL(max), tCK= 60 uA -- ICC2N CKEVIH (min), /CSVIH(min), tCK=10ns Input Signal are changed one time during 2clks. 6 mA -- tCK= Input signals are stable 1 mA -- ICC3P CKEVIL(max), tCK=10ns 0.5 mA -- ICC3PS CKE & CLK VIL(max), tCK= 0.5 mA -- ICC3N CKEVIH(min), /CSVIH(min), tCK=10ns Input Signals are changed one time during 2clks 12 mA -- 6 mA -- mA 1 mA 2 CKEVIH (min), /CSVIH(min) CKEVIH(min), CLK VIL(max) ICC3NS PASR 75 30 Active Standby Current in Non Power-Down Mode Auto Refresh Current 60 Burst Length=1, One Bank Active tRC tRC (min) IOL=0mA ICC2NS Operating Current (Burst Mode) SPEED ICC1 Precharge Standby Current in Non Power Down Mode Active Standby Current in PowerDown Mode TEST CONDITION tCK= Input Signals are stable ICC4 tCKtCK(min), IOL=0mA, Page Burst All Banks Activated, tCCD = 1clk ICC5 tRC tRFC (min) All banks active 55 45 35 30 TCSR 45~85C -25~45C 85 ~ 100 ICC6 45~85C 70 ~ 85 uA 80 ~ 95 -25~45C Deep Power Down Mode Current CKE 0.2V 65 ~ 80 ICC7 20 uA Note: 1. Measured with outputs open. 2. Refresh period is 64ms. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 22 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted) PARAMETER CLK Cycle Time Access time from CLK (pos. edge) SYM -60 MIN -75 MAX MIN MAX MIN tCK3 6.0 CL=2 tCK2 10 CL=3 tAC3 5.5 6 8 CL=2 tAC2 8 8 8 CLK High-Level Width 10 1000 10 10 1000 1 2 2.5 2.5 3 3 2.5 2.5 2.5 1.5 2.0 2.0 CKE Hold Time tCKH 1.0 1.0 1.0 /CS, /RAS, /CAS, /WE, DQM Setup Time tCMS 1.5 2.0 2.0 /CS, /RAS, /CAS, /WE, DQM Hold TIme tCMH 1.0 1.0 1.0 Address Setup Time tAS 1.5 2.0 2.0 Address Hold Time tAH 1.0 1.0 1.0 Data-In Setup Time tDS 1.5 2.0 2.0 Data-In Hold Time tDH 1.0 1.0 1.0 ns CL=3 tHZ3 5.5 6 8 CL=2 tHZ2 8 8 8 Data-Out Low-Impedance Time NOTE 2.5 tCL CKE Setup Time UNIT tCH tCKS CLK Low-Level Width Data-Out High-Impedance Time from CLK (pos.edge) MAX CL=3 1000 7.5 -10 tLZ 1.0 1.0 1.0 2.5 4 tOH 2.5 2.5 Data-Out Hold Time (no load) tOHN 1.8 1.8 ACTIVE to PRECHARGE command tRAS 42 PRECHARGE command period tRP 18 22.5 20 ACTIVE bank a to ACTIVE bank a command tRC 60 67.5 60 ACTIVE bank a to ACTIVE bank b command tRRD 12 15 20 ACTIVE to READ or WRITE delay tRCD 18 22.5 20 READ/WRITE command to READ/WRITE command tCCD 1 1 1 CLK 6 WRITE command to input data delay tDWD 0 0 0 CLK 6 Data-in to PRECHARGE command tDPL 12 15 20 Data-Out Hold Time (load) 100K 45 1.8 100K 40 100K 5 ns 7 Data-in to ACTIVE command tDAL 30 37.5 40 DQM to data high-impedance during READs tDQZ 2 2 2 6 DQM to data mask during WRITES tDQM 0 0 0 6 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 8 CL=3 tROH3 3 3 3 CL=2 tROH2 2 2 2 Last data-in to burst STOP command tBDL 1 1 1 Last data-in to new READ/WRITE command tCDL 1 1 1 6 tCKED 1 1 1 9 CKE to clock enable or power-down exit setup mode tPED 1 1 1 9 Self Refresh Exit Time tSRE 1 1 1 10 Data-out to high-impedance from PRECHARGE command CKE to clock disable or power-down entry mode 7 6 CLK Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 6 23 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted) PARAMETER SYM -60 MIN -75 MAX MIN 64 -10 MAX MIN 64 64 Refresh Period (4,096 rows) tREF AUTO REFRESH period tRFC 66 67.5 70 Exit SELF REFRESH to ACTIVE command tXSR 66 67.5 70 tT 0.5 Transition time 1.2 0.5 1.2 MAX 0.5 UNIT NOTE ms 5 ns 5 1.2 Note: 1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to reduce the data rate. 2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. 3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 5. Parameter guaranteed by design. A. Target values listed with alternative values in parentheses. B. tRFC must be less than or equal to tRC+1CLK tXSR must be less than or equal to tRC+1CLK 6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate 8. JEDEC and PC100 specify three clocks. 9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate. 10. A new command can be given tRC after self refresh exit. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 24 N16D1633LPA NanoAmp Solutions, Inc. Advance Information SPECIAL OPERATION FOR LOW POWER CONSUMPTION TEMPERATURE COMPENSATED SELF REFRESH Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Setting E4 and E3, allow the DRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. PARTIAL ARRAY SELF REFRESH For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are Two Bank;all two banks, One Bank;bank a. WRITE and READ commands can still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost. DEEP POWER DOWN Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low. This mode is exited by asserting CKE high. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 25 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Figure 9: Deep Power Down Mode Entry CLK CKE /CS /RAS tRP Deep Power Down Entry Precharge if needed Figure 10: Deep Power Down Mode Exit CLK CKE /CS /RAS /CAS /WE 100 s Deep Power Down Exit tRP tRFC Auto Refresh All Banks Precharge Auto Refresh Mode Register Set New Command Extended Mode Register Set Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 26 N16D1633LPA NanoAmp Solutions, Inc. Advance Information Ordering Information N 16 D 16 33 LP A XX - XX X Temperature C = Commercial (0-70C) I = Industrial (-25 to 85) NanoAmp Solutions Speed Density 60 = 6.0ns (166MHz) 75 = 7.5ns (133MHz) 10 = 10ns (100MHz) Package 16= 16Mb Product Type D = SDRAM Z2 = Green 48FBGA (RoHS Compliant) C2 = Green 60WBGA (RoHS Compliant) T2 = Green 50 TSOP2 (RoHS Compliant) Generation Data I/O Width 16 = 16 I/O A = 1ST Generation Features Power Supply 33 = 3.0/3.3V LP = Low Power SDRAM Revision History Revision Date Change Description A November 18 2004 Initial ADVANCE Release B November 30 2004 Changed Refresh Time to 4K / 64ms C December 15 2004 General Update. Added BGA package option D February 16, 2005 Changed Driver Strength control EMRS Table E February 23, 2005 Changed Pin Ordering (Page 2) Changed Pin Name BA to A11 F March 1, 2005 Removed 2/3 Reg Drive Strength (Page 1) Updated Extend Mode Register Diagram (Page 8) Modifed Pin Name Description (Page 10) Updated Command Truth Table (Burst Stop). Changed CKEn "X" to "H" (Page 12) Updated Partial Array Description. Changed Bank 0 to Bank a (Page 24) G March 3, 2005 Updated Mode Register and Extended Mode Register Diagram (Page 7, 8, 9, 24) Fixed Typo in Table 3 (Page 7) Updated Footnote #14(Page 16) Deleted tSRE from AC Timing Table and Footnote #10 (Page 22, 23) H May 3, 2005 Changed 48FBGA and 60WBGA package thickness to 1.0mm Max Added Pb-Free ordering option for 48FBGA package and 60WBGA package I May 11, 2005 Changed 48FBGA ordering option to Green instead of Pb-Free J July 19, 2005 Added 50-pin TSOP II package option K August 15, 2005 L January 2006 Updated AC/DC characteristics and added green TSOP II Designated green package to be RoHS Compliant (c) 2004-2005 Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp product may be expected to result in significant injury or death, including life support systems and critical medical instrument. Stock No. 23395- Rev L 1/06 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 27