N16D1633LPAT2-60I - NanoAmp Solutions, Inc.

NanoAmp Solutions, Inc.

670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035

ph: 408-935-7777, FAX: 408-935-7770

www.nanoamp.com

N16D1633LPA

Stock No. 23395- Rev L 1/06 1

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

Advance Information

512K × 16 Bits × 2 Banks Low Power Synchronous DRAM

DESCRIPTION

These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288

words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the

clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally

pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Features

• JEDEC standard 3.0V/3.3V power supply.

• Auto refresh and self refresh.

• All pins are compatible with LVTTL interface.

• 4K refresh cycle / 64ms.

• Programmable Burst Length and Burst Type.

- 1, 2, 4, 8 or Full Page for Sequential Burst.

- 4 or 8 for Interleave Burst.

• Programmable CAS Latency : 2,3 clocks.

• Programmable Driver Strength Control.

- Full Strength or 1/2, 1/4 of Full Strength

• Deep Power Down Mode

• All inputs and outputs referenced to the positive

edge of the system clock.

• Data mask function by DQM.

• Internal dual banks operation.

• Burst Read Single Write operation.

• Special Function Support.

-PASR (Partial Array Self Refresh)

-Auto TCSR(Temperature Compensated Self Refresh)

• Automatic precharge, includes CONCURRENT

Auto Precharge Mode and controlled Precharge

Table 1: Ordering Information

PART NO. CLOCK Freq. Temperature VDD/VDDQ INTERLEAVE PACKAGE

N16D1633LPAZ2-75I 133MHz

-25o C to

85o C

3.0V/3.0V

3.3V/3.3V

LVTTL

48-Ball Green

FBGA

N16D1633LPAZ2-10I 100MHz

N16D1633LPAC2-60I 166MHz

60-Ball Green

WBGA

N16D1633LPAC2-75I 133MHz

N16D1633LPAC2-10I 100MHz

N16D1633LPAT2-60I 166MHz

50-Pin Green

TSOP II

N16D1633LPAT2-75I 133MHz

N16D1633LPAT2-10I 100MHz

N16D1633LPA

Stock No. 23395- Rev L 1/06 2

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 1: Package Configuration (60-Ball WBGA)

Note:

1. All Dimensions in millimeters

VSS DQ15 DQ0 VDD

DQ14 VSSQ VDDQ DQ1

DQ13 VDDQ VSSQ DQ2

DQ12 DQ11 DQ4 DQ3

DQ10 VSSQ VDDQ DQ5

DQ9 VDDQ VSSQ DQ6

DQ8 NC NC DQ7

NC NC NC NC

NC UDQM LDQM /WE

NC CLK /RAS /CAS

CKE NC NC /CS

A11 A9 NC NC

A8 A7 A0 A10

A6 A5 A2 A1

VSS A4 A3 VDD

[Bottom View]

7 6 5 4 3 2 1

0.65

3.9

10.10.1

6.40.1

9.1

1.0max 0.230.05

0.30.05

Unit [mm]

1 2 3 4 5 6 7

[Top View]

0.65

1.25

VSS DQ15 DQ0 VDD

DQ14 VSSQ VDDQ DQ1

DQ13 VDDQ VSSQ DQ2

DQ12 DQ11 DQ4 DQ3

DQ10 VSSQ VDDQ DQ5

DQ9 VDDQ VSSQ DQ6

DQ8 NC NC DQ7

NC NC NC NC

NC UDQM LDQM /WE

NC CLK /RAS /CAS

CKE NC NC /CS

A11 A9 NC NC

A8 A7 A0 A10

A6 A5 A2 A1

VSS A4 A3 VDD

[Bottom View]

7 6 5 4 3 2 1

0.65

3.9

10.10.1

6.40.1

9.1

1.0max 0.230.05

0.30.05

Unit [mm]

1 2 3 4 5 6 7

[Top View]

0.65

1.25

N16D1633LPA

Stock No. 23395- Rev L 1/06 3

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 2: Package Configuration (48-Ball FBGA)

Note:

1. All Dimensions in millimeters

[Bottom View]

[Top View]

CLK /CS A0 A1 A2 /CAS

DQ8 NC A3 A4 CKE DQ0

DQ9 DQ10 A5 A6 DQ1 DQ2

VSS DQ11 /RAS A7 DQ3 VDDQ

VDD DQ12 NC NC DQ4 VSSQ

DQ14 DQ13 NC NC DQ5 DQ6

DQ15 NC UDQM LDQM /WE DQ7

NC A8 A9 A10 A11 NC

1 2 3 4 5 6

6 5 4 3 2 1

80.1

5.25

0.75

6.00.1

3.75

0.75

0.230.05

0.300.05

1.0max

1.125

Unit [mm]

N16D1633LPA

Stock No. 23395- Rev L 1/06 4

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 3: Package Configuration (50-Pin TSOP II)

50 Pin

TSOP II

VDD

DQ0

DQ1

GNDQ

DQ2

DQ3

VDDQ

DQ4

DQ5

GNDQ

DQ6

DQ7

VDDQ

LDQM

/WE

/CAS

/RAS

/CS

A11

A10

VDD

GND

DQ15

DQ14

GNDQ

DQ13

DQ12

VDDQ

DQ11

DQ10

GNDQ

DQ9

DQ8

VDDQ

UDQM

CLK

CKE

GND

20.95 ± 0.10

10.16 ± 0.10

0.80 BSC

0o - 8o

[Top View]

11.76 ± 0.20

1.20 MAX

0.50 ± 0.10

NOTES:

1. All dimensions in millimeters unless otherwise noted

2. BSC = Basic lead spacing between centers

3. MAX / MIN

0.49

0.27

0.15

0.05

1.00 ± 0.05 0.17 NOM

0.80 NOM

1.03 MAX

N16D1633LPA

Stock No. 23395- Rev L 1/06 5

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Table 2: Pin Descriptions

PIN PIN NAME DESCRIPTIONS

CLK System Clock The system clock input. All other inputs are registered to the

SDRAM on the rising edge of the CLK

CKE Clock Enable

Controls internal clock signal and when deactivated, the

SDRAM will be one of the states among power down, suspend

or self refresh.

/CS Chip Select Enable or disable all inputs except CLK, CKE and DQM

A11 Bank Address Selects bank to be activated during /RAS activity

Selects bank to be read/written during /CAS activity

A0~A10 Address

Row Address : RA0~RA10

Column Address: CA0~CA7

Auto Precharge : A10

/RAS, /CAS, /WE

Row Address Strobe,

Column Address Strobe,

Write Enable

/RAS, /CAS and /WE define the operation

Refer function truth table for details

LDQM/UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in

write mode

DQ0~DQ15 Data Input/Output Multiplexed data input/output pin

VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

VDDQ/VSSQ Data Output Power/Ground Power Supply for output buffers

NC No Connection No Connection

N16D1633LPA

Stock No. 23395- Rev L 1/06 6

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 4: Functional Block Diagram

TCSR

PASR

CONTROL LOGIC

COMMAND DECODER

COLUMN

ADDRESS

BUFFER &

BURST

COUNTER

CLOCK

GENERATOR

CLK

CKE

ROW

ADDRESS

BUFFER &

REFRESH

COUNTER

/CS

/RAS

/CAS

/WE

MODE

BANK B

ROW DECODER

BANK B

ROW DECODER

BANK A

ROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

& LATCH CIRCUIT

BANK A

ROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

& LATCH CIRCUIT

DQM

ADDRESS

DATA CONTROL CIRCUITDATA CONTROL CIRCUIT

LATCH CIRCUITLATCH CIRCUIT

INPUT & OUTPUT

BUFFER

INPUT & OUTPUT

BUFFER

EXTENDED

MODE

N16D1633LPA

Stock No. 23395- Rev L 1/06 7

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Figure 5: Simplified State Diagram

CKE ↓

CKE

CKE ↓

CKE

IDLE

ROW

ACTIVE

SELF

REFRESH

CBR

REFRESH

POWER

DOWN

ACTIVE

POWER

DOWN

READWRITE

READ AWRITE A

PRE-

CHARGE

READ

SUSPEND

READ A

SUSPEND

WRITE

SUSPEND

WRITE A

SUSPEND

POWER

MODE

SET

PRECHARGE

CKE ↓

CKE

CKE ↓

CKE

CKE ↓

CKE

CKE ↓

CKE

CKE ↓

CKE

CKE ↓

CKE

READ

WRITE

CKE ↓

CKE

CKE ↓

CKE

READ

WRITE

AUTO PRECHARGE

WRITE WITH

AUTO PRECHARGE

WRITE WITH

AUTO PRECHARGE

WRITE WITH

PRE

BST

ACT

CKE ↓

CKE

CKE ↓

CKE

REF

SELF

SELF EXIT

SELF

SELF EXIT

MRS

PRE(Prechargetermination)

Automatic Sequence

Manual Input

Automatic Sequence

Manual Input

EXTENDED

MODE

SET

EMRS

DEEP

POWER

DOWN

DPD EXIT

DPD

N16D1633LPA

Stock No. 23395- Rev L 1/06 8

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 6: Mode Register Definition

Note: M11(A11) must be sest to “0” to select mode Register (vs. the Extend Mode Register)

Burst Type

Accesses within a given burst may be programmed to be

either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3. The ordering of

accesses within a burst is determined by the burst

length, the burst type and the starting column address,

as shown in Table 3 .

Note :

1. For full-page accesses: y = 256

2. For a burst length of two, A1-A7 select the block-of-

two burst; A0 selects the starting column within the

block.

3. For a burst length of four, A2-A7 select the block-of-

four burst; A0-A1 select the starting column within the

block.

4. For a burst length of eight, A3-A7 select the block-of-

eight burst; A0-A2 select the starting column within the

block.

5. For a full-page burst, the full row is selected and A0-

A7 select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

7. For a burst length of one, A0-A7 select the unique

column to be accessed, and mode register bit M3 is

ignored.

Burst Read and Single Write1

Burst Read and Burst Write0

Write Burst ModeM9

Burst Read and Single Write1

Burst Read and Burst Write0

Write Burst ModeM9

Interleave1

Sequential0

Burst TypeM3

Interleave1

Sequential0

Burst TypeM3

Reserved001

Reserved101

2010

1100

3110

Reserved011

Reserved111

Reserved000

CAS LatencyM4M5M6

Reserved001

Reserved101

2010

1100

3110

Reserved011

Reserved111

Reserved000

CAS LatencyM4M5M6

Full Page

Reserved

M3 = 0

Burst Length

Reserved001

Reserved101

4010

2100

8110

Reserved011

Reserved111

1000

M3 = 1

M0M1M2

Full Page

Reserved

M3 = 0

Burst Length

Reserved001

Reserved101

4010

2100

8110

Reserved011

Reserved111

1000

M3 = 1

M0M1M2

0CAS Latency BT Burst Length

Address Bus

01234561098711

A0A1A2A3A4A5A6A7A8A9A10A11

Mode Register (Mx)

Table 3: Burst Definition

Burst

Length

Starting Column

Address Order of Access Within a Burst

A2 A1 A0 Sequential Interleave

200-1 0-1

11-0 1-0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

Page

N=A0~7

(Location 0-256)

Cn, Cn+1. Cn+2,

Cn+3, Cn+4…

…Cn-1, Cn...

Not Supported

N16D1633LPA

Stock No. 23395- Rev L 1/06 9

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 7: Extended Mode Register

Note: 1. E11(A11) must be set to “1” to select Extend Mode Register (vs. the base Mode Register)

1PASR

Address Bus

Extended Mode Register (Ex)

01234561098711

A0A1A2A3A4A5A6A7A8A9A10A11

Reserved001

Half of One Bank (A11=0, Row Address MSB=0)101

Reserved110

Quarter of One Bank (A11=0, Row Address 2 MSB=0)011

One Bank (A11=0)100

Reserved010

Reserved111

All Banks000

Self Refresh CoverageE0E1E2

Reserved001

Half of One Bank (A11=0, Row Address MSB=0)101

Reserved110

Quarter of One Bank (A11=0, Row Address 2 MSB=0)011

One Bank (A11=0)100

Reserved010

Reserved111

All Banks000

Self Refresh CoverageE0E1E2

1/2 Strength 10

1/4 Strength 01

Reserved11

Full Strength 00

Driver StrengthE5E6

1/2 Strength 10

1/4 Strength 01

Reserved11

Full Strength 00

Driver StrengthE5E6

000 0 DS TCSR

70°

45°

Auto11

85°

Maximum Case

Temp.

E3E4

70°

45°

Auto11

85°

Maximum Case

Temp.

E3E4

N16D1633LPA

Stock No. 23395- Rev L 1/06 10

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FUNCTIONAL DESCRIPTION

In general, this 16Mb SDRAM (512K x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.3V and includes a

synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 8,388,608-

bit banks is organized as 2,048 rows by 256 columns by 16-bits. Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE

command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to

be accessed (A11 select the bank, A0-A10 select the row). The address bits (A11 select the bank, A0-A7 select the

column) registered coincident with the READ or WRITE command are used to select the starting column location for

the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed

information covering device initialization, register definition, command descriptions and device operation.

Power up and Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is

stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM

requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. CKE must be held

high during the entire initialization period until the RECHARGE command has been issued. Starting at some point

during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP

commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks must then be precharged,

thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are

complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an

unknown state, it should be loaded prior to applying any operational command. And a extended mode register set

command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Low

Power SDRAM is ready for normal operation.

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection

of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is

programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed

again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst

(sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the

write burst mode, and M10 should be set to zero. M11 should be set to zero to prevent extended mode register. The

mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating

the subsequent operation. Violating either of these requirements will result in unspecified operation.

EXTENDED MODE REGISTER

The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional

functions are special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR)

Control, and Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed

via the Mode Register Set command (A11=1) and retains the stored information until it is programmed again or the

device loses power. The Extended Mode Register must be programmed with E7 through E10 set to “0”. The Extended

Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the

specified time before before initiating any subsequent operation. Violating either of these requirements results in

unspecified operation.

N16D1633LPA

Stock No. 23395- Rev L 1/06 11

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in

Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given

READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the

interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in

conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a

READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses

for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The

block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four;

and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to

select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by

activating /CS, /RAS and deasserting /CAS, /WE at the positive edge of the clock. The value on the A11 selects the

bank, and the value on the A0-A10 selects the row. This row remains active for column access until a precharge

command is issued to that bank. Read and write operations can only be initiated on this activated bank after the

minimum tRCD time is passed from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating /CS, /CAS, and

deasserting /WE, /RAS at the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge

is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected,

the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the

values programmed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating /CS, /CAS, /WE

and deasserting /RAS at the positive edge of the clock. A11 input select the bank, A0-A7 address inputs select the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge

is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected,

the row will remain active for subsequent accesses.

N16D1633LPA

Stock No. 23395- Rev L 1/06 12

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CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the

first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge

n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of

the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid

by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if

a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1

and the data will be valid by T2, as shown in Figure 2. Reserved states should not be used as unknown operation or

incompatibility with future versions may result.

Figure 8: CAS Latency

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8

are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions

may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the

programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

CLK

COMMAND

NOP NOP

Dout

T0 T1 T2

tLZ tOH

tAC

CAS Latency=2

READ

CLK

COMMAND

NOP NOP

Dout

T0 T1 T2

tLZ tOH

tAC

CAS Latency=2

READ

CLK

COMMAND

NOP NOP

Dout

T0 T1 T2

tLZ tOH

tAC

CAS Latency=3

NOP

READ

DON’T CARE

UNDEFINED

CLK

COMMAND

NOP NOP

Dout

T0 T1 T2

tLZ tOH

tAC

CAS Latency=3

NOP

READ

DON’T CARE

UNDEFINED

N16D1633LPA

Stock No. 23395- Rev L 1/06 13

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Note :

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previoys clock edge.

H: High Level, L: Low Level, X: Don't Care, V: Valid

2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once

tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A mimum

of two NOP commands must be provided during tXSR period.

3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended

mode register set.

5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and

Read DQM Latency is 2 CLK.

6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is

assigned to the Deep Power Down function.

Table 4: Command Truth Table

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10 Note

Command Inhibit (NOP) H X H X X X X X

No Operation (NOP) H X L H H H X X

Mode Register Set H X L L L L X OP-CODE 4

Extended Mode Register Set H X L L L L X OP-CODE 4

Active (select bank and activate

row) H X L L H H X Bank/Row

Read H X L H L H L/H Bank/Col L 5

Read with Autoprecharge H X L H L H L/H Bank/Col H 5

Write H X L H L L L/H Bank/Col L 5

Write with Autoprecharge H X L H L L L/H Bank/Col H 5

Precharge All Banks H X L L H L X X H

Precharge Selected Bank H X L L H L X Bank L

Burst stop H H L H H L X X

Auto Refresh H H L L L H X X 3

Self Refresh Entry H L L L L H X X 3

Self Refresh Exit L H HX X X XX2

LH HH

Precharge Power Down Entry H L HX X X XX

LH HH

Precharge Down Exit L H HX X X XX

LH HH

Clock Suspend Entry H L HX X X XX

LV VV

Clock Suspend Exit L H X X X

Deep Power Down Entry H L L H H L X X 6

Deep Power Down Exit L H X X X

N16D1633LPA

Stock No. 23395- Rev L 1/06 14

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Table 5: Function Truth Table

Current

State

Command

Action Note

/CS /RAS /CAS /WE A11 A0-A10 Description

IDLE

L L L L OP CODE Mode Register Set Set the Mode Register 14

L L L H X X Auto or Self Refresh Start Auto or Self Refresh 5

L L H L BA X Precharge No Operation

L L H H BA Row Addr Bank Active Activate the Specific Bank

and Row

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 4

LH HHXX NOP NOP 3

H X X X X X Device Deselect NOP or Power Down 3

ROW

ACTIVE

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge Precharge 7

L L H H BA Row Addr Bank Active ILLEGAL 4

L H L L BA Col Addr/A10 Write/Write AP Start Write : Optional

AP(A10 = H) 6

L H L H BA Col Addr/A10 Read/Read AP Start Read: Optional

AP(A10 = H) 6

LH HHXX NOP NOP

H X X X X X Device Deselect NOP

READ

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge Termination Burst :

Start the Precharge

L L H H BA Row Addr Bank Active ILLEGAL 4

L H L L BA Col Addr/A10 Write/Write AP Termination Burst:

Start Write(AP) 8,9

L H L H BA Col Addr/A10 Read/Read AP Termination Burst:

Start Read(AP) 8

L H H H X X NOP Continue the Burst

H X X X X X Device Deselect Continue the Burst

WRITE

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge Termination Burst :

Start the Precharge

L L H H BA Row Addr Bank Active ILLEGAL 4

L H L L BA Col Addr/A10 Write/Write AP Termination Burst:

Start Write(AP) 8,9

L H L H BA Col Addr/A10 Read/Read AP Termination Burst:

Start Read(AP) 8

L H H H X X NOP Continue the Burst

H X X X X X Device Deselect Continue the Burst

N16D1633LPA

Stock No. 23395- Rev L 1/06 15

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READ

with

AUTO

PRE-

CHARGE

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 4,12

L L H H BA Row Addr Bank Active ILLEGAL 4,12

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 12

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 12

L H H H X X NOP Continue the Burst

H X X X X X Device Deselect Continue the Burst

WRITE

with

AUTO

PRE-

CHARGE

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 4,12

L L H H BA Row Addr Bank Active ILLEGAL 4,12

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 12

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 12

L H H H X X NOP Continue the Burst

H X X X X X Device Deselect Continue the Burst

PRE-

CHARG-

ING

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge No Operation: Bank(s)

Idle after tRP

L L H H BA Row Addr Bank Active ILLEGAL 4,12

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4,12

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 4,12

LH HHXX NOP No Operation: Bank(s)

Idle after tRP

H X X X X X Device Deselect No Operation: Bank(s)

Idle after tRP

ROW

ACTIVAT-

ING

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 4,12

L L H H BA Row Addr Bank Active ILLEGAL 4, 11,

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4,12

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 4,12

LH HHXX NOP No Operation: Row Acti-

vated after tRCD

H X X X X X Device Deselect No Operation: Row Acti-

vated after tRCD

Table 5: Function Truth Table

Current

State

Command

Action Note

/CS /RAS /CAS /WE A11 A0-A10 Description

N16D1633LPA

Stock No. 23395- Rev L 1/06 16

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WRITE

RECOV-

ERING

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 4,13

L L H H BA Row Addr Bank Active ILLEGAL 4,12

L H L L BA Col Addr/A10 Write/Write AP Start Write : Optional

AP(A10 = H)

L H L H BA Col Addr/A10 Read/Read AP Start Write : Optional

AP(A10 = H) 9

LH HHXX NOP No Operation : Row Active

after tDPL

H X X X X X Device Deselect No Operation : Row Active

after tDPL

Write

Recover-

ing with

Auto Pre-

charge

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 4,13

L L H H BA Row Addr Bank Active ILLEGAL 4,12

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 4,12

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 4,9,

LH HHXX NOP No Operation : Precharge

after tDPL

H X X X X X Device Deselect No Operation : Precharge

after tDPL

REFRES

HING

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 13

L L H H BA Row Addr Bank Active ILLEGAL 13

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 13

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 13

LH HHXX NOP No Operation : Idle after

tRC

H X X X X X Device Deselect No Operation : Idle after

tRC

Mode

Accessing

L L L L OP CODE Mode Register Set ILLEGAL 13,14

L L L H X X Auto or Self Refresh ILLEGAL 13

L L H L BA X Precharge ILLEGAL 13

L L H H BA Row Addr Bank Active ILLEGAL 13

L H L L BA Col Addr/A10 Write/Write AP ILLEGAL 13

L H L H BA Col Addr/A10 Read/Read AP ILLEGAL 13

LH HHXX NOP No Operation : Idle after 2

Clock Cycle

H X X X X X Device Deselect No Operation : Idle after 2

Clock Cycle

Table 5: Function Truth Table

Current

State

Command

Action Note

/CS /RAS /CAS /WE A11 A0-A10 Description

N16D1633LPA

Stock No. 23395- Rev L 1/06 17

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Note :

1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.

2. All entries assume that CKE was active during the preceding clock cycle.

3. If both banks are idle and CKE is inactive, then in power down cycle

4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,

depending on the state of that bank.

5. If both banks are idle and CKE is inactive, then Self Refresh mode.

6. Illegal if tRCD is not satisfied.

7. Illegal if tRAS is not satisfied.

8. Must satisfy burst interrupt condition.

9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

10. Must mask preceding data which don't satisfy tDPL.

11. Illegal if tRRD is not satisfied

12. Illegal for single bank, but legal for other banks in multi-bank devices.

13. Illegal for all banks.

14. Mode Register Set and Extended Mode Register Set is same command truth table except A11.

N16D1633LPA

Stock No. 23395- Rev L 1/06 18

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Table 6: CKE Truth Table

Current

State

CKE Command

Action Note

Cycle

Current

Cycle /CS /RAS /CAS /WE A11 A0-A10

Self

Refresh

HXXXXXXXINVALID 2

LHHXXXXX

Exit Self Refresh with

Device Deselect 3

LHLHHHXX

Exit Self Refresh with

No Operation 3

L H L H H L X X ILLEGAL 3

L H L H L X X X ILLEGAL 3

L H L L X X X X ILLEGAL 3

L L X X X X X X Maintain Self Refresh

Power

Down

HXXXXXXXINVALID 2

HX XXX X Power Down Mode

Exit, All Banks Idle 3

LH HHX X

LHL

LXXX X

ILLEGAL 3XLXX X

XXLX X

LLXXXXXX

Maintain Power Down

Mode

Deep

Power

Down

HXXXXXXXINVALID 2

LHXXXXXX

Deep Power Down

Mode Set 6

LLXXXXXX

Maintain Deep Power

Down Mode

All Bank

Idle

HHHXXX Refer to the Idle State

section of the Current

State Truth Table

HHLHXX 4

HHLLHX 4

H H L L L H X X Auto Refresh

H H L L L L Op-Code Mode Register Set 5

HLHXXX Refer to the Idle State

section of the Current

State Truth Table

HLLHXX 4

HLLLHX 4

H L L L L H X X Entry Self Refresh 5

H L L L L L Op-Code Mode Register Set

L X X X X X X X Power Down 5

Any State

other than

listed

above

HHXXXXXX

Refer to Operations of

the Current State

Truth Table

HLXXXXXX

Begin Clock Suspend

next cycle

LHXXXXXX

Exit Clock Suspend

next cycle

LLXXXXXX

Maintain Clock Sus-

pend

N16D1633LPA

Stock No. 23395- Rev L 1/06 19

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Note :

1. H: Logic High, L: Logic Low, X: Don't care

2. For the given current state CKE must be low in the previous cycle.

3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,

a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.

4. The address inputs depend on the command that is issued.

5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle

state.

6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down

mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained

for a minimum 100usec.

N16D1633LPA

Stock No. 23395- Rev L 1/06 20

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Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

Note :

1. VDDQ must not exceed the level of VDD

2. VIH(max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns

3. VIL(min) = -2.0V AC. The overshoot voltage duration is ≤ 3ns.

4. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs

5. DOUT is disabled, 0V ≤ VOUT ≤ VDDQ.

Table 7: ABSOLUTE MAXIMUM RATING

PARAMETER SYMBOL RATING UNIT

Ambient Temperature (Industrial) TA -25 ~ 85 °C

Ambient Temperature (Commerical) 0 ~ 70

Storage Temperature TSTG -55~150 °C

Voltage on Any Pin Relative to VSS VIN, VOUT -1.0~4.6 V

Voltage on VDD Relative to VSS VDD, VDDQ -1.0~4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD 1 W

Table 8: Capacitance (TA = 25°C, f = 1MHz, VDD = 3.0V or 3.3V)

PARAMETER PIN SYMBOL MIN MAX UNIT

Input Capacitance

CLK Cl1 2 4 pF

A0~A11, CKE, /CS

/RAS, /CAS, /WE, L(U)DQM Cl2 2 4 pF

Data Input / Output

Capacitance DQ0~DQ15 CIO 3 5 pF

Table 9: DC CHARACTERISTIC & OPERATION CONDITION (TA = -25 to 85°C)

PARAMETER SYMBOL MIN TYP MAX UNIT NOTE

Power Supply Voltage VDD 2.7 3.0 3.6 V

VDDQ 2.7 3.0 3.6 V 1

Input High Voltage VIH 2.2 -- VDDQ+0.3 V 2

Input Low Voltage VIL -0.3 0 0.5 V 3

Output Logic High Current VOH 2.4 -- -- V IOH = -0.1mA

Output Logic Low Current VOL -- -- 0.4 V IOL = +0.1mA

Input Leakage Current ILI -1 -- 1 µA 4

Output Leakage Current ILO -1.5 -- 1.5 µA 5

N16D1633LPA

Stock No. 23395- Rev L 1/06 21

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Table 10: AC OPERATNG CONDITION (TA = -25 to 85°C, VDD=3.0V or 3.3V ± 0.3V, VSS = 0V)

PARAMETER SYMBOL TYP UNIT

AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 0.5 × VDDQ V

Input Rise / Fall Time tR / tF 1 / 1 ns

Output Timing Measurement Reference Level Voutref 0.5 × VDDQ V

Output Load Capacitance for Access Time Measurement CL 30 pF

Output

870Ω

1200Ω

VDDQ

30pF

Output

30pF

50Ω

VTT=0.5 x VDDQ

Z0=50Ω

DC Output Load Circuit AC Output Load Circuit

N16D1633LPA

Stock No. 23395- Rev L 1/06 22

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Note:

1. Measured with outputs open.

2. Refresh period is 64ms.

Table 11: DC CHARACTERISTIC (DC Operating Conditions Unless Otherwise Noted)

PARAMETER SYM TEST CONDITION

SPEED

UNIT NOTE

60 75 10

Operating Current ICC1 Burst Length=1, One Bank Active

tRC ≥ tRC (min) IOL=0mA 30 mA 1

Precharge Standby Current in

Power Down Mode

ICC2P CKE ≤ VIL (max), tCK=10ns 60 uA --

ICC2PS CKE & CLK ≤VIL(max), tCK=∞60 uA --

Precharge Standby Current in

Non Power Down Mode

ICC2N

CKE≥VIH (min), /CS≥VIH(min),

tCK=10ns

Input Signal are changed one time

during 2clks.

6mA--

ICC2NS

CKE≥VIH (min), /CS≥VIH(min)

tCK=∞

Input signals are stable

1mA--

Active Standby Current in Power-

Down Mode

ICC3P CKE≤VIL(max), tCK=10ns 0.5 mA --

ICC3PS CKE & CLK ≤VIL(max), tCK=∞0.5 mA --

Active Standby Current in Non

Power-Down Mode

ICC3N

CKE≥VIH(min), /CS≥VIH(min),

tCK=10ns

Input Signals are changed one time

during 2clks

12 mA --

ICC3NS

CKE≥VIH(min), CLK ≤ VIL(max)

tCK=∞

Input Signals are stable

6mA--

Operating Current

(Burst Mode) ICC4

tCK≥tCK(min), IOL=0mA, Page

Burst

All Banks Activated, tCCD = 1clk

55 45 35 mA 1

Auto Refresh Current ICC5 tRC ≥ tRFC (min) All banks active 30 mA 2

Self

Refresh

Current

PASR TCSR

ICC6 CKE ≤ 0.2V uA

2Bank 45~85C 85 ~ 100

-25~45C 70 ~ 85

1Bank 45~85C 80 ~ 95

-25~45C 65 ~ 80

Deep Power Down Mode Current ICC7 20 uA

Stock No. 23395- Rev L 1/06 23

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Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted)

PARAMETER SYM

-60 -75 -10

UNIT NOTE

MIN MAX MIN MAX MIN MAX

CLK Cycle Time CL=3 tCK3 6.0 1000 7.5 1000 10 1000

CL=2 tCK2 10 10 10

Access time from CLK (pos. edge) CL=3 tAC3 5.5 6 8 2

CL=2 tAC2 888

CLK High-Level Width tCH 2.5 2.5 2.5 3

CLK Low-Level Width tCL 2.5 2.5 2.5 3

CKE Setup Time tCKS 1.5 2.0 2.0

CKE Hold Time tCKH 1.0 1.0 1.0

/CS, /RAS, /CAS, /WE, DQM Setup Time tCMS 1.5 2.0 2.0

/CS, /RAS, /CAS, /WE, DQM Hold TIme tCMH 1.0 1.0 1.0

Address Setup Time tAS 1.5 2.0 2.0

Address Hold Time tAH 1.0 1.0 1.0

Data-In Setup Time tDS 1.5 2.0 2.0

Data-In Hold Time tDH 1.0 1.0 1.0

Data-Out High-Impedance Time

from CLK (pos.edge)

CL=3 tHZ3 5.5 6 8 4

CL=2 tHZ2 8 8 8

Data-Out Low-Impedance Time tLZ 1.0 1.0 1.0

Data-Out Hold Time (load) tOH 2.5 2.5 2.5

Data-Out Hold Time (no load) tOHN 1.8 1.8 1.8

ACTIVE to PRECHARGE command tRAS 42 100K 45 100K 40 100K

PRECHARGE command period tRP 18 22.5 20

ACTIVE bank a to ACTIVE bank a com-

mand tRC 60 67.5 60 5

ACTIVE bank a to ACTIVE bank b com-

mand tRRD 12 15 20

ACTIVE to READ or WRITE delay tRCD 18 22.5 20

READ/WRITE command to READ/WRITE

command tCCD 111CLK6

WRITE command to input data delay tDWD 000CLK6

Data-in to PRECHARGE command tDPL 12 15 20 ns 7

Data-in to ACTIVE command tDAL 30 37.5 40 7

DQM to data high-impedance during

READs tDQZ 222

CLK

DQM to data mask during WRITES tDQM 000 6

LOAD MODE REGISTER command to

ACTIVE or REFRESH command tMRD 222 8

Data-out to high-impedance from

PRECHARGE command

CL=3 tROH3 333 6

CL=2 tROH2 222

Last data-in to burst STOP command tBDL 111 6

Last data-in to new READ/WRITE com-

mand tCDL 111 6

CKE to clock disable or power-down entry

mode tCKED 111 9

CKE to clock enable or power-down exit

setup mode tPED 111 9

Self Refresh Exit Time tSRE 111 10

Stock No. 23395- Rev L 1/06 24

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Note:

1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the

clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used

to reduce the data rate.

2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge

rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.

3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid

data element will meet tOH before going High-Z.

5. Parameter guaranteed by design.

A. Target values listed with alternative values in parentheses.

B. tRFC must be less than or equal to tRC+1CLK

tXSR must be less than or equal to tRC+1CLK

6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.

7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate

8. JEDEC and PC100 specify three clocks.

9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.

10. A new command can be given tRC after self refresh exit.

Refresh Period (4,096 rows) tREF 64 64 64 ms

AUTO REFRESH period tRFC 66 67.5 70

Exit SELF REFRESH to ACTIVE command tXSR 66 67.5 70 5

Transition time tT 0.5 1.2 0.5 1.2 0.5 1.2

Table 12: AC CHARACTERISTIC (AC Operating Conditions Unless Otherwise Noted)

PARAMETER SYM

-60 -75 -10

UNIT NOTE

MIN MAX MIN MAX MIN MAX

Stock No. 23395- Rev L 1/06 25

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SPECIAL OPERATION FOR LOW POWER CONSUMPTION

TEMPERATURE COMPENSATED SELF REFRESH

Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH

mode, according to the case temperature of the Low Power SDRAM device. This allows great power savings during

SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller

have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires

refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher

temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more

often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest

temperature range expected.

Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh

rate was set to accommodate the higher temperatures. Setting E4 and E3, allow the DRAM to accommodate more

specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF

REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM

is operating at normal temperatures.

PARTIAL ARRAY SELF REFRESH

For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of

memory that will be refreshed during SELF REFRESH. The refresh options are Two Bank;all two banks, One

Bank;bank a. WRITE and READ commands can still occur during standard operation, but only the selected banks will

be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.

DEEP POWER DOWN

Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole

memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is

entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the

clock, while CKE is low. This mode is exited by asserting CKE high.

Stock No. 23395- Rev L 1/06 26

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Figure 9: Deep Power Down Mode Entry

Figure 10: Deep Power Down Mode Exit

CLK

CKE

/CS

/RAS

Prechar

e if needed Deep Power Down Entry

tRP

CLK

CKE

/CS

/RAS

Prechar

e if needed Deep Power Down Entry

tRP

CLK

CKE

/CS

/RAS

/CAS

/WE

100 µ s tRP tRFC

Deep Power Down Exit

All Banks Prechar

Auto Refresh Mode Register Set

Extended Mode Re

ister Set

New Command

Auto Refresh

CLK

CKE

/CS

/RAS

/CAS

/WE

100 µ s tRP tRFC

Deep Power Down Exit

All Banks Prechar

Auto Refresh Mode Register Set

Extended Mode Re

ister Set

New Command

Auto Refresh

Stock No. 23395- Rev L 1/06 27

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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Ordering Information

NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.

NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-

poses only and they vary depending upon specific applications.

NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application

or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp

product may be expected to result in significant injury or death, including life support systems and critical medical instrument.

Revision History

Revision Date Change Description

A November 18 2004 Initial ADVANCE Release

B November 30 2004 Changed Refresh Time to 4K / 64ms

C December 15 2004 General Update. Added BGA package option

D February 16, 2005 Changed Driver Strength control EMRS Table

E February 23, 2005 Changed Pin Ordering (Page 2)

Changed Pin Name BA to A11

F March 1, 2005

Removed 2/3 Reg Drive Strength (Page 1)

Updated Extend Mode Register Diagram (Page 8)

Modifed Pin Name Description (Page 10)

Updated Command Truth Table (Burst Stop). Changed CKEn “X” to “H” (Page 12)

Updated Partial Array Description. Changed Bank 0 to Bank a (Page 24)

G March 3, 2005

Updated Mode Register and Extended Mode Register Diagram (Page 7, 8, 9, 24)

Fixed Typo in Table 3 (Page 7)

Updated Footnote #14(Page 16)

Deleted tSRE from AC Timing Table and Footnote #10 (Page 22, 23)

H May 3, 2005 Changed 48FBGA and 60WBGA package thickness to 1.0mm Max

Added Pb-Free ordering option for 48FBGA package and 60WBGA package

I May 11, 2005 Changed 48FBGA ordering option to Green instead of Pb-Free

J July 19, 2005 Added 50-pin TSOP II package option

K August 15, 2005 Updated AC/DC characteristics and added green TSOP II

L January 2006 Designated green package to be RoHS Compliant

N 16 D 16 33 LP A XX - XX X

NanoAmp Solutions

Product Type

Density

Data I/O Width

Power Supply

Temperature

Package

Speed

Generation

Features

16= 16Mb

D = SDRAM

16=16I/O

33 = 3.0/3.3V LP = Low Power SDRAM

A = 1ST Generation

Z2 = Green 48FBGA (RoHS Compliant)

60 = 6.0ns (166MHz)

75 = 7.5ns (133MHz)

10 = 10ns (100MHz)

C = Commercial (0-70C)

I = Industrial (-25 to 85)

C2 = Green 60WBGA (RoHS Compliant)

T2 = Green 50 TSOP2 (RoHS Compliant)