© 2000 Fairchild Semiconductor Corporation DS006420 www .fairchildsemi.com
August 1986
Revised March 2000
DM74LS279 Quad S-R Latch
DM74LS279
Quad S-R Latch
General Descript ion
The DM74LS279 consists of four individual and indepen-
dent Set-Reset Latches with active low inputs . Two of the
four latc hes h ave an add itiona l S input ANDed with the pri-
mary S input. A LOW on any S input while the R input is
HIGH will be stored in the latch and appear on the corre-
spondin g Q output as a H IG H. A LO W on the R input while
the S input is HIGH will clear the Q output to a LOW. Simul-
taneous transition of the R and S inputs from LOW-to-
HIGH will cause the Q output to be indeterminate. Both
inputs are voltage level triggered and are not affected by
transition time of the input data.
Ordering Code:
Devices also available in Tape and R eel. Spe ci fy by append ing the suffix let t er “X” to the orderin g c ode.
Connection Diagram Function Table
H = HIGH Level
L = LOW Level
Q0 = The Level of Q bef ore the indi ca t ed input cond it ions were es t ablished.
Note 1: For latches with double S inputs :
H = both S inputs HIGH
L = one or both S inputs LOW
Note 2: This outp ut level is pseud o stable; that is, it may not persist wh en
the S and R inputs return to their inactive (HIGH) level.
Order Number Package Number Package Description
DM74LS27 9M M16A 16-Lead Small Outline Integrated Circuit ( SOIC), JEDEC MS-0 12, 0.150 Narrow
DM74LS279N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Output
S (Note 1) R Q
L L H (Note 2)
LHH
HLL
HHQ
0
www.fairchildsemi.com 2
DM74LS279
Absolute Maximum Ratings(No te 3) Note 3: The “A bsolute Maxim um Ratin gs” are those valu es beyon d which
the saf ety of the device cannot be guarante ed. The device s hould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guarant eed at the absolute maximum ratin gs.
The “Re comme nded Operat ing Co ndition s” table will define the cond itions
for actu al device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 4: All typic als are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: ICC is meas ured wit h all R inpu ts grounde d, all S inputs at 4. 5V and all outputs OPEN.
Switching Characteri stics
at VCC = 5V and TA = 25°C
Supply Voltage 7V
Input Voltag e 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Volt age 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Curre nt 8 mA
TAFree Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
(Note 4)
VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, I OH = Max 2.7 3.5 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max 0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Curre nt VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA
IOS Short Circuit Output Current VCC = Max (Note 5) −20 −100 mA
ICC Supply Current VCC = Max (Note 6) 3.8 7 mA
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
tPLH Propagation Delay Time S to Q 22 25 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time S to Q 15 23 ns
HIGH-to-LOW Level Output
tPHL Propagation Delay Time R to Q 27 33 ns
HIGH-to-LOW Level Output
3 www.fairchildsemi.com
DM74LS279
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
www.fairchildsemi.com 4
DM74LS279 Quad S-R Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does no t assume any responsibility for use of any circuitr y described, no circuit patent licenses ar e implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a life su pport
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
