CD4510BMS CD4516BMS S E M I C O N D U C T O R CMOS Presettable Up/Down Counters December 1992 Features Description * High Voltage Types (20V Rating) CD4510BMS Presettable BCD Up/Down Counter and the CD4516BMS Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510BMS will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. * CD4510BMS - BCD Type * CD4516BMS - Binary Type * Medium Speed Operation - fCL = 8MHz Typ. at 10V * Synchronous Internal Carry Propagation * Reset and Preset Capability * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Standardized Symmetrical Output Characteristics * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" If the CARRY IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY OUT of a less significant stage to the CARRY IN of a more significant stage. The CD4510BMS and CD4516BMS can be cascaded in the ripple mode by connecting the CARRY OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Figures 13, 14.) These devices are similar to types MC14510 and MC14516. The CD4510BMS and CD4516BMS are supplied in these 16-lead outline packages: Applications * Up/Down Difference Counting * Multistage Synchronous Counting * Multistage Ripple Counting * Synchronous Frequency Dividers Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4510B Only *H4W H45 *FBF H1F H6W CD4516B Only Functional Diagram Pinout CD4510BMS, CD4516BMS TOP VIEW PRESET ENABLE 1 PRESET ENABLE 1 P1 16 VDD Q4 2 15 CLOCK P4 3 14 Q3 P1 4 13 P3 CARRY IN 5 12 P2 Q1 6 11 Q2 CARRY OUT 7 10 UP/DOWN VSS 8 P2 P3 P4 CLOCK UP/DOWN CARRY IN 9 RESET 4 6 12 11 13 14 3 2 5 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. 7-1157 Q3 Q4 10 7 9 (c) Harris Corporation 1992 Q2 15 RESET Copyright Q1 CARRY OUT VDD = 16 VSS = 8 File Number 3338 Specifications CD4510BMS, CD4516BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 C - 10 A +125oC - 1000 A 3 -55oC - 10 A o 1 +25 C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 2 -55oC VDD = 18V MAX 1 o 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1158 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4510BMS, CD4516BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay Clock to Q Output TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay Preset or Reset to Q TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Clock to Carry Out TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Propagation Delay Carry In to Carry Out Propagation Delay Preset or Reset to Carry Out Transition Time Maximum Clock Input Frequency TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND TTHL TTLH VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND +25 +125 oC, -55oC LIMITS MIN MAX UNITS - 400 ns - 540 ns - 420 ns 9 +25oC 10, 11 +125oC, -55oC - 567 ns 9 +25oC - 480 ns 10, 11 +125oC, -55oC - 648 ns - 250 ns - 338 ns - 640 ns - 864 ns oC 9 10, 11 VDD = 5V, VIN = VDD or GND (Note 3) oC 9 10, 11 TPHL5 TPLH5 FCL GROUP A SUBGROUPS TEMPERATURE +25 +125oC, -55oC 9 10, 11 +25 +125 oC oC, -55oC 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns 9 +25oC 2 - MHz 10, 11 +125oC, -55oC 1.48 - MHz MIN MAX UNITS - 5 A - 150 A - 10 A - 300 A - 10 A +125 - 600 A oC, +125oC, - 50 mV NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. Reset to Carry Out (TPLH) only. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE oC, -55 +25oC oC +125 VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC oC +125 VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC oC Output Voltage VOL VDD = 5V, No Load 1, 2 +25 -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA 0.64 - mA 0.9 - mA 1.6 - mA -55 Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55 Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 oC oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA - -0.64 mA +125 -55 7-1159 oC oC Specifications CD4510BMS, CD4516BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH5B CONDITIONS VDD = 5V, VOUT = 2.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -1.15 mA -55 Output Current (Source) Output Current (Source) Input Voltage Low IOH10 IOH15 VIL VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V +125oC 1, 2 1, 2 1, 2 oC - -2.0 mA - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA - 3 V oC, +125oC, +25 -55oC 1, 2 +25oC, +125oC, -55oC +7 - V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25 oC - 150 ns VDD = 10V 1, 2, 3 +25oC - 210 ns VDD = 15V 1, 2, 3 +25oC - 160 ns VDD = 10V 1, 2, 3 +25oC - 240 ns 1, 2, 3 +25 oC - 180 ns oC Input Voltage High VIH Propagation Delay Clock to Q Output TPHL1 TPLH1 VDD = 10V Propagation Delay Preset or Reset to Q TPHL2 TPLH2 Propagation Delay Clock to Carry Out TPHL3 TPLH3 Propagation Delay Carry In to Carry Out Propagation Delay Preset or Reset to Carry Out Transition Time Maximum Clock Input Frequency Minimum Hold Time Preset Enable to JN TPHL4 TPLH4 VDD = 10V, VOH > 9V, VOL < 1V VDD = 15V VDD = 10V 1, 2, 3 +25 - 120 ns VDD = 15V 1, 2, 3 +25oC - 100 ns +25 oC - 320 ns +25 oC - 250 ns - 100 ns TPHL5 TPLH5 VDD = 10V VDD = 15V 1, 2, 3, 4 TTLH TTHL VDD = 10V 1, 2, 3 +25oC VDD = 15V 1, 2, 3 oC - 80 ns FCL VDD = 10V 1, 2 +25oC 4 - MHz VDD = 15V 1, 2 +25oC TH 1, 2, 3, 4 Minimum Data Hold Time Clock to Carry In Minimum Clock Hold Time Clock to Up/Down TS TH +25 - 70 ns 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25 oC - 40 ns oC VDD = 5V 1, 2, 3 +25 - 25 ns VDD = 10V 1, 2, 3 +25oC - 10 ns VDD = 15V 1, 2, 3 +25 oC - 10 ns VDD = 5V 1, 2, 3 +25oC - 60 ns 1, 2, 3 +25 oC - 30 ns oC VDD = 15V 1, 2, 3 +25 - 30 ns VDD = 5V 1, 2, 3 +25oC - 30 ns 1, 2, 3 +25 oC - 30 ns +25 oC - 30 ns +25oC - 7.5 pF VDD = 10V CIN MHz 1, 2, 3 VDD = 15V Input Capacitance - VDD = 10V VDD = 10V TH 5.5 oC VDD = 5V VDD = 15V Minimum Data Setup Time Preset Enable to JN +25 1, 2, 3 Any Input 1, 2 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Reset to Carry Out (TPLH) only. 7-1160 Specifications CD4510BMS, CD4516BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 A 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10A 1, 4 +25oC - 1 V VSS = 0V, IDD = 10A 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - 1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Supply Current N Threshold Voltage VNTH N Threshold Voltage Delta VTN P Threshold Voltage VTP P Threshold Voltage Delta VTP Functional F VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD 1.0A Output Current (Sink) IOL5 20% x Pre-Test Reading IOH5A 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-1161 Specifications CD4510BMS, CD4516BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 2, 6, 7, 11, 14 1, 3-5, 8-10, 12, 13, 15 16 Static Burn-In 2 (Note 1) 2, 6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13, 15, 16 Dynamic BurnIn (Note 1) - 1, 3, 4, 8, 9, 12, 13 10, 16 2, 6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13, 15, 16 9V -0.5V 50kHz 25kHz 2, 6, 7, 11, 14 15 5 CD4510BMS Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V Logic Diagrams P1* 4 RESET* PRESET* ENABLE CLOCK* CARRY OUT P2* 12 Q1 6 Q4 2 1 P P P P PE Q PE Q PE Q PE Q C C C C 15 7 Q T Q1 UP/DOWN* P4* 3 Q3 14 9 T CARRY IN* P3* 13 Q2 11 Q Q2 T Q Q2 Q3 T Q3 Q Q4 5 10 U/D U/D Q1 U/D VDD * VSS U/D Q3 Q4 Q2 Q4 ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK FIGURE 1. CD4510BMS 7-1162 U/D Q3 U/D U/D Q2 Q2 Q4 U/D Q3 Q2 Q3 Q2 U/D Q3 Q4 Q4 CD4510BMS, CD4516BMS Logic Diagrams (Continued) P1* 4 RESET* PRESET* ENABLE CLOCK* CARRY OUT P2* 12 Q1 6 Q4 2 1 P P P P PE Q PE Q PE Q PE Q C C C C 15 7 Q T Q1 UP/DOWN* P4* 3 Q3 14 9 T CARRY IN* P3* 13 Q2 11 Q Q2 T Q Q2 Q3 T Q3 5 10 U/D U/D Q1 U/D Q3 U/D Q3 Q2 Q4 Q2 Q4 VDD * VSS U/D U/D Q2 Q2 ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK FIGURE 2. CD4516BMS TRUTH TABLE CL CI U/D PE R X 1 X 0 0 NO COUNT 0 1 0 0 COUNT UP 0 0 0 0 COUNT DOWN X X X 1 0 PRESET X X X X 1 RESET X = DON'T CARE 7-1163 ACTION U/D Q3 Q2 Q2 U/D Q3 Q Q4 Q4 CD4510BMS, CD4516BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -5 -10V TRANSITION TIME (tTLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 10V 15V 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE -15 FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 100 0 0 -10 -15V 200 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V AMBIENT TEMPERATURE (TA) = +25oC 150 0 AMBIENT TEMPERATURE (TA) = +25oC PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 250 200 SUPPLY VOLTAGE (VDD) = 5V 150 10V 100 15V 50 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE FOR CLOCK-TO-Q OUTPUTS 7-1164 CD4510BMS, CD4516BMS (Continued) POWER DISSIPATION PER GATE (PD) (W) MAXIMUM CLOCK INPUT FREQUENCY (fCL MAX) (MHz) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF 15 10 5 104 AMBIENT TEMPERATURE (TA) 8 = +25oC 6 4 tr, tf = 20ns 2 SUPPLY VOLTS (VDD) = 15V 103 10V 8 6 4 10V 5V 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 0 5 10 15 2 20 4 68 01 SUPPLY VOLTAGE (VDD) FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs SUPPLY VOLTAGE 2 1 4 68 2 4 68 2 4 68 2 4 68 10 102 103 INPUT FREQUENCY (fCL) (kHz) 104 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY Test Circuit and Waveform 100F ID 1 16 2 15 3 14 4 13 500F PULSE GENERATOR 20ns 90% CL CL CL CL 5 12 6 11 7 10 8 9 20ns VDD 50% 10% VARIABLE WIDTH VSS CL FIGURE 11. POWER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM Acquisition System SAMPLE AND HOLD AMPLIFIER ANALOG DATA INPUTS 16 CHANNEL MULTIPLEXER CD4067 START CLOCK CONVERSION LOGIC PRESET INPUTS NOTE: This acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the CD4516BMS. Q4 CD4516BMS CLOCK PARALLEL DATA OUTPUTS END SELECT INPUTS Q1 10 BIT A/D CONVERTER PRESET ENABLE FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM 7-1165 CD4510BMS, CD4516BMS Timing Diagrams CLOCK CARRY IN UP/DOWN RESET PE P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0 FIGURE 13. CD4510BMS CLOCK CARRY IN UP/DOWN RESET PE P1 P2 P3 VDD VSS P4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 5 6 7 8 9 10 11 12 13 14 15 9 8 7 FIGURE 14. CD4516BMS 7-1166 6 5 4 3 2 1 0 0 15 0 CD4510BMS, CD4516BMS PARALLEL CLOCKING UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 CI CD4510/16BMS CO CI CD4510/16BMS CO CI CD4510/16BMS CO R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 * CLOCK RESET * CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS IC'S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edgesensitive logic devices, such as FF'S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as CD4071BMS. RIPPLE CLOCKING UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 CLOCK UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 CI CD4510/16BMS CO CI CD4510/16BMS CO CI CD4510/16BMS CO R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 1/4 CD4071B RESET Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded. FIGURE 15. CASCADING COUNTER PACKAGES 7-1167 CD4510BMS, CD4516BMS Chip Dimensions and Pad Layouts CD4510BMS CD4510BMS Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kA - 14kA, AL. PASSIVATION: 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1168