MB96F315RSBPMC-GS-N2E2 - CYPRESS SEMICONDUCTOR

CY96310 Series

F2MC-16FX 16-bit Proprietary

Microcontroller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-04592 Rev. *B Revised June 4, 2018

CY96310 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The

CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new

16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the

same operation frequency, reduced power consumption and faster start-up time.

For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz

operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with

excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The

emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select

suitable operation frequencies for peripheral resources independent of the CPU speed.

Features

Technology

■0.18μm CMOS

CPU

■F2MC-16FX CPU

■Up to 56 MHz internal, 17.8 ns instruction cycle time

■Optimized instruction set for controller applications (bit, byte,

word and long-word data types; 23 different addressing modes;

barrel shift; variety of pointers)

■8-byte instruction execution queue

■Signed multiply (16-bit ×16-bit) and divide (32-bit/16-bit)

instructions available

System clock

■On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)

■3 MHz - 16 MHz external crystal oscillator clock (maximum

frequency when using ceramic resonator depends on

Q-factor).

■Up to 56 MHz external clock

■32-100 kHz subsystem quartz clock

■100kHz/2MHz internal RC clock for quick and safe startup,

oscillator stop detection, watchdog

■Clock source selectable from main- and subclock oscillator

(part number suffix “W”) and on-chip RC oscillator,

independently for CPU and 2 clock domains of peripherals.

■Low Power Consumption - 13 operating modes : (different Run,

Sleep, Timer modes, Stop mode)

■Clock modulator

On-chip vo lt a ge regu l at or

■Internal voltage regulator supports reduced internal MCU

voltage, offering low EMI and low power consumption figures

Low voltage rese t

■Reset is generated when supply voltage is below minimum.

Code Security

■Protects ROM content from unintended read-out

Memory Patch Function

■Replaces ROM content

■Can also be used to implement embedded debug support

DMA

■Automatic transfer function independent of CPU, can be

assigned freely to resources

Interrupts

■Fast Interrupt processing

■8 programmable priority levels

■Non-Maskable Interrupt (NMI)

Timers

■Three independent clock timers (23-bit RC clock timer, 23-bit

Main clock timer, 17-bit Sub clock timer)

■Watchdog Timer

CAN

■Supports CAN protocol version 2.0 part A and B

■ISO16845 certified

■Bit rates up to 1 Mbit/s

■32 message objects

■Each message object has its own identifier mask

■Programmable FIFO mode (concatenation of message

objects)

■Maskable interrupt

■Disabled Automatic Retransmission mode for Time Triggered

CAN applications

■Programmable loop-back mode for self-test operation

Document Number: 002-04592 Rev. *B Page 2 of 82

CY96310 Series

USART

■Full duplex USARTs (SCI/LIN)

■Wide range of baud rate settings using a dedicated reload timer

■Special synchronous options for adapting to different

synchronous serial protocols

■LIN functionality working either as master or slave LIN device

A/D converter

■SAR-type

■10-bit resolution

■Signals interrupt on conversion end, single conversion mode,

continuous conversion mode, stop conversion mode, activation

by software, external trigger or reload timer

Reload Timers

■16-bit wide

■Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral

clock frequency

■Event count function

Free Running Timers

■Signals an interrupt on overflow, supports timer clear upon

match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22,

1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency

Input Capture Units

■16-bit wide

■Signals an interrupt upon external event

■Rising edge, falling edge or rising & falling edge sensitive

Output Compare Units

■16-bit wide

■Signals an interrupt when a match with 16-bit I/O Timer occurs

■A pair of compare registers can be used to generate an output

signal.

Programmable Pulse Generator

■16-bit down counter, cycle and duty setting registers

■Interrupt at trigger, counter borrow and/or duty match

■PWM operation and one-shot operation

■Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock

as counter clock and Reload timer underflow as clock input

■Can be triggered by software or reload timer

Real Time Clock

■Can be clocked either from sub oscillator (devices with part

number suffix “W”), main oscillator or from the RC oscillator

■Facility to correct oscillation deviation of Sub clock or RC

oscillator clock (clock calibration)

■Read/write accessible second/minute/hour registers

■Can signal interrupts every half

second/second/minute/hour/day

■Internal clock divider and prescaler provide exact 1s clock

External Interrupts

■Edge sensitive or level sensitive

■Interrupt mask and pending bit per channel

■Each available CAN channel RX has an external interrupt for

wake-up

■Selected USART channels SIN have an external interrupt for

wake-up

Non Maskable Interrupt

■Disabled after reset

■Once enabled, can not be disabled other than by reset.

■Level high or level low sensitive

■Pin shared with external interrupt 0.

I/O Ports

■Virtually all external pins can be used as general purpose I/O

■All push-pull outputs

■Bit-wise programmable as input/output or peripheral signal

■Bit-wise programmable input enable

■Bit-wise programmable input levels: Automotive /

CMOS-Schmitt trigger / TTL

■Bit-wise programmable pull-up resistor

■Bit-wise programmable output driving strength for EMI

optimization

Packages

■48-pin plastic LQFP M26

Document Number: 002-04592 Rev. *B Page 3 of 82

CY96310 Series

Flash Memory

■Supports automatic programming, Embedded Algorithm

■Write/Erase/Erase-Suspend/Resume commands

■A flag indicating completion of the algorithm

■Number of erase cycles: 10,000 times

■Data retention time: 20 years

■Erase can be performed on each sector individually

■Sector protection

■Flash Security feature to protect the content of the Flash

■Low voltage detection during Flash erase

Document Number: 002-04592 Rev. *B Page 4 of 82

CY96310 Series

Contents

Product Lineup .................................................................5

Block Diagram ..................................................................6

Pin Assignments ..............................................................7

Pin Function Descripti on .................................................8

Pin Circuit Type ..............................................................10

I/O Circuit Type ...............................................................11

Memory Map ......................... ............................ ...............13

RAMSTART Addresses ............... ... ................................14

User ROM Memory Map for Flash Devices ..................15

Serial Programming Communication Interface ...........16

I/O Map .............................................................................17

Interrupt Vector Table ....................................................39

Handling Devices ............................................................42

Latch-up prevention ................................................... 42

Unused pins handling ................................................ 42

External clock usage .................................................42

Unused sub clock signal ............................................ 43

Notes on PLL clock mode operation ......................... 43

Power supply pins (VCC/VSS) .................................. 43

Crystal oscillator and ceramic resonator circuit ......... 43

Turn on sequence of power supply to

A/D converter and analog inputs ............................... 43

Pin handling when not using the A/D converter ........ 43

Notes on Power-on .................................................... 43

Stabilization of power supply voltage ........................ 44

Serial communication ................................................ 44

Electrical Characteristics ........... ....................................45

Absolute Maximum Ratings ....................................... 45

Recommended Operating Conditions ....................... 47

DC characteristics ..................................................... 48

AC Characteristics ..................................................... 55

Analog Digital Converter ........................................... 63

Low Voltage Detector characteristics ........................ 67

FLASH memory program/erase characteristics ........ 69

Example Characteristics ......... .......................................70

Temperature dependency of

power supply currents ............................................... 70

Frequency dependency of

power supply currents in PLL Run mode .................. 75

Package Dimension CY96(F)31x LQFP48 ....................76

Ordering Information ......................................................77

Revision History ............................................... ..............78

Major Changes ................................................................79

Document History ...........................................................81

Document Number: 002-04592 Rev. *B Page 5 of 82

CY96310 Series

1. Product Lineup

Features CY96V300C CY96(F)31x

Product type Evaluation sample Flash product: CY96F31x

Mask ROM product: CY9631x

Product options

YS NA Low voltage reset persistently on / Single clock devices

RS Low voltage reset can be disabled / Single clock devices

YW Low voltage reset persistently on / Dual clock devices

RW Low voltage reset can be disabled / Dual clock devices

AS No CAN / Low voltage reset can be disabled / Single clock devices

AW No CAN / Low voltage reset can be disabled / Dual clock devices

Flash/ROM RAM

96KB 8KB ROM/Flash memory

emulation by external

RAM, 92KB internal

RAM

CY96F313Y, CY96F313R, CY96F313A

160KB 8KB CY96F315Y, CY96F315R, CY96F315A

Package BGA416 LQA048

DMA 16 channels 4 channels

USART 10 channels 3 channels

A/D Converter 40 channels 12 channels

A/D Converter Reference

Voltage switch

yes No

16-bit Reload Timer 6 channels + 1

channel (for PPG)

4 channels + 1 channel (for PPG)

16-bit Free-Running Timer 4 channels 4 channels (without external clock input pin)

16-bit Output Compare 12 channels 2 channels

16-bit Input Capture 12 channels 4 channels (plus 3 channels for LIN USART)

16-bit Programmable Pulse

Generator

20 channels 14 channels

CAN Interface 5 channels 1 channel

External Interrupts 16 channels 11 channels

Non-Maskable Interrupt 1 channel

Real Time Clock 1

I/O Ports 136 34 for part number with suffix “W”, 36 for part number with suffix “S”

Clock output function 2 channels

Low voltage reset Yes

On-chip RC-oscillator Yes

Document Number: 002-04592 Rev. *B Page 6 of 82

CY96310 Series

2. Block Diagram

Block diagram of CY96(F)31x

DMA

Controller Boot ROM

Peripheral

Bus Bridge

Peripheral

Bus Bridge

16FX Core Bus (CLKB)

USART

3 ch.

10-bit ADC

12 ch.

I/O Timer 0

ICU 0/1

CAN

Interface

1 ch.

Real Time

Clock

Watchdog RAM Voltage

Regulator

SIN2, SIN2_R, SIN7_R, SIN8_R

SOT2, SOT2_R, SOT7_R, SOT8_R

SCK2, SCK2_R, SCK7_R, SCK8_R

IN0, IN1

OUT6, OUT7

TX2

RX2

Peripheral Bus 1 (CLKP1)

Peripheral Bus 2 (CLKP2)

VCC

VSS

I/O Timer 1

ICU 4/5/6

IN4, IN5

16FX

CPU

Interrupt

Controller

Clock &

Mode Controller

Flash

Memory A

Memory Patch

Unit

NMI

OCU 6/7

16-bit Reload

Timer

4 ch.

TIN1

TOT0_R, TOT2_R

TOT1, TOT3

External

Interrupt

INT0, INT8 ... INT13

INT2_R, INT4_R

INT3_R1

INT7_R, INT10_R

16-bit PPG

14 ch. PPG0, PPG1, PPG3, PPG4

TTG0, TTG1, TTG4, TTG8, TTG9, TTG12

PPG8_R, PPG9_R, PPG16_R ... PPG19_R

TTG8_R, TTG9_R, TTG16_R, TTG17_R

CKOT0_R, CKOT1, CKOT1_R

CKOTX1

X0, X1

X0A, X1A *1

RSTX

MD0...MD2

RLT6

*1: X0A, X1A only available on devices with suffix “W”

I/O Timer 2

ICU 9

I/O Timer 3

ICU 10

AVCC

AVSS

AVRH

AN0, AN1, AN3, AN4

ADTG_R

AN6 ... AN10

AN12, AN14, AN16

PPG6, PPG7, PPG12, PPG14

Document Number: 002-04592 Rev. *B Page 7 of 82

CY96310 Series

3. Pin Assignments

Pin assignment of CY96( F)31x

(LQA048)

Devices with suffix W: X0A, X1A

Devices with suffix S: P04_0, P04_1

*1:

12345678910 11 12

2627282930313233343536

LQFP - 48

Package code (mold)

LQA048

P05_1 / AN9 / SOT2

P06_7 / AN7 / PPG7

P06_4 / AN4 / PPG4

P06_3 / AN3 / PPG3

AVss

AVRH

P05_6 / AN14 / INT4_R

P05_2 / AN10 / SCK2

P05_4 / AN12 / TOT3 / INT2_R

P05_0 / AN8 / SIN2 / INT_3R1

P07_0 / AN16 / INT0 / NMI

P06_6 / AN6 / PPG6

X0A / P04_0 *1

X1A / P04_1 *1

MD2

MD1

MD0

P00_0 / INT8 / SCK7_R / TTG8_R

P00_1 / INT9 / SOT7_R / TTG9_R

P00_2 / INT10 / SIN7_R

P00_4 / INT12 / SOT8_R / PPG8_R

P00_5/ INT13 / SIN8_R / PPG9_R

P00_3 / INT11 / SCK8_R

P01_0 / CKOT1 / TIN1 / TTG16_R

P01_4 / PPG16_R

P01_6 / SOT2_R / PPG18_R

P01_7 / SCK2_R / PPG19_R

P02_0 / PPG12 / CKOT1_R

P02_2 / PPG14 / CKOT0_R

P02_4 / IN0 / TTG8 / TTG0

P01_5 / SIN2_R / INT7_R / PPG17_R

P01_1 / CKOTX1 / TOT1 / TTG17_R

P06_1 /AN1 / PPG1

P06_0 / AN0 / PPG0

AVcc

P02_5 / IN1 / TTG1 / TTG9 / ADTG_R

P03_0 / IN4 / TTG4 / TTG12 / TOT0_R

P03_1 / IN5 / TOT2_R

P03_2 / INT10_R / RX2

P03_3 / TX2

P03_6 / OUT6

P03_7 / OUT7

Vcc

RSTX

Vss

Document Number: 002-04592 Rev. *B Page 8 of 82

CY96310 Series

4. Pin Function Description

Pin Function description (1 of 2)

Pin name Feature Description

ADTG_R ADC Relocated A/D converter trigger input

ANn ADC A/D converter channel n input

AVCC Supply Analog circuits power supply

AVRH ADC A/D converter high reference voltage input

AVSS Supply Analog circuits power supply

C Voltage regulator Internally regulated power supply stabilization capacitor pin

CKOTn Clock output function Clock Output function n output

CKOTn_R Clock output function Relocated Clock Output function n output

CKOTXn Clock output function Clock Output function n inverted output

INn ICU Input Capture Unit n input

INTn External Interrupt External Interrupt n input

INTn_R External Interrupt Relocated External Interrupt n input

MDn Core Input pins for specifying the operating mode.

NMI External Interrupt Non-Maskable Interrupt input

OUTn OCU Output Compare Unit n waveform output

Pxx_n GPIO General purpose IO

PPGn PPG Programmable Pulse Generator n output

PPGn_R PPG Relocated Programmable Pulse Generator n output

RSTX Core Reset input

RXn CAN CAN interface n RX input

SCKn USART USART n serial clock input/output

SCKn_R USART Relocated USART n serial clock input/output

SINn USART USART n serial data input

SINn_R USART Relocated USART n serial data input

SOTn USART USART n serial data output

SOTn_R USART Relocated USART n serial data output

TINn Reload Timer Reload Timer n event input

TINn_R Reload Timer Relocated Reload Timer n event input

TOTn Reload Timer Reload Timer n output

TOTn_R Reload Timer Relocated Reload Timer n output

Document Number: 002-04592 Rev. *B Page 9 of 82

CY96310 Series

TTGn PPG Programmable Pulse Generator n trigger input

TTGn_R PPG Relocated Programmable Pulse Generator n trigger input

TXn CAN CAN interface n TX output

VCC Supply Power supply

VSS Supply Power supply

X0 Clock Oscillator input

X0A Clock Subclock Oscillator input (only for devices with suffix “W”)

X1 Clock Oscillator output

X1A Clock Subclock Oscillator output (only for devices with suffix “W”)

Pin Function description (2 of 2)

Pin name Feature Description

Document Number: 002-04592 Rev. *B Page 10 of 82

CY96310 Series

5. Pin Circuit Type

*1: Please refer to “6.“I/O Circuit Type”” for details on the I/O circuit types

*2: Devices with suffix “W”

*3: Devices without suffix “W”

Pin circuit types

LQA048

Pin no. Circuit type *1

1 Supply

3 to 12 I

13, 14 B *2

13, 14 H *3

15 to 17 C

18 to 32 H

33 E

34, 35 A

36, 37 Supply

38 F

39 to 45 H

46, 47 I

48 Supply

Document Number: 002-04592 Rev. *B Page 11 of 82

CY96310 Series

6. I/O Circuit Type

Type Circuit Remarks

High-speed oscillation circuit:

• Programmable between oscillation mode (external

crystal or resonator connected to X0/X1 pins) and

Fast external Clock Input (FCI) mode (external clock

connected to X0 pin)

• Programmable feedback resistor = approx.

2 * 0.5 MΩ. Feedback resistor is grounded in the

center when the oscillator is disabled or in FCI mode

Low-speed oscillation circuit:

• Programmable feedback resistor = approx.

2 * 5 MΩ. Feedback resistor is grounded in the center

when the oscillator is disabled

• Mask ROM and EVA device:

CMOS Hysteresis input pin

• Flash device:

CMOS input pin

E• CMOS Hysteresis input pin

• Pull-up resistor value: approx. 50 kΩ

MRFBE

Xout

FCI

FCI or osc disable

X1A

X0A

SRFBE

Xout

osc disable

Hysteresis

inputs

Pull-up

Resistor

Hysteresis

inputs

Document Number: 002-04592 Rev. *B Page 12 of 82

CY96310 Series

F • Power supply input protection circuit

• A/D converter ref+ (AVRH) power supply input pin

with protection circuit

• Flash devices do not have a protection circuit against

VCC for pin AVRH

• CMOS level output (programmable IOL = 5mA,

IOH = -5mA and IOL = 2mA, IOH = -2mA)

• CMOS hysteresis input with input shutdown function

• Automotive input with input shutdown function

• Programmable pull-up resistor: 50kΩ approx.

• CMOS level output (programmable IOL = 5mA,

IOH = -5mA and IOL = 2mA, IOH = -2mA)

• CMOS hysteresis input with input shutdown function

• Automotive input with input shutdown function

• Programmable pull-up resistor: 50kΩ approx.

• Analog input

Type Circuit Remarks

ANE

AVR

ANE

Pout

pull-up control

Nout

Hysteresis input

Automotive input

Standby control

for input shutdown

Standby control

for input shutdown

Hysteresis input

Automotive input

Standby control

for input shutdown

Standby control

for input shutdown

Pull-up control

Pout

Nout

Analog input

Document Number: 002-04592 Rev. *B Page 13 of 82

CY96310 Series

7. Memory Map

CY96V300C CY96(F)31x

FF:FFFFH

Emulation ROM USER ROM /

Reserved*4

DE:0000H

External Bus Reserved

10:0000H

0F:E000HBoot-ROM Boot-ROM

Reserved

0E:0000H

External RAM

02:0000H

Internal RAM

bank 1

01:0000H

ROM/RAM MIRROR ROM/RAM MIRROR

00:8000H

Internal RAM

bank 0

Internal RAM

bank 0

RAMSTART0*2

Reserved

RAM-

START0*3

00:0C00HExternal Bus

Peripherals Peripherals

00:0380H

00:0180HGPR*1 GPR*1

00:0100HDMA DMA

00:00F0HExternal Bus Reserved

00:0000HPeripheral Peripheral

*1: Unused GPR banks can be used as RAM area

*2: For RAMSTART0 addresses, please refer to the table on the next page.

*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.

*4: For details about USER ROM area, see the ■ User ROM Memory Map for Flash Devices on the following

pages.

The DMA area is only available if the device contains the corresponding resource.

The available RAM and ROM area depends on the device.

Document Number: 002-04592 Rev. *B Page 14 of 82

CY96310 Series

8. RAMSTART Addresses

Devices RAM size RAMSTART0

CY96F313/F315 8KByte 00:6240H

Document Number: 002-04592 Rev. *B Page 15 of 82

CY96310 Series

9. User ROM Memory Map for Flash Devices

CY96F313 CY96F315

Alternative mode

CPU address

Flash memory

mode address

Flash size

96kByte

Flash size

160kByte

FF:FFFFH

FF:0000H

3F:FFFFH

3F:0000HS39 - 64K S39 - 64K

Flash A

FE:FFFFH

FE:0000H

3E:FFFFH

3E:0000H

Reserved

S38 - 64K

FD:FFFFH

FD:0000H

3D:FFFFH

3D:0000H

Reserved

FC:FFFFH

FC:0000H

3C:FFFFH

3C:0000H

FB:FFFFH

FB:0000H

3B:FFFFH

3B:0000H

FA:FFFFH

FA:0000H

3A:FFFFH

3A:0000H

F9:FFFFH

F9:0000H

39:FFFFH

39:0000H

F8:FFFFH

F8:0000H

38:FFFFH

38:0000H

F7:FFFFH

F7:0000H

37:FFFFH

37:0000H

F6:FFFFH

F6:0000H

36:FFFFH

36:0000H

F5:FFFFH

F5:0000H

35:FFFFH

35:0000H

F4:FFFFH

F4:0000H

34:FFFFH

34:0000H

F3:FFFFH

F3:0000H

33:FFFFH

33:0000H

F2:FFFFH

F2:0000H

32:FFFFH

32:0000H

F1:FFFFH

F1:0000H

31:FFFFH

31:0000H

F0:FFFFH

F0:0000H

30:FFFFH

30:0000H

E0:FFFFH

DF:FFFFH

DF:8000H

DF:7FFFH

DF:6000H

1F:7FFFH

1F:6000HSA3 - 8K SA3 - 8K

Flash A

DF:5FFFH

DF:4000H

1F:5FFFH

1F:4000HSA2 - 8K SA2 - 8K

DF:3FFFH

DF:2000H

1F:3FFFH

1F:2000HSA1 - 8K SA1 - 8K

DF:1FFFH

DF:0000H

1F:1FFFH

1F:0000HSA0 - 8K *1 SA0 - 8K *1

DE:FFFFH

DE:0000H

Reserved Reserved

*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH

Document Number: 002-04592 Rev. *B Page 16 of 82

CY96310 Series

10. Serial Programming Communication Interface

Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least

port P00_1 on pin 19.

If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to

check the tool manual or to contact the tool vendor for alternative handshaking pins.

USART pins for Flash serial programming (MD[2:0] = 010)

CY96F31x

Pin number USART Number Normal function

LQFP-48

USART2

SIN2

8SOT2

9SCK2

USART7

SIN7_R

19 SOT7_R

18 SCK7_R

USART8

SIN8_R

21 SOT8_R

23 SCK8_R

Document Number: 002-04592 Rev. *B Page 17 of 82

CY96310 Series

11. I/O Map

I/O map CY96(F)315x (Sheet 1 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

000000HI/O Port P00 - Port Data Register PDR00 R/W

000001HI/O Port P01 - Port Data Register PDR01 R/W

000002HI/O Port P02 - Port Data Register PDR02 R/W

000003HI/O Port P03 - Port Data Register PDR03 R/W

000004HReserved -

000005HI/O Port P05 - Port Data Register PDR05 R/W

000006HI/O Port P06 - Port Data Register PDR06 R/W

000007HI/O Port P07 - Port Data Register PDR07 R/W

000008H-

000017H

Reserved -

000018HADC0 - Control Status register Low ADCSL ADCS R/W

000019HADC0 - Control Status register High ADCSH R/W

00001AHADC0 - Data Register Low ADCRL ADCR R

00001BHADC0 - Data Register High ADCRH R

00001CHADC0 - Setting Register ADSR R/W

00001DHADC0 - Setting Register R/W

00001EHADC0 - Extended Configuration Register ADECR R/W

00001FHReserved -

000020HFRT0 - Data register of free-running timer TCDT0 R/W

000021HFRT0 - Data register of free-running timer R/W

000022HFRT0 - Control status register of free-running timer Low TCCSL0 TCCS0 R/W

000023HFRT0 - Control status register of free-running timer High TCCSH0 R/W

000024HFRT1 - Data register of free-running timer TCDT1 R/W

000025HFRT1 - Data register of free-running timer R/W

000026HFRT1 - Control status register of free-running timer Low TCCSL1 TCCS1 R/W

000027HFRT1 - Control status register of free-running timer High TCCSH1 R/W

000028H-

000039H

Reserved -

00003AHOCU6 - Output Compare Control Status OCS6 R/W

00003BHOCU7 - Output Compare Control Status OCS7 R/W

Document Number: 002-04592 Rev. *B Page 18 of 82

CY96310 Series

00003CHOCU6 - Compare Register OCCP6 R/W

00003DHOCU6 - Compare Register R/W

00003EHOCU7 - Compare Register OCCP7 R/W

00003FHOCU7 - Compare Register R/W

000040HICU0/ICU1 - Control Status Register ICS01 R/W

000041HICU0/ICU1 - Edge register ICE01 R/W

000042HICU0 - Capture Register Low IPCPL0 IPCP0 R

000043HICU0 - Capture Register High IPCPH0 R

000044HICU1 - Capture Register Low IPCPL1 IPCP1 R

000045HICU1 - Capture Register High IPCPH1 R

000046H -

00004BH

Reserved -

00004CHICU4/ICU5 - Control Status Register ICS45 R/W

00004DHICU4/ICU5 - Edge register ICE45 R/W

00004EHICU4 - Capture Register Low IPCPL4 IPCP4 R

00004FHICU4 - Capture Register High IPCPH4 R

000050HICU5 - Capture Register Low IPCPL5 IPCP5 R

000051HICU5 - Capture Register High IPCPH5 R

000052HICU6/ICU7 - Control Status Register ICS67 R/W

000053HICU6/ICU7 - Edge register ICE67 R/W

000054HICU6 - Capture Register Low IPCPL6 IPCP6 R

000055HICU6 - Capture Register High IPCPH6 R

000056HICU7 - Capture Register Low IPCPL7 IPCP7 R

000057HICU7 - Capture Register High IPCPH7 R

000058HEXTINT0 - External Interrupt Enable Register ENIR0 R/W

000059HEXTINT0 - External Interrupt Interrupt request Register EIRR0 R/W

00005AHEXTINT0 - External Interrupt Level Select Low ELVRL0 ELVR0 R/W

00005BHEXTINT0 - External Interrupt Level Select High ELVRH0 R/W

00005CHEXTINT1 - External Interrupt Enable Register ENIR1 R/W

00005DHEXTINT1 - External Interrupt Interrupt request Register EIRR1 R/W

00005EHEXTINT1 - External Interrupt Level Select Low ELVRL1 ELVR1 R/W

I/O map CY96(F)315x (Sheet 2 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 19 of 82

CY96310 Series

00005FHEXTINT1 - External Interrupt Level Select High ELVRH1 R/W

000060HRLT0 - Timer Control Status Register Low TMCSRL0 TMCSR0 R/W

000061HRLT0 - Timer Control Status Register High TMCSRH0 R/W

000062HRLT0 - Reload Register - for writing TMRLR0 W

000062HRLT0 - Reload Register - for reading TMR0 R

000063HRLT0 - Reload Register - for writing W

000063HRLT0 - Reload Register - for reading R

000064HRLT1 - Timer Control Status Register Low TMCSRL1 TMCSR1 R/W

000065HRLT1 - Timer Control Status Register High TMCSRH1 R/W

000066HRLT1 - Reload Register - for writing TMRLR1 W

000066HRLT1 - Reload Register - for reading TMR1 R

000067HRLT1 - Reload Register - for writing W

000067HRLT1 - Reload Register - for reading R

000068HRLT2 - Timer Control Status Register Low TMCSRL2 TMCSR2 R/W

000069HRLT2 - Timer Control Status Register High TMCSRH2 R/W

00006AHRLT2 - Reload Register - for writing TMRLR2 W

00006AHRLT2 - Reload Register - for reading TMR2 R

00006BHRLT2 - Reload Register - for writing W

00006BHRLT2 - Reload Register - for reading R

00006CHRLT3 - Timer Control Status Register Low TMCSRL3 TMCSR3 R/W

00006DHRLT3 - Timer Control Status Register High TMCSRH3 R/W

00006EHRLT3 - Reload Register - for writing TMRLR3 W

00006EHRLT3 - Reload Register - for reading TMR3 R

00006FHRLT3 - Reload Register - for writing W

00006FHRLT3 - Reload Register - for reading R

000070H

RLT6 - Timer Control Status Register Low (dedic. RLT for

PPG) TMCSRL6 TMCSR6 R/W

000071H

RLT6 - Timer Control Status Register High (dedic. RLT for

PPG) TMCSRH6 R/W

000072HRLT6 - Reload Register (dedic. RLT for PPG) - for writing TMRLR6 W

000072HRLT6 - Reload Register (dedic. RLT for PPG) - for reading TMR6 R

I/O map CY96(F)315x (Sheet 3 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 20 of 82

CY96310 Series

000073HRLT6 - Reload Register (dedic. RLT for PPG) - for writing W

000073HRLT6 - Reload Register (dedic. RLT for PPG) - for reading R

000074HPPG3-PPG0 - General Control register 1 Low GCN1L0 GCN10 R/W

000075HPPG3-PPG0 - General Control register 1 High GCN1H0 R/W

000076HPPG3-PPG0 - General Control register 2 Low GCN2L0 GCN20 R/W

000077HPPG3-PPG0 - General Control register 2 High GCN2H0 R/W

000078HPPG0 - Timer register PTMR0 R

000079HPPG0 - Timer register R

00007AHPPG0 - Period setting register PCSR0 W

00007BHPPG0 - Period setting register W

00007CHPPG0 - Duty cycle register PDUT0 W

00007DHPPG0 - Duty cycle register W

00007EHPPG0 - Control status register Low PCNL0 PCN0 R/W

00007FHPPG0 - Control status register High PCNH0 R/W

000080HPPG1 - Timer register PTMR1 R

000081HPPG1 - Timer register R

000082HPPG1 - Period setting register PCSR1 W

000083HPPG1 - Period setting register W

000084HPPG1 - Duty cycle register PDUT1 W

000085HPPG1 - Duty cycle register W

000086HPPG1 - Control status register Low PCNL1 PCN1 R/W

000087HPPG1 - Control status register High PCNH1 R/W

000088H-

00008FH

Reserved -

000090HPPG3 - Timer register PTMR3 R

000091HPPG3 - Timer register R

000092HPPG3 - Period setting register PCSR3 W

000093HPPG3 - Period setting register W

000094HPPG3 - Duty cycle register PDUT3 W

000095HPPG3 - Duty cycle register W

000096HPPG3 - Control status register Low PCNL3 PCN3 R/W

I/O map CY96(F)315x (Sheet 4 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 21 of 82

CY96310 Series

000097HPPG3 - Control status register High PCNH3 R/W

000098HPPG7-PPG4 - General Control register 1 Low GCN1L1 GCN11 R/W

000099HPPG7-PPG4 - General Control register 1 High GCN1H1 R/W

00009AHPPG7-PPG4 - General Control register 2 Low GCN2L1 GCN21 R/W

00009BHPPG7-PPG4 - General Control register 2 High GCN2H1 R/W

00009CHPPG4 - Timer register PTMR4 R

00009DHPPG4 - Timer register R

00009EHPPG4 - Period setting register PCSR4 W

00009FHPPG4 - Period setting register W

0000A0HPPG4 - Duty cycle register PDUT4 W

0000A1HPPG4 - Duty cycle register W

0000A2HPPG4 - Control status register Low PCNL4 PCN4 R/W

0000A3HPPG4 - Control status register High PCNH4 R/W

0000A4H-

0000D3H

Reserved -

0000D4HUSART2 - Serial Mode Register SMR2 R/W

0000D5HUSART2 - Serial Control Register SCR2 R/W

0000D6HUSART2 - TX Register TDR2 W

0000D6HUSART2 - RX Register RDR2 R

0000D7HUSART2 - Serial Status SSR2 R/W

0000D8HUSART2 - Control/Com. Register ECCR2 R/W

0000D9HUSART2 - Ext. Status Register ESCR2 R/W

0000DAHUSART2 - Baud Rate Generator Register Low BGRL2 BGR2 R/W

0000DBHUSART2 - Baud Rate Generator Register High BGRH2 R/W

0000DCHUSART2 - Extended Serial Interrupt Register ESIR2 R/W

0000DDH-

0000FFH

Reserved -

000100HDMA0 - Buffer address pointer low byte BAPL0 R/W

000101HDMA0 - Buffer address pointer middle byte BAPM0 R/W

000102HDMA0 - Buffer address pointer high byte BAPH0 R/W

000103HDMA0 - DMA control register DMACS0 R/W

I/O map CY96(F)315x (Sheet 5 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 22 of 82

CY96310 Series

000104HDMA0 - I/O register address pointer low byte IOAL0 IOA0 R/W

000105HDMA0 - I/O register address pointer high byte IOAH0 R/W

000106HDMA0 - Data counter low byte DCTL0 DCT0 R/W

000107HDMA0 - Data counter high byte DCTH0 R/W

000108HDMA1 - Buffer address pointer low byte BAPL1 R/W

000109HDMA1 - Buffer address pointer middle byte BAPM1 R/W

00010AHDMA1 - Buffer address pointer high byte BAPH1 R/W

00010BHDMA1 - DMA control register DMACS1 R/W

00010CHDMA1 - I/O register address pointer low byte IOAL1 IOA1 R/W

00010DHDMA1 - I/O register address pointer high byte IOAH1 R/W

00010EHDMA1 - Data counter low byte DCTL1 DCT1 R/W

00010FHDMA1 - Data counter high byte DCTH1 R/W

000110HDMA2 - Buffer address pointer low byte BAPL2 R/W

000111HDMA2 - Buffer address pointer middle byte BAPM2 R/W

000112HDMA2 - Buffer address pointer high byte BAPH2 R/W

000113HDMA2 - DMA control register DMACS2 R/W

000114HDMA2 - I/O register address pointer low byte IOAL2 IOA2 R/W

000115HDMA2 - I/O register address pointer high byte IOAH2 R/W

000116HDMA2 - Data counter low byte DCTL2 DCT2 R/W

000117HDMA2 - Data counter high byte DCTH2 R/W

000118HDMA3 - Buffer address pointer low byte BAPL3 R/W

000119HDMA3 - Buffer address pointer middle byte BAPM3 R/W

00011AHDMA3 - Buffer address pointer high byte BAPH3 R/W

00011BHDMA3 - DMA control register DMACS3 R/W

00011CHDMA3 - I/O register address pointer low byte IOAL3 IOA3 R/W

00011DHDMA3 - I/O register address pointer high byte IOAH3 R/W

00011EHDMA3 - Data counter low byte DCTL3 DCT3 R/W

00011FHDMA3 - Data counter high byte DCTH3 R/W

000120H-

00017FH

Reserved -

I/O map CY96(F)315x (Sheet 6 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 23 of 82

CY96310 Series

000180H-

00037FH

CPU - General Purpose registers (RAM access) GPR_RAM R/W

000380HDMA0 - Interrupt select DISEL0 R/W

000381HDMA1 - Interrupt select DISEL1 R/W

000382HDMA2 - Interrupt select DISEL2 R/W

000383HDMA3 - Interrupt select DISEL3 R/W

000384H-

00038FH

Reserved -

000390HDMA - Status register low byte DSRL DSR R/W

000391HDMA - Status register high byte DSRH R/W

000392HDMA - Stop status register low byte DSSRL DSSR R/W

000393HDMA - Stop status register high byte DSSRH R/W

000394HDMA - Enable register low byte DERL DER R/W

000395HDMA - Enable register high byte DERH R/W

000396H-

00039FH

Reserved -

0003A0HInterrupt level register ILR ICR R/W

0003A1HInterrupt index register IDX R/W

0003A2HInterrupt vector table base register Low TBRL TBR R/W

0003A3HInterrupt vector table base register High TBRH R/W

0003A4HDelayed Interrupt register DIRR R/W

0003A5HNon Maskable Interrupt register NMI R/W

0003A6H-

0003ABH

Reserved -

0003ACHEDSU communication interrupt selection Low EDSU2L EDSU2 R/W

0003ADHEDSU communication interrupt selection High EDSU2H R/W

0003AEHROM mirror control register ROMM R/W

0003AFHEDSU configuration register EDSU R/W

0003B0HMemory patch control/status register ch 0/1 PFCS0 R/W

0003B1HMemory patch control/status register ch 0/1 R/W

0003B2HMemory patch control/status register ch 2/3 PFCS1 R/W

0003B3HMemory patch control/status register ch 2/3 R/W

I/O map CY96(F)315x (Sheet 7 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 24 of 82

CY96310 Series

0003B4HMemory patch control/status register ch 4/5 PFCS2 R/W

0003B5HMemory patch control/status register ch 4/5 R/W

0003B6HMemory patch control/status register ch 6/7 PFCS3 R/W

0003B7HMemory patch control/status register ch 6/7 R/W

0003B8HMemory Patch function - Patch address 0 low PFAL0 R/W

0003B9HMemory Patch function - Patch address 0 middle PFAM0 R/W

0003BAHMemory Patch function - Patch address 0 high PFAH0 R/W

0003BBHMemory Patch function - Patch address 1 low PFAL1 R/W

0003BCHMemory Patch function - Patch address 1 middle PFAM1 R/W

0003BDHMemory Patch function - Patch address 1 high PFAH1 R/W

0003BEHMemory Patch function - Patch address 2 low PFAL2 R/W

0003BFHMemory Patch function - Patch address 2 middle PFAM2 R/W

0003C0HMemory Patch function - Patch address 2 high PFAH2 R/W

0003C1HMemory Patch function - Patch address 3 low PFAL3 R/W

0003C2HMemory Patch function - Patch address 3 middle PFAM3 R/W

0003C3HMemory Patch function - Patch address 3 high PFAH3 R/W

0003C4HMemory Patch function - Patch address 4 low PFAL4 R/W

0003C5HMemory Patch function - Patch address 4 middle PFAM4 R/W

0003C6HMemory Patch function - Patch address 4 high PFAH4 R/W

0003C7HMemory Patch function - Patch address 5 low PFAL5 R/W

0003C8HMemory Patch function - Patch address 5 middle PFAM5 R/W

0003C9HMemory Patch function - Patch address 5 high PFAH5 R/W

0003CAHMemory Patch function - Patch address 6 low PFAL6 R/W

0003CBHMemory Patch function - Patch address 6 middle PFAM6 R/W

0003CCHMemory Patch function - Patch address 6 high PFAH6 R/W

0003CDHMemory Patch function - Patch address 7 low PFAL7 R/W

0003CEHMemory Patch function - Patch address 7 middle PFAM7 R/W

0003CFHMemory Patch function - Patch address 7 high PFAH7 R/W

0003D0HMemory Patch function - Patch data 0 Low PFDL0 PFD0 R/W

0003D1HMemory Patch function - Patch data 0 High PFDH0 R/W

I/O map CY96(F)315x (Sheet 8 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 25 of 82

CY96310 Series

0003D2HMemory Patch function - Patch data 1 Low PFDL1 PFD1 R/W

0003D3HMemory Patch function - Patch data 1 High PFDH1 R/W

0003D4HMemory Patch function - Patch data 2 Low PFDL2 PFD2 R/W

0003D5HMemory Patch function - Patch data 2 High PFDH2 R/W

0003D6HMemory Patch function - Patch data 3 Low PFDL3 PFD3 R/W

0003D7HMemory Patch function - Patch data 3 High PFDH3 R/W

0003D8HMemory Patch function - Patch data 4 Low PFDL4 PFD4 R/W

0003D9HMemory Patch function - Patch data 4 High PFDH4 R/W

0003DAHMemory Patch function - Patch data 5 Low PFDL5 PFD5 R/W

0003DBHMemory Patch function - Patch data 5 High PFDH5 R/W

0003DCHMemory Patch function - Patch data 6 Low PFDL6 PFD6 R/W

0003DDHMemory Patch function - Patch data 6 High PFDH6 R/W

0003DEHMemory Patch function - Patch data 7 Low PFDL7 PFD7 R/W

0003DFHMemory Patch function - Patch data 7 High PFDH7 R/W

0003E0H-

0003F0H

Reserved -

0003F1HMemory Control Status Register A MCSRA R/W

0003F2HMemory Timing Configuration Register A Low MTCRAL MTCRA R/W

0003F3HMemory Timing Configuration Register A High MTCRAH R/W

0003F4H-

0003F8H

Reserved -

0003F9HFlash Memory Write Control register 1 FMWC1 R/W

0003FAHFlash Memory Write Control register 2 FMWC2 R/W

0003FBHFlash Memory Write Control register 3 FMWC3 R/W

0003FCHFlash Memory Write Control register 4 FMWC4 R/W

0003FDHFlash Memory Write Control register 5 FMWC5 R/W

0003FEH-

0003FFH

Reserved -

000400HStandby Mode control register SMCR R/W

000401HClock select register CKSR R/W

000402HClock Stabilization select register CKSSR R/W

000403HClock monitor register CKMR R

I/O map CY96(F)315x (Sheet 9 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 26 of 82

CY96310 Series

000404HClock Frequency control register Low CKFCRL CKFCR R/W

000405HClock Frequency control register High CKFCRH R/W

000406HPLL Control register Low PLLCRL PLLCR R/W

000407HPLL Control register High PLLCRH R/W

000408HRC clock timer control register RCTCR R/W

000409HMain clock timer control register MCTCR R/W

00040AHSub clock timer control register SCTCR R/W

00040BHReset cause and clock status register with clear function RCCSRC R

00040CHReset configuration register RCR R/W

00040DHReset cause and clock status register RCCSR R

00040EHWatch dog timer configuration register WDTC R/W

00040FHWatch dog timer clear pattern register WDTCP W

000410H-

000414H

Reserved -

000415HClock output activation register COAR R/W

000416HClock output configuration register 0 COCR0 R/W

000417HClock output configuration register 1 COCR1 R/W

000418HClock Modulator control register CMCR R/W

000419HReserved -

00041AHClock Modulator Parameter register Low CMPRL CMPR R/W

00041BHClock Modulator Parameter register High CMPRH R/W

00041CH-

00042BH

Reserved -

00042CHVoltage Regulator Control register VRCR R/W

00042DHClock Input and LVD Control Register CILCR R/W

00042EH-

00042FH

Reserved -

000430HI/O Port P00 - Data Direction Register DDR00 R/W

000431HI/O Port P01 - Data Direction Register DDR01 R/W

000432HI/O Port P02 - Data Direction Register DDR02 R/W

000433HI/O Port P03 - Data Direction Register DDR03 R/W

000434HReserved -

I/O map CY96(F)3 15 x (Sh e et 10 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 27 of 82

CY96310 Series

000435HI/O Port P05 - Data Direction Register DDR05 R/W

000436HI/O Port P06 - Data Direction Register DDR06 R/W

000437HI/O Port P07 - Data Direction Register DDR07 R/W

000438H-

000443H

Reserved -

000444HI/O Port P00 - Port Input Enable Register PIER00 R/W

000445HI/O Port P01 - Port Input Enable Register PIER01 R/W

000446HI/O Port P02 - Port Input Enable Register PIER02 R/W

000447HI/O Port P03 - Port Input Enable Register PIER03 R/W

000448HReserved -

000449HI/O Port P05 - Port Input Enable Register PIER05 R/W

00044AHI/O Port P06 - Port Input Enable Register PIER06 R/W

00044BHI/O Port P07 - Port Input Enable Register PIER07 R/W

00044CH-

000457H

Reserved -

000458HI/O Port P00 - Port Input Level Register PILR00 R/W

000459HI/O Port P01 - Port Input Level Register PILR01 R/W

00045AHI/O Port P02 - Port Input Level Register PILR02 R/W

00045BHI/O Port P03 - Port Input Level Register PILR03 R/W

00045CHReserved -

00045DHI/O Port P05 - Port Input Level Register PILR05 R/W

00045EHI/O Port P06 - Port Input Level Register PILR06 R/W

00045FHI/O Port P07 - Port Input Level Register PILR07 R/W

000460H-

00046BH

Reserved -

00046CHI/O Port P00 - Extended Port Input Level Register EPILR00 R/W

00046DHI/O Port P01 - Extended Port Input Level Register EPILR01 R/W

00046EHI/O Port P02 - Extended Port Input Level Register EPILR02 R/W

00046FHI/O Port P03 - Extended Port Input Level Register EPILR03 R/W

000470HReserved -

000471HI/O Port P05 - Extended Port Input Level Register EPILR05 R/W

000472HI/O Port P06 - Extended Port Input Level Register EPILR06 R/W

I/O map CY96(F)3 15 x (Sh e et 11 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 28 of 82

CY96310 Series

000473HI/O Port P07 - Extended Port Input Level Register EPILR07 R/W

000474H-

00047FH

Reserved -

000480HI/O Port P00 - Port Output Drive Register PODR00 R/W

000481HI/O Port P01 - Port Output Drive Register PODR01 R/W

000482HI/O Port P02 - Port Output Drive Register PODR02 R/W

000483HI/O Port P03 - Port Output Drive Register PODR03 R/W

000484HReserved -

000485HI/O Port P05 - Port Output Drive Register PODR05 R/W

000486HI/O Port P06 - Port Output Drive Register PODR06 R/W

000487HI/O Port P07 - Port Output Drive Register PODR07 R/W

000488H-

0004A7H

Reserved -

0004A8HI/O Port P00 - Pull-Up resistor Control Register PUCR00 R/W

0004A9HI/O Port P01 - Pull-Up resistor Control Register PUCR01 R/W

0004AAHI/O Port P02 - Pull-Up resistor Control Register PUCR02 R/W

0004ABHI/O Port P03 - Pull-Up resistor Control Register PUCR03 R/W

0004ACHReserved -

0004ADHI/O Port P05 - Pull-Up resistor Control Register PUCR05 R/W

0004AEHI/O Port P06 - Pull-Up resistor Control Register PUCR06 R/W

0004AFHI/O Port P07 - Pull-Up resistor Control Register PUCR07 R/W

0004B0H-

0004BBH

Reserved -

0004BCHI/O Port P00 - External Pin State Register EPSR00 R

0004BDHI/O Port P01 - External Pin State Register EPSR01 R

0004BEHI/O Port P02 - External Pin State Register EPSR02 R

0004BFHI/O Port P03 - External Pin State Register EPSR03 R

0004C0HReserved -

0004C1HI/O Port P05 - External Pin State Register EPSR05 R

0004C2HI/O Port P06 - External Pin State Register EPSR06 R

0004C3HI/O Port P07 - External Pin State Register EPSR07 R

I/O map CY96(F)3 15 x (Sh e et 12 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 29 of 82

CY96310 Series

0004C4H-

0004CFH

Reserved -

0004D0HADC analog input enable register 0 ADER0 R/W

0004D1HADC analog input enable register 1 ADER1 R/W

0004D2HADC analog input enable register 2 ADER2 R/W

0004D3HADC analog input enable register 3 ADER3 R/W

0004D4HADC analog input enable register 4 ADER4 R/W

0004D5HReserved -

0004D6HPeripheral Resource Relocation Register 0 PRRR0 R/W

0004D7HPeripheral Resource Relocation Register 1 PRRR1 R/W

0004D8HPeripheral Resource Relocation Register 2 PRRR2 R/W

0004D9HPeripheral Resource Relocation Register 3 PRRR3 R/W

0004DAHPeripheral Resource Relocation Register 4 PRRR4 R/W

0004DBHPeripheral Resource Relocation Register 5 PRRR5 R/W

0004DCHPeripheral Resource Relocation Register 6 PRRR6 R/W

0004DDHPeripheral Resource Relocation Register 7 PRRR7 R/W

0004DEHPeripheral Resource Relocation Register 8 PRRR8 R/W

0004DFHPeripheral Resource Relocation Register 9 PRRR9 R/W

0004E0HRTC - Sub Second Register L WTBRL0 WTBR0 R/W

0004E1HRTC - Sub Second Register M WTBRH0 R/W

0004E2HRTC - Sub-Second Register H WTBR1 R/W

0004E3HRTC - Second Register WTSR R/W

0004E4HRTC - Minutes WTMR R/W

0004E5HRTC - Hour WTHR R/W

0004E6HRTC - Timer Control Extended Register WTCER R/W

0004E7HRTC - Clock select register WTCKSR R/W

0004E8HRTC - Timer Control Register Low WTCRL WTCR R/W

0004E9HRTC - Timer Control Register High WTCRH R/W

0004EAHCAL - Calibration unit Control register CUCR R/W

0004EBHReserved -

0004ECHCAL - Duration Timer Data Register Low CUTDL CUTD R/W

I/O map CY96(F)3 15 x (Sh e et 13 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 30 of 82

CY96310 Series

0004EDHCAL - Duration Timer Data Register High CUTDH R/W

0004EEHCAL - Calibration Timer Register 2 Low CUTR2L CUTR2 R

0004EFHCAL - Calibration Timer Register 2 High CUTR2H R

0004F0HCAL - Calibration Timer Register 1 Low CUTR1L CUTR1 R

0004F1HCAL - Calibration Timer Register 1 High CUTR1H R

0004F2H-

0004F9H

Reserved -

0004FAHRLT - Timer input select (for Cascading) TMISR R/W

0004FBH-00

04FFH

Reserved -

000500HFRT2 - Data register of free-running timer TCDT2 R/W

000501HFRT2 - Data register of free-running timer R/W

000502HFRT2 - Control status register of free-running timer Low TCCSL2 TCCS2 R/W

000503HFRT2 - Control status register of free-running timer High TCCSH2 R/W

000504HFRT3 - Data register of free-running timer TCDT3 R/W

000505HFRT3 - Data register of free-running timer R/W

000506HFRT3 - Control status register of free-running timer Low TCCSL3 TCCS3 R/W

000507HFRT3 - Control status register of free-running timer High TCCSH3 R/W

000508H-

000513H

Reserved -

000514HICU8/ICU9 - Control Status Register ICS89 R/W

000515HICU8/ICU9 - Edge Register ICE89 R/W

000516HICU8 - Capture Register Low IPCPL8 IPCP8 R

000517HICU8 - Capture Register High IPCPH8 R

000518HICU9 - Capture Register Low IPCPL9 IPCP9 R

000519HICU9 - Capture Register High IPCPH9 R

00051AHICU10/ICU11 - Control Status Register ICS1011 R/W

00051BHICU10/ICU11 - Edge Register ICE1011 R/W

00051CHICU10 - Capture Register Low IPCPL10 IPCP10 R

00051DHICU10 - Capture Register High IPCPH10 R

00051EHICU11 - Capture Register Low IPCPL11 IPCP11 R

00051FHICU11 - Capture Register High IPCPH11 R

I/O map CY96(F)3 15 x (Sh e et 14 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 31 of 82

CY96310 Series

000520H-

00053DH

Reserved -

00053EHUSART7 - Serial Mode Register SMR7 R/W

00053FHUSART7 - Serial Control Register SCR7 R/W

000540HUSART7 - Serial TX Register TDR7 W

000540HUSART7 - Serial RX Register RDR7 R

000541HUSART7 - Serial Status Register SSR7 R/W

000542HUSART7 - Ext. Control/Com. Register ECCR7 R/W

000543HUSART7 - Ext. Status Com. Register ESCR7 R/W

000544HUSART7 - Baud Rate Generator Register Low BGRL7 BGR7 R/W

000545HUSART7 - Baud Rate Generator Register High BGRH7 R/W

000546HUSART7 - Extended Serial Interrupt Register ESIR7 R/W

000547HReserved -

000548HUSART8 - Serial Mode Register SMR8 R/W

000549HUSART8 - Serial Control Register SCR8 R/W

00054AHUSART8 - Serial TX Register TDR8 W

00054AHUSART8 - Serial RX Register RDR8 R

00054BHUSART8 - Serial Status Register SSR8 R/W

00054CHUSART8 - Ext. Control/Com. Register ECCR8 R/W

00054DHUSART8 - Ext. Status Com. Register ESCR8 R/W

00054EHUSART8 - Baud Rate Generator Register Low BGRL8 BGR8 R/W

00054FHUSART8 - Baud Rate Generator Register High BGRH8 R/W

000550HUSART8 - Extended Serial Interrupt Register ESIR8 R/W

000551H-

000563H

Reserved -

000564HPPG6 - Timer register PTMR6 R

000565HPPG6 - Timer register R

000566HPPG6 - Period setting register PCSR6 W

000567HPPG6 - Period setting register W

000568HPPG6 - Duty cycle register PDUT6 W

000569HPPG6 - Duty cycle register W

I/O map CY96(F)3 15 x (Sh e et 15 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 32 of 82

CY96310 Series

00056AHPPG6 - Control status register Low PCNL6 PCN6 R/W

00056BHPPG6 - Control status register High PCNH6 R/W

00056CHPPG7 - Timer register PTMR7 R

00056DHPPG7 - Timer register R

00056EHPPG7 - Period setting register PCSR7 W

00056FHPPG7 - Period setting register W

000570HPPG7 - Duty cycle register PDUT7 W

000571HPPG7 - Duty cycle register W

000572HPPG7 - Control status register Low PCNL7 PCN7 R/W

000573HPPG7 - Control status register High PCNH7 R/W

000574HPPG11-PPG8 - General Control register 1 Low GCN1L2 GCN12 R/W

000575HPPG11-PPG8 - General Control register 1 High GCN1H2 R/W

000576HPPG11-PPG8 - General Control register 2 Low GCN2L2 GCN22 R/W

000577HPPG11-PPG8 - General Control register 2 High GCN2H2 R/W

000578HPPG8 - Timer register PTMR8 R

000579HPPG8 - Timer register R

00057AHPPG8 - Period setting register PCSR8 W

00057BHPPG8 - Period setting register W

00057CHPPG8 - Duty cycle register PDUT8 W

00057DHPPG8 - Duty cycle register W

00057EHPPG8 - Control status register Low PCNL8 PCN8 R/W

00057FHPPG8 - Control status register High PCNH8 R/W

000580HPPG9 - Timer register PTMR9 R

000581HPPG9 - Timer register R

000582HPPG9 - Period setting register PCSR9 W

000583HPPG9 - Period setting register W

000584HPPG9 - Duty cycle register PDUT9 W

000585HPPG9 - Duty cycle register W

000586HPPG9 - Control status register Low PCNL9 PCN9 R/W

000587HPPG9 - Control status register High PCNH9 R/W

I/O map CY96(F)3 15 x (Sh e et 16 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 33 of 82

CY96310 Series

000588H-

000597H

Reserved -

000598HPPG15-PPG12 - General Control register 1 Low GCN1L3 GCN13 R/W

000599HPPG15-PPG12 - General Control register 1 High GCN1H3 R/W

00059AHPPG15-PPG12 - General Control register 2 Low GCN2L3 GCN23 R/W

00059BHPPG15-PPG12 - General Control register 2 High GCN2H3 R/W

00059CHPPG12 - Timer register PTMR12 R

00059DHPPG12 - Timer register R

00059EHPPG12 - Period setting register PCSR12 W

00059FHPPG12 - Period setting register W

0005A0HPPG12 - Duty cycle register PDUT12 W

0005A1HPPG12 - Duty cycle register W

0005A2HPPG12 - Control status register Low PCNL12 PCN12 R/W

0005A3HPPG12 - Control status register High PCNH12 R/W

0005A4H-

0005ABH

Reserved -

0005ACHPPG14 - Timer register PTMR14 R

0005ADHPPG14 - Timer register R

0005AEHPPG14 - Period setting register PCSR14 W

0005AFHPPG14 - Period setting register W

0005B0HPPG14 - Duty cycle register PDUT14 W

0005B1HPPG14 - Duty cycle register W

0005B2HPPG14 - Control status register Low PCNL14 PCN14 R/W

0005B3HPPG14 - Control status register High PCNH14 R/W

0005B4H-

0005BBH

Reserved -

0005BCHPPG19-PPG16 - General Control register 1 Low GCN1L4 GCN14 R/W

0005BDHPPG19-PPG16 - General Control register 1 High GCN1H4 R/W

0005BEHPPG19-PPG16 - General Control register 2 Low GCN2L4 GCN24 R/W

0005BFHPPG19-PPG16 - General Control register 2 High GCN2H4 R/W

0005C0HPPG16 - Timer register PTMR16 R

0005C1HPPG16 - Timer register R

I/O map CY96(F)3 15 x (Sh e et 17 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 34 of 82

CY96310 Series

0005C2HPPG16 - Period setting register PCSR16 W

0005C3HPPG16 - Period setting register W

0005C4HPPG16 - Duty cycle register PDUT16 W

0005C5HPPG16 - Duty cycle register W

0005C6HPPG16 - Control status register Low PCNL16 PCN16 R/W

0005C7HPPG16 - Control status register High PCNH16 R/W

0005C8HPPG17 - Timer register PTMR17 R

0005C9HPPG17 - Timer register R

0005CAHPPG17 - Period setting register PCSR17 W

0005CBHPPG17 - Period setting register W

0005CCHPPG17 - Duty cycle register PDUT17 W

0005CDHPPG17 - Duty cycle register W

0005CEHPPG17 - Control status register Low PCNL17 PCN17 R/W

0005CFHPPG17 - Control status register High PCNH17 R/W

0005D0HPPG18 - Timer register PTMR18 R

0005D1HPPG18 - Timer register R

0005D2HPPG18 - Period setting register PCSR18 W

0005D3HPPG18 - Period setting register W

0005D4HPPG18 - Duty cycle register PDUT18 W

0005D5HPPG18 - Duty cycle register W

0005D6HPPG18 - Control status register Low PCNL18 PCN18 R/W

0005D7HPPG18 - Control status register High PCNH18 R/W

0005D8HPPG19 - Timer register PTMR19 R

0005D9HPPG19 - Timer register R

0005DAHPPG19 - Period setting register PCSR19 W

0005DBHPPG19 - Period setting register W

0005DCHPPG19 - Duty cycle register PDUT19 W

0005DDHPPG19 - Duty cycle register W

0005DEHPPG19 - Control status register Low PCNL19 PCN19 R/W

0005DFHPPG19 - Control status register High PCNH19 R/W

I/O map CY96(F)3 15 x (Sh e et 18 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 35 of 82

CY96310 Series

0005E0H-

00065FH

Reserved -

000660HPeripheral Resource Relocation Register 10 PRRR10 R/W

000661HPeripheral Resource Relocation Register 11 PRRR11 R/W

000662HPeripheral Resource Relocation Register 12 PRRR12 R/W

000663HPeripheral Resource Relocation Register 13 PRRR13 W

000664H-

0008FFH

Reserved -

000900HCAN2 - Control register Low CTRLRL2 CTRLR2 R/W

000901HCAN2 - Control register High (reserved) CTRLRH2 R

000902HCAN2 - Status register Low STATRL2 STATR2 R/W

000903HCAN2 - Status register High (reserved) STATRH2 R

000904HCAN2 - Error Counter Low (Transmit) ERRCNTL2 ERRCNT2 R

000905HCAN2 - Error Counter High (Receive) ERRCNTH2 R

000906HCAN2 - Bit Timing Register Low BTRL2 BTR2 R/W

000907HCAN2 - Bit Timing Register High BTRH2 R/W

000908HCAN2 - Interrupt Register Low INTRL2 INTR2 R

000909HCAN2 - Interrupt Register High INTRH2 R

00090AHCAN2 - Test Register Low TESTRL2 TESTR2 R/W

00090BHCAN2 - Test Register High (reserved) TESTRH2 R

00090CHCAN2 - BRP Extension register Low BRPERL2 BRPER2 R/W

00090DHCAN2 - BRP Extension register High (reserved) BRPERH2 R

00090EH-

00090FH

Reserved -

000910HCAN2 - IF1 Command request register Low IF1CREQL2 IF1CREQ2 R/W

000911HCAN2 - IF1 Command request register High IF1CREQH2 R/W

000912HCAN2 - IF1 Command Mask register Low IF1CMSKL2 IF1CMSK2 R/W

000913HCAN2 - IF1 Command Mask register High (reserved) IF1CMSKH2 R

000914HCAN2 - IF1 Mask 1 Register Low IF1MSK1L2 IF1MSK12 R/W

000915HCAN2 - IF1 Mask 1 Register High IF1MSK1H2 R/W

000916HCAN2 - IF1 Mask 2 Register Low IF1MSK2L2 IF1MSK22 R/W

000917HCAN2 - IF1 Mask 2 Register High IF1MSK2H2 R/W

I/O map CY96(F)3 15 x (Sh e et 19 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 36 of 82

CY96310 Series

000918HCAN2 - IF1 Arbitration 1 Register Low IF1ARB1L2 IF1ARB12 R/W

000919HCAN2 - IF1 Arbitration 1 Register High IF1ARB1H2 R/W

00091AHCAN2 - IF1 Arbitration 2 Register Low IF1ARB2L2 IF1ARB22 R/W

00091BHCAN2 - IF1 Arbitration 2 Register High IF1ARB2H2 R/W

00091CHCAN2 - IF1 Message Control Register Low IF1MCTRL2 IF1MCTR2 R/W

00091DHCAN2 - IF1 Message Control Register High IF1MCTRH2 R/W

00091EHCAN2 - IF1 Data A1 Low IF1DTA1L2 IF1DTA12 R/W

00091FHCAN2 - IF1 Data A1 High IF1DTA1H2 R/W

000920HCAN2 - IF1 Data A2 Low IF1DTA2L2 IF1DTA22 R/W

000921HCAN2 - IF1 Data A2 High IF1DTA2H2 R/W

000922HCAN2 - IF1 Data B1 Low IF1DTB1L2 IF1DTB12 R/W

000923HCAN2 - IF1 Data B1 High IF1DTB1H2 R/W

000924HCAN2 - IF1 Data B2 Low IF1DTB2L2 IF1DTB22 R/W

000925HCAN2 - IF1 Data B2 High IF1DTB2H2 R/W

000926H-

00093FH

Reserved -

000940HCAN2 - IF2 Command request register Low IF2CREQL2 IF2CREQ2 R/W

000941HCAN2 - IF2 Command request register High IF2CREQH2 R/W

000942HCAN2 - IF2 Command Mask register Low IF2CMSKL2 IF2CMSK2 R/W

000943HCAN2 - IF2 Command Mask register High (reserved) IF2CMSKH2 R

000944HCAN2 - IF2 Mask 1 Register Low IF2MSK1L2 IF2MSK12 R/W

000945HCAN2 - IF2 Mask 1 Register High IF2MSK1H2 R/W

000946HCAN2 - IF2 Mask 2 Register Low IF2MSK2L2 IF2MSK22 R/W

000947HCAN2 - IF2 Mask 2 Register High IF2MSK2H2 R/W

000948HCAN2 - IF2 Arbitration 1 Register Low IF2ARB1L2 IF2ARB12 R/W

000949HCAN2 - IF2 Arbitration 1 Register High IF2ARB1H2 R/W

00094AHCAN2 - IF2 Arbitration 2 Register Low IF2ARB2L2 IF2ARB22 R/W

00094BHCAN2 - IF2 Arbitration 2 Register High IF2ARB2H2 R/W

00094CHCAN2 - IF2 Message Control Register Low IF2MCTRL2 IF2MCTR2 R/W

00094DHCAN2 - IF2 Message Control Register High IF2MCTRH2 R/W

00094EHCAN2 - IF2 Data A1 Low IF2DTA1L2 IF2DTA12 R/W

I/O map CY96(F)3 15 x (Sh e et 20 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 37 of 82

CY96310 Series

00094FHCAN2 - IF2 Data A1 High IF2DTA1H2 R/W

000950HCAN2 - IF2 Data A2 Low IF2DTA2L2 IF2DTA22 R/W

000951HCAN2 - IF2 Data A2 High IF2DTA2H2 R/W

000952HCAN2 - IF2 Data B1 Low IF2DTB1L2 IF2DTB12 R/W

000953HCAN2 - IF2 Data B1 High IF2DTB1H2 R/W

000954HCAN2 - IF2 Data B2 Low IF2DTB2L2 IF2DTB22 R/W

000955HCAN2 - IF2 Data B2 High IF2DTB2H2 R/W

000956H-

00097FH

Reserved -

000980HCAN2 - Transmission Request 1 Register Low TREQR1L2 TREQR12 R

000981HCAN2 - Transmission Request 1 Register High TREQR1H2 R

000982HCAN2 - Transmission Request 2 Register Low TREQR2L2 TREQR22 R

000983HCAN2 - Transmission Request 2 Register High TREQR2H2 R

000984H-

00098FH

Reserved -

000990HCAN2 - New Data 1 Register Low NEWDT1L2 NEWDT12 R

000991HCAN2 - New Data 1 Register High NEWDT1H2 R

000992HCAN2 - New Data 2 Register Low NEWDT2L2 NEWDT22 R

000993HCAN2 - New Data 2 Register High NEWDT2H2 R

000994H-

00099FH

Reserved -

0009A0HCAN2 - Interrupt Pending 1 Register Low INTPND1L2 INTPND12 R

0009A1HCAN2 - Interrupt Pending 1 Register High INTPND1H2 R

0009A2HCAN2 - Interrupt Pending 2 Register Low INTPND2L2 INTPND22 R

0009A3HCAN2 - Interrupt Pending 2 Register High INTPND2H2 R

0009A4H-

0009AFH

Reserved -

0009B0HCAN2 - Message Valid 1 Register Low MSGVAL1L2 MSGVAL12 R

0009B1HCAN2 - Message Valid 1 Register High MSGVAL1H2 R

0009B2HCAN2 - Message Valid 2 Register Low MSGVAL2L2 MSGVAL22 R

0009B3HCAN2 - Message Valid 2 Register High MSGVAL2H2 R

I/O map CY96(F)3 15 x (Sh e et 21 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 38 of 82

CY96310 Series

Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results

in reading ‘X’.

Registers of resources which are described in this table, but which are not supported by the device, should also be handled

as “Reserved”.

0009B4H-

0009CDH

Reserved -

0009CEHCAN2 - Output enable register COER2 R/W

0009CFH-

000BFFH

Reserved -

I/O map CY96(F)3 15 x (Sh e et 22 of 22)

Address Register Abbreviation

8-bit access Abbreviation

16-bit access Access

Document Number: 002-04592 Rev. *B Page 39 of 82

CY96310 Series

12. Interrupt Vector Table

Vector

number Offset in

vector table Vector name Cleared by

DMA Index in ICR

to program Description

03FC

HCALLV0 No -

13F8

HCALLV1 No -

23F4

HCALLV2 No -

33F0

HCALLV3 No -

43EC

HCALLV4 No -

53E8

HCALLV5 No -

63E4

HCALLV6 No -

73E0

HCALLV7 No -

83DC

HRESET No -

93D8

HINT9 No -

10 3D4HEXCEPTION No -

11 3D0HNMI No - Non-Maskable Interrupt

12 3CCHDLY No 12 Delayed Interrupt

13 3C8HRC_TIMER No 13 RC Timer

14 3C4HMC_TIMER No 14 Main Clock Timer

15 3C0HSC_TIMER No 15 Sub Clock Timer

16 3BCHPLL_UNLOCK No 16 Reserved

17 3B8HEXTINT0 Yes 17 External Interrupt 0

18 3B4HReserved

19 3B0HEXTINT2 Yes 19 External Interrupt 2

20 3ACHEXTINT3 Yes 20 External Interrupt 3

21 3A8HEXTINT4 Yes 21 External Interrupt 4

22 3A4HReserved

23 3A0HEXTINT7 Yes 23 External Interrupt 7

24 39CHEXTINT8 Yes 24 External Interrupt 8

25 398HEXTINT9 Yes 25 External Interrupt 9

26 394HEXTINT10 Yes 26 External Interrupt 10

27 390HEXTINT11 Yes 27 External Interrupt 11

28 38CHEXTINT12 Yes 28 External Interrupt 12

29 388HEXTINT13 Yes 29 External Interrupt 13

30 384HReserved

31 380HReserved

32 37CHReserved

33 378HCAN2 No 33 CAN Controller 2

34 374HPPG0 Yes 34 Programmable Pulse Generator 0

35 370HPPG1 Yes 35 Programmable Pulse Generator 1

Document Number: 002-04592 Rev. *B Page 40 of 82

CY96310 Series

36 36CHReserved

37 368HPPG3 Yes 37 Programmable Pulse Generator 3

38 364HPPG4 Yes 38 Programmable Pulse Generator 4

39 360 Reserved

40 35CHPPG6 Yes 40 Programmable Pulse Generator 6

41 358HPPG7 Yes 41 Programmable Pulse Generator 7

42 354HPPG8 Yes 42 Programmable Pulse Generator 8

43 350HPPG9 Yes 43 Programmable Pulse Generator 9

44 34CHReserved

45 348HReserved

46 344HPPG12 Yes 46 Programmable Pulse Generator 12

47 340HReserved

48 33CHPPG14 Yes 48 Programmable Pulse Generator 14

49 338HReserved

50 334HPPG16 Yes 50 Programmable Pulse Generator 16

51 330HPPG17 Yes 51 Programmable Pulse Generator 17

52 32CHPPG18 Yes 52 Programmable Pulse Generator 18

53 328HPPG19 Yes 53 Programmable Pulse Generator 19

54 324HRLT0 Yes 54 Reload Timer 0

55 320HRLT1 Yes 55 Reload Timer 1

56 31CHRLT2 Yes 56 Reload Timer 2

57 318HRLT3 Yes 57 Reload Timer 3

58 314HPPGRLT Yes 58 Reload Timer 6 - dedicated for PPG

59 310HICU0 Yes 59 Input Capture Unit 0

60 30CHICU1 Yes 60 Input Capture Unit 1

61 308HReserved

62 304HReserved

63 300HICU4 Yes 63 Input Capture Unit 4

64 2FCHICU5 Yes 64 Input Capture Unit 5

65 2F8HICU6 Yes 65 Input Capture Unit 6

66 2F4HReserved

67 2F0HReserved

68 2ECHICU9 Yes 68 Input Capture Unit 9

69 2E8HICU10 Yes 69 Input Capture Unit 10

70 2E4HReserved

71 2E0HReserved

72 2DCHReserved

Vector

number Offset in

vector table Vector name Cleared by

DMA Index in ICR

to program Description

Document Number: 002-04592 Rev. *B Page 41 of 82

CY96310 Series

73 2D8HOCU6 Yes 73 Output Compare Unit 6

74 2D4HOCU7 Yes 74 Output Compare Unit 7

75 2D0HReserved

76 2CCHReserved

77 2C8HFRT0 Yes 77 Free Running Timer 0

78 2C4HFRT1 Yes 78 Free Running Timer 1

79 2C0HFRT2 Yes 79 Free Running Timer 2

80 2BCHFRT3 Yes 80 Free Running Timer 3

81 2B8HRTC0 No 81 Real Timer Clock

82 2B4HCAL0 No 82 Clock Calibration Unit

83 2B0HReserved

84 2ACHADC0 Yes 84 A/D Converter

85 2A8HLINR2 Yes 85 LIN USART 2 RX

86 2A4HLINT2 Yes 86 LIN USART 2 TX

87 2A0HReserved

88 29CHReserved

89 298HLINR7 Yes 89 LIN USART 7 RX

90 294HLINT7 Yes 90 LIN USART 7 TX

91 290HLINR8 Yes 91 LIN USART 8 RX

92 28CHLINT8 Yes 92 LIN USART 8 TX

93 288HFLASH_A No 93 Flash memory A (only Flash devices)

Vector

number Offset in

vector table Vector name Cleared by

DMA Index in ICR

to program Description

Document Number: 002-04592 Rev. *B Page 42 of 82

CY96310 Series

13. Handling Devices

Special care is required for the following when handling the device:

• Latch-up prevention

• Unused pins handling

• External clock usage

• Unused sub clock signal

• Notes on PLL clock mode operation

• Power supply pins (VCC/VSS)

• Crystal oscillator circuit

• Turn on sequence of power supply to A/D converter and analog inputs

• Pin handling when not using the A/D converter

• Notes on energization

• Stabilization of power supply voltage

• Serial communication

13.1 Latch-up prevention

CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.

Latch-up may increase the power supply current dramatically, causing thermal damages to the device.

13.2 Unused pins handling

Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).

Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device.

They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 kΩ.

Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or

external pull-up/pull-down resistor as described above.

13.3 External clock usage

The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for

detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:

1. Single phase external clock

• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.

Document Number: 002-04592 Rev. *B Page 43 of 82

CY96310 Series

2. Opposite phase external clock

• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to

the X0 (X0A) pins.

13.4 Unused sub clock signal

If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin

must be left open.

13.5 Notes on PLL cloc k mode operation

If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts

to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.

13.6 Power supply pins (VCC/VSS)

It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or

VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.

VCC and VSS must be connected to the device from the power supply with lowest possible impedance.

As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 μF between VCC and VSS as close

as possible to VCC and VSS pins.

13.7 Crystal oscillator and ceramic resonator circuit

Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest

possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost

effort, that the lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area

for stabilizing the operation.

It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially

when using low-Q resonators at higher frequencies.

13.8 Turn on sequence of power supply to A/D converter and analog inputs

It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power

supply (VCC) on.

It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage

must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).

13.9 Pin handling when not using the A/D converter

It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.

13.10 Notes on Powe r-o n

To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than

50μs from 0.2 V to 2.7 V.

Document Number: 002-04592 Rev. *B Page 44 of 82

CY96310 Series

13.11 Stabilization of power supply voltage

If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may

occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be

stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10%

of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/μs or less in instantaneous fluctuation for

power supply switching.

13.12 Serial communic atio n

There is a possibility to receive wrong data due to noise or other causes on the serial communication.

Therefore, design a printed circuit board so as to avoid noise.

Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error

occurs.

Document Number: 002-04592 Rev. *B Page 45 of 82

CY96310 Series

14. Electrical Characteristics

14.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage

VCC VSS - 0.3 VSS + 6.0 V

AVCC VSS - 0.3 VSS + 6.0 VVCC = AVCC *1

AD Converter voltage references AVRH,

AVRL VSS - 0.3 VSS + 6.0 VAVCC ≥ AVRH, AVCC ≥ AVRL, AVRH

> AVRL, AVRL ≥ AVSS

Input voltage VIVSS - 0.3 VSS + 6.0 VVI ≤ VCC + 0.3V *2

Output voltage VOVSS - 0.3 VSS + 6.0 VVO ≤ VCC + 0.3V *2

Maximum Clamp Current ICLAMP -4.0 +4.0 mA Applicable to general purpose

I/O pins *3

Total Maximum Clamp Current Σ|ICLAMP|-40mA

Applicable to general purpose

I/O pins *3

“L” level maximum output current IOL1 - 15 mA Normal outputs with driving strength

set to 5mA

“L” level average output current IOLAV1 - 5 mA Normal outputs with driving strength

set to 5mA

“L” level maximum overall output current ΣIOL1 - 100 mA Normal outputs

“L” level average overall output current ΣIOLAV1 - 50 mA Normal outputs

”H” level maximum output current IOH1 - -15 mA Normal outputs with driving strength

set to 5mA

”H” level average output current IOHAV1 - -5 mA Normal outputs with driving strength

set to 5mA

”H” level maximum overall output current ΣIOH1 - -100 mA Normal outputs

”H” level average overall output current ΣIOHAV1 - -50 mA Normal outputs

Permitted Power dissipation (Flash devices) *4 PD

-220*5 mW TA = 105oC

-450*5 mW TA = 85oC

-615*5 mW TA = 70oC

-280*5 mW TA=125oC, no Flash program/

erase *6

-500*5 mW TA=105oC, no Flash program/

erase *6

Operating ambient temperature TA

0+70

CY96V300C

-40 +105

-40 +125 *6

Storage temperature TSTG -55 +150 oC

Document Number: 002-04592 Rev. *B Page 46 of 82

CY96310 Series

*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog

inputs does not exceed AVCC neither when the power is switched on.

*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current

to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output

voltages of standard ports depend on VCC.

*3: • Applicable to all general purpose I/O pins (Pnn_m)

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller

pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass

through the protective diode and increase the potential at the VCC pin, and this may affect other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided

from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage

may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode).

• Sample recommended circuits:

*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance

of the package on the PCB.

The actual power dissipation depends on the customer application and can be calculated as follows:

PD = PIO + PINT

PIO = Σ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)

PINT = VCC * (ICC + IA) (internal power dissipation)

ICC is the total core current consumption into VCC as described in the “3. DC characteristics” and depends on the selected

operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator.

IA is the analog current consumption into AVCC.

*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.

*6: Please contact Cypress for reliability limitations when using under these conditions.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in

excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

Protective Diode

Limiting

resistance

+B input (0V to 16V)

Document Number: 002-04592 Rev. *B Page 47 of 82

CY96310 Series

14.2 Recommended Operating Conditions

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor

device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.

Users considering application outside the listed conditions are advised to contact their representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage VCC 3.0 - 5.5 V

Smoothing capacitor at C pin CS3.5 4.7 15 μF

Use a X7R ceramic capacitor or a

capacitor that has similar frequency

characteristics

Document Number: 002-04592 Rev. *B Page 48 of 82

CY96310 Series

14.3 DC characteristics

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Input H voltage

VIH

Port inputs

Pnn_m

CMOS Hysteresis

0.7/0.3 input

selected

0.7

VCC -VCC +

0.3 VVCC ≥ 4.5V

0.74

VCC -VCC +

0.3 VVCC < 4.5V

AUTOMOTIVE

Hysteresis input

selected

0.8

VCC -VCC +

0.3 V

VIHX0F X0

External clock in

“Fast Clock Input

mode”

0.8

VCC -VCC +

0.3 V

VIHX0S X0,X1,

X0A,X1A

External clock in

“oscillation mode” 2.5 - VCC +

0.3 V

VIHR RSTX - 0.8

VCC -VCC +

0.3 V CMOS Hysteresis input

VIHM MD2-MD0 - VCC -

0.3 -VCC +

0.3 V

Input L voltage

VIL

Port inputs

Pnn_m

CMOS Hysteresis

0.7/0.3 input

selected

VSS -

0.3 -0.3

VCC V

AUTOMOTIVE

Hysteresis input

selected

VSS -

0.3 -0.5

VCC VVCC ≥ 4.5V

VSS -

0.3 -0.46

VCC VCC < 4.5V

VILX0F X0

External clock in

“Fast Clock Input

mode”

VSS -

0.3 -0.2 VCC V

VILX0S X0,X1,

X0A,X1A

External clock in

“oscillation mode”

VSS -

0.3 -0.4V

VILR RSTX - VSS -

0.3 -0.2 VCC V CMOS Hysteresis input

VILM MD2-MD0 - VSS -

0.3 -VSS +

0.3 V

Output H voltage

VOH2 Normal

outputs

4.5V ≤ VCC ≤ 5.5V

IOH = -2mA VCC -

0.5 --V

Driving strength set to

2mA

(PODR:OD=1)

3.0V ≤ VCC < 4.5V

IOH = -1.6mA

VOH5 Normal

outputs

4.5V ≤ VCC ≤ 5.5V

IOH = -5mA VCC -

0.5 --V

Driving strength set to

5mA

(PODR:OD=0)

3.0V ≤ VCC < 4.5V

IOH = -3mA

Document Number: 002-04592 Rev. *B Page 49 of 82

CY96310 Series

Output L voltage

VOL2 Normal

outputs

4.5V ≤ VCC ≤ 5.5V

IOL = +2mA

--0.4V

Driving strength set to

2mA

(PODR:OD=1)

3.0V ≤ VCC < 4.5V

IOL = +1.6mA

VOL5 Normal

outputs

4.5V ≤ VCC ≤ 5.5V

IOL = +5mA

--0.4V

Driving strength set to

5mA

(PODR:OD=0)

3.0V ≤ VCC < 4.5V

IOL = +3mA

Input leak current IIL Pnn_m

VSS < VI < VCC

AVSS, AVRL < VI <

AVCC, AVRH

-1 - +1 μA Single port pin

Pull-up resistance RUP Pnn_m,

RSTX

VCC = 3.3V ± 10%40 100 160 kΩ

VCC = 5.0V ± 10%25 50 100 kΩ

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Condition Value Unit Remarks

Min Typ Max

Document Number: 002-04592 Rev. *B Page 50 of 82

CY96310 Series

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Condition (at TA)Value Unit Remarks

Typ Max

Power supply

current in

Run modes*

ICCPLL

PLL Run mode with

CLKS1/2 = CLKB =

CLKP1 = 16MHz,

CLKP2 = 8MHz

1 Flash/ROM wait state

(CLKRC and CLKSC stopped)

+25°C 14.5 19.5

+125°C 16 23

PLL Run mode with

CLKS1/2 = CLKB =

CLKP1 = 32MHz,

CLKP2 = 16MHz

2 Flash/ROM wait states

(CLKRC and CLKSC stopped)

+25°C 23 29

+125°C 25 33

PLL Run mode with

CLKS1/2 = 48MHz,

CLKB = CLKP1/2 = 24MHz

0 Flash/ROM wait states

(CLKRC and CLKSC stopped)

+25°C 26 38

+125°C 28 42

PLL Run mode with

CLKS1/2 = CLKB =

CLKP1= 56MHz,

CLKP2 = 28MHz

2 Flash/ROM wait states

(CLKRC and CLKSC stopped.

Core voltage at 1.9V)

+25°C 40 51

+125°C 42 55

PLL Run mode with

CLKS1/2 = 96MHz,

CLKB = CLKP1= 48MHz,

CLKP2 = 24MHz

1 Flash/ROM wait state

(CLKRC and CLKSC stopped.

Core voltage at 1.9V)

+25°C 43 56

+125°C 45 60

Document Number: 002-04592 Rev. *B Page 51 of 82

CY96310 Series

Power supply

current in

Run modes*

ICCMAIN

Main Run mode with

CLKS1/2 = CLKB =

CLKP1/2 = 4MHz

1 Flash/ROM wait state

(CLKPLL, CLKSC and CLKRC

stopped)

+25°C 4 5

+125°C 4.7 8

ICCRCH

RC Run mode with

CLKS1/2 = CLKB =

CLKP1/2 = 2MHz

1 Flash/ROM wait state

(CLKMC, CLKPLL and

CLKSC stopped)

+25°C 2.5 3.5

+125°C 3.2 6.5

ICCRCL

RC Run mode with

CLKS1/2 = CLKB =

CLKP1/2 = 100kHz,

SMCR:LPMS = 0

1 Flash/ROM wait state

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in high power mode)

+25°C 0.18 0.3

+125°C 0.73 3.1

RC Run mode with

CLKS1/2 = CLKB =

CLKP1/2 = 100kHz,

SMCR:LPMS = 1

1 Flash/ROM wait state

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in low power mode,

no Flash programming/

erasing allowed)

+25°C 0.15 0.25

+125°C 0.7 3.05

ICCSUB

Sub Run mode with

CLKS1/2 = CLKB =

CLKP1/2 = 32kHz

1 Flash/ROM wait state

(CLKMC, CLKPLL and

CLKRC stopped, no Flash

programming/erasing

allowed)

+25°C 0.1 0.2

+125°C 0.65 3

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Condition (at TA)Value Unit Remarks

Typ Max

Document Number: 002-04592 Rev. *B Page 52 of 82

CY96310 Series

Power supply

current in

Sleep modes*

ICCSPLL

PLL Sleep mode with

CLKS1/2 = CLKP1 = 16MHz,

CLKP2 = 8MHz

(CLKRC and CLKSC stopped)

+25°C 4 6

+125°C 4.7 9

PLL Sleep mode with

CLKS1/2 = CLKP1 = 32MHz,

CLKP2 = 16MHz

(CLKRC and CLKSC stopped)

+25°C 7 9.5

+125°C 8 12.5

PLL Sleep mode with

CLKS1/2 = 48MHz,

CLKP1/2 = 24MHz

(CLKRC and CLKSC stopped)

+25°C 7 9

+125°C 8 12

PLL Sleep mode with

CLKS1/2 = CLKP1= 56MHz,

CLKP2 = 28MHz

(CLKRC and CLKSC stopped.

Core voltage at 1.9V)

+25°C 11 14.5

+125°C 12 17.5

PLL Sleep mode with

CLKS1/2 = 96MHz,

CLKP1= 48MHz,

CLKP2 = 24MHz

(CLKRC and CLKSC stopped.

Core voltage at 1.9V)

+25°C 12 15

+125°C 13 18

ICCSMAIN

Main Sleep mode with

CLKS1/2 = CLKP1/2 = 4MHz

(CLKPLL, CLKSC and CLKRC

stopped)

+25°C 1 1.3

+125°C 1.6 4.1

ICCSRCH

RC Sleep mode with

CLKS1/2 = CLKP1/2 = 2MHz

(CLKMC, CLKPLL and

CLKSC stopped)

+25°C 0.55 1.1

+125°C 1.15 3.9

Power supply

current in

Sleep modes*

ICCSRCL

RC Sleep mode with

CLKS1/2 = CLKP1/2 =

100kHz,

SMCR:LPMSS = 0

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in high power mode)

+25°C 0.08 0.2

+125°C 0.59 2.95

RC Sleep mode with CLKS1/2

= CLKP1/2 = 100kHz,

SMCR:LPMSS = 1

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in low power mode)

+25°C 0.05 0.15

+125°C 0.56 2.9

ICCSSUB

Sub Sleep mode with

CLKS1/2 = CLKP1/2 = 32kHz

(CLKMC, CLKPLL and

CLKRC stopped)

+25°C 0.04 0.12

+125°C 0.54 2.9

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Condition (at TA)Value Unit Remarks

Typ Max

Document Number: 002-04592 Rev. *B Page 53 of 82

CY96310 Series

Power supply

current in

Timer modes*

ICCTPLL

PLL Timer mode with

CLKMC = 4MHz,

CLKPLL = 48MHz

(CLKRC and CLKSC stopped)

+25°C 1.3 1.8

+125°C 1.9 4.8

ICCTMAIN

Main Timer mode with CLKMC

= 4MHz,

SMCR:LPMSS = 0

(CLKPLL, CLKRC and CLKSC

stopped. Voltage regulator in

high power mode)

+25°C 0.11 0.2

+125°C 0.63 3

Main Timer mode with

CLKMC = 4MHz,

SMCR:LPMSS = 1

(CLKPLL, CLKRC and CLKSC

stopped. Voltage regulator in

low power mode)

+25°C 0.08 0.15

+125°C 0.6 2.9

Power supply

current in

Timer modes*

ICCTRCH

RC Timer mode with

CLKRC = 2MHz,

SMCR:LPMSS = 0

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in high power mode)

+25°C 0.1 0.2

+125°C 0.63 3

RC Timer mode with

CLKRC = 2MHz,

SMCR:LPMSS = 1

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in low power mode)

+25°C 0.07 0.15

+125°C 0.6 2.9

ICCTRCL

RC Timer mode with

CLKRC = 100kHz,

SMCR:LPMSS = 0

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in high power mode)

+25°C 0.06 0.15

+125°C 0.56 2.95

RC Timer mode with

CLKRC = 100kHz,

SMCR:LPMSS = 1

(CLKMC, CLKPLL and

CLKSC stopped. Voltage

regulator in low power mode)

+25°C 0.03 0.1

+125°C 0.53 2.85

ICCTSUB

Sub Timer mode with

CLKSC = 32kHz

(CLKMC, CLKPLL and

CLKRC stopped)

+25°C 0.035 0.1

+125°C 0.53 2.85

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Condition (at TA)Value Unit Remarks

Typ Max

Document Number: 002-04592 Rev. *B Page 54 of 82

CY96310 Series

Power supply

current in Stop Mode ICCH

VRCR:LPMB[2:0] = 110B

(Core voltage at 1.8V)

+25°C 0.02 0.08

+125°C 0.52 2.8

VRCR:LPMB[2:0] = 000B

(Core voltage at 1.2V)

+25°C 0.015 0.06

+125°C 0.4 2.3

Power supply

current for active

Low Voltage detec-

tor

ICCLVD Low voltage detector enabled

(RCR:LVDE = 1)

+25°C 5 10

μAMust be added to all

current above

+125°C 7 20

Power supply

current for active

Clock modulator

ICCCLOMO Clock modulator enabled (CM-

CR:PDX = 1) -34.5mA

Must be added to all

current above

Flash Write/Erase

current ICCFLASH Current for one Flash module - 15 40 mA Must be added to all

current above

Input capacitance CIN --515pF

Other than C, AVCC,

AVSS, AVRH, AVRL, VCC,

VSS

* : The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock

connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for

further details about voltage regulator control.

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Condition (at TA)Value Unit Remarks

Typ Max

Document Number: 002-04592 Rev. *B Page 55 of 82

CY96310 Series

14.4 AC Characteristics

Source Clock timing (TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Clock frequency fCX0, X1

3 - 16 MHz When using a crystal oscillator, PLL off

0-16MHz

When using an opposite phase external clock,

PLL off

3.5 - 16 MHz When using a crystal oscillator or opposite

phase external clock, PLL on

Clock frequency fFCI X0

0-56MHz

When using a single phase external clock in

“Fast Clock Input mode” , PLL off

3.5 - 56 MHz When using a single phase external clock in

“Fast Clock Input mode” , PLL on

Clock frequency fCL

X0A, X1A 32 32.768 100 kHz When using an oscillation circuit

0 - 100 kHz When using an opposite phase external clock

X0A 0 - 50 kHz When using a single phase external clock

Clock frequency fCR -50 100 200 kHz When using slow frequency of RC oscillator

1 2 4 MHz When using fast frequency of RC oscillator

RC clock

stabilization time tRCSTAB - 256 RC clock cycles Applied after any reset and when activating

the RC oscillator.

PLL Clock

frequency fCLKVCO - 64 - 200 MHz Permitted VCO output frequency of PLL

(CLKVCO)

PLL Phase Jitter TPSKEW ---± 5ns

For CLKMC (PLL input clock) 4MHz, jitter

coming from external oscillator, crystal or

resonator is not covered

Input clock pulse

width PWH, PWL X0,X1 8 - - ns Duty ratio is about 30% to 70%

Input clock pulse

width PWHL, PWLL X0A,X1A 5 - - μs

Document Number: 002-04592 Rev. *B Page 56 of 82

CY96310 Series

tCYL

PWH PWL

VIL

VIH

X0A

tCYLL

PWH PWL

VIL

VIH

Document Number: 002-04592 Rev. *B Page 57 of 82

CY96310 Series

Internal Clock timing

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol

Core Voltag e Settings

Unit Remarks1.8V 1.9V

Min Max Min Max

Internal System clock

frequency (CLKS1 and

CLKS2)

fCLKS1, fCLKS2 092096MHz

Internal CPU clock frequency

(CLKB), internal peripheral

clock frequency (CLKP1)

fCLKB, fCLKP1 052056MHz

Internal peripheral clock

frequency (CLKP2) fCLKP2 028032MHz

Document Number: 002-04592 Rev. *B Page 58 of 82

CY96310 Series

External Reset timing

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Reset input time tRSTL RSTX 500 - - ns

0.2 VCC

RSTX

tRSTL

0.2 VCC

Document Number: 002-04592 Rev. *B Page 59 of 82

CY96310 Series

Power On Reset timing

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Power on rise time tRVcc 0.05 - 30 ms

Power off time tOFF Vcc 1 - - ms

0.2 V

2.7V

tOFF

0.2 V 0.2 V

If the power supply is changed too rapidly, a power-on reset may occur.

We recommend a smooth startup by restraining voltages when changing the

power supply voltage during operation, as shown in the figure below.

3 V

VCC

Rising edge of 50 mV/ms

maximum is allowed

Document Number: 002-04592 Rev. *B Page 60 of 82

CY96310 Series

External Input timin g

Note : Relocated Resource Inputs have same characteristics

(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Condition Value Unit Used Pin input function

Min Max

Input pulse

width

tINH

tINL

INTn(_R)

—

200 — ns External Interrupt

NMI NMI

Pnn_m

2*tCLKP1 + 200

(tCLKP1=1/fCLKP1)—ns

General Purpose IO

TINn Reload Timer

TTGn(_R) PPG Trigger input

ADTG_R AD Converter Trigger

INn Input Capture

VIL

VIH

tINH

VIL

VIH

tINL

External Pin input

Document Number: 002-04592 Rev. *B Page 61 of 82

CY96310 Series

USART timing

WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing

described in the different tables must then be increased by 10ns.

Notes: • AC characteristic in CLK synchronized mode.

•C

L is the load capacity value of pins when testing.

• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.

These parameters are shown in “CY96300 Super series Hardware Manual”.

•t

CLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns

*1: Parameter N depends on tSCYCI and can be calculated as follows:

•if t

SCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2

•if t

SCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1

Examples:

(TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)

Parameter Symbol Pin Condition VCC = AVCC= 4.5V

to 5.5V VCC = A VCC= 3.0V to

4.5V Unit

Min Max Min Max

Serial clock cycle time tSCYCI SCKn

Internal Shift

Clock Mode

4 tCLKP1 —4 t

CLKP1 —ns

SCK ↓ → SOT delay time tSLOVI

SCKn,

SOTn -20 +20 -30 +30 ns

SOT → SCK ↑ delay time tOVSHI

SCKn,

SOTn

N*tCLKP1

- 20 *1 —N*tCLKP1 -

30 *1 —ns

Valid SIN → SCK ↑tIVSHI

SCKn,

SINn

tCLKP1 +

45 —tCLKP1 +

55 —ns

SCK ↑ → Valid SIN hold

time tSHIXI

SCKn,

SINn 0— 0 —ns

Serial clock “L” pulse width tSLSHE SCKn

External Shift

Clock Mode

tCLKP1 +

10 —tCLKP1 +

10 —ns

Serial clock “H” pulse width tSHSLE SCKn tCLKP1 +

10 —tCLKP1 +

10 —ns

SCK ↓ → SOT delay time tSLOVE

SCKn,

SOTn —2 tCLKP1

+ 45 —2 tCLKP1

+ 55 ns

Valid SIN → SCK ↑tIVSHE

SCKn,

SINn

tCLKP1/2

+ 10 —tCLKP1/2 +

10 —ns

SCK ↑ → Valid SIN hold

time tSHIXE

SCKn,

SINn

tCLKP1 +

10 —tCLKP1 +

10 —ns

SCK fall time tFE SCKn — 20 — 20 ns

SCK rise time tRE SCKn — 20 — 20 ns

tSCYCI N

4*tCLKP1 2

5*tCLKP1, 6*tCLKP1 3

7*tCLKP1, 8*tCLKP1 4

... ...

Document Number: 002-04592 Rev. *B Page 62 of 82

CY96310 Series

Internal Shift Clock Mode

SOT

tSLOVI

SIN

VIL

VIH

tIVSHI

VIL

VIH

tSHIXI

tOVSHI

SCK for

ESCR:SCES = 0

0.8*VCC

tSCYCI

SCK for

ESCR:SCES = 1

0.8*VCC 0.8*VCC

0.2*VCC

0.8*VCC

0.2*VCC

External Shift Clock Mode

tFE

VIL

SOT

tSLOVE

SIN

VIL

VIH

tIVSHE

VIL

VIH

tSHIXE

VIH

tRE

VIH

tSLSHE

VIL

VIH

tSHSLE

VIH

SCK for

ESCR:SCES = 0

SCK for

ESCR:SCES = 1

0.8*VCC

0.2*VCC

Document Number: 002-04592 Rev. *B Page 63 of 82

CY96310 Series

14.5 Analog Digital Converter

Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.

(TA = -40 °C to +125 °C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Value Unit Remarks

Min Typ Max

Resolution - - - - 10 bit

Tot a l e r r o r - - - - ± 3LSB

Nonlinearity error - - - - ± 2.5 LSB

Differential nonlinearity error - - --± 1.9 LSB

Zero transition voltage VOT ANn AVRL - 1.5

LSB

AVRL+

0.5 LSB

AVRL +

2.5 LSB V

Full scale transition voltage VFST ANn AVRH -

3.5 LSB

AVRH -

1.5 LSB

AVRH +

0.5 LSB V

Compare time - -

1.0 - 16,500 μs4.5V ≤ AVCC ≤ 5.5V

2.0 - - μs3.0V ≤ AVCC < 4.5V

Sampling time - -

0.5 - - μs4.5V ≤ AVCC ≤ 5.5V

1.2 - - μs3.0V ≤ AVCC < 4.5V

Analog input leakage current

(during conversion) IAIN ANn

-1 - +1 μA

TA ≤ 105 °C,

AVSS, AVRL < VI < AVCC,

AVRH

-1.2 - +1.2 μA

105 °C < TA ≤ 125 °C,

AVSS, AVRL < VI < AVCC,

AVRH

Analog input voltage range VAIN ANn AVRL - AVRH V

Reference voltage range

AVRH AVRH 0.75 AVcc - AVcc V

AVRL AVRL AVSS -0.25 AVCC V

Power supply current

IAAVcc - 2.5 5 mA A/D Converter active

IAH AVcc - - 5 μAA/D Converter not

operated

Reference voltage current

IRAVRH/AVR

L- 0.7 1 mA A/D Converter active

IRH AVRH/AVR

L--5μAA/D Converter not

operated

Offset between input

channels -ANn--4LSB

Document Number: 002-04592 Rev. *B Page 64 of 82

CY96310 Series

Definition of A/D Converter Terms

Resolution: Analog variation that is recognized by an A/D converter.

Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition

error and nonlinearity error.

Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”) and full-scale transition

line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.

Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Zero reading voltage: Input voltage which results in the minimum conversion value.

Full scale reading voltage: Input voltage which results in the maximum conversion value.

3FF

3FE

3FD

004

003

002

001

AVRL AVRH

1.5 LSB

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

Actual conversion

characteristics

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

Digital output

Analog input

Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB [LSB]

1 LSB = (Ideal value) AVRH − AVRL

1024 [V]

VOT (Ideal value) = AVRL + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

VNT : A voltage at which digital output transitions from (N − 1) to N.

Total error

N: A/D converter digital output value

Document Number: 002-04592 Rev. *B Page 65 of 82

CY96310 Series

3FF

3FE

3FD

004

003

002

001

AVRL AVRH AVRL AVRH

N + 1

N − 1

N − 2

VOT (actual measurement value)

{1 LSB × (N − 1)

+ VOT }

Actual conversion

characteristics

VFST (actual

measurement

value)

VNT (actual

measurement value)

Actual conversion

characteristics

Ideal characteristics

Actual conversion

characteristics

Actual conversion

characteristics

Ideal

characteristics

Digital output

Analog inputAnalog input

VNT

(actual measurement value)

V (N + 1) T

(actual measurement

value)

Nonlinearity error Differential nonlinearity error

Differential nonlinearity error of digital output N =

1 LSB =

Nonlinearity error of digital output N = VNT − {1 LSB × (N − 1) + VOT}

1 LSB [LSB]

V (N+1) T − VNT

1 LSB

−1 LSB [LSB]

VFST − VOT

1022

[V]

N : A/D converter digital output value

VOT : Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

Document Number: 002-04592 Rev. *B Page 66 of 82

CY96310 Series

Accuracy and setting of the A/D Converter sampling time

If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold

capacitor is insufficient, adversely affecting the A/D conversion precision.

To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time depends on the

external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVcc voltage level. The following

replacement model can be used for the calculation:

The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement model above can be used:

Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC)

• Do not select a sampling time below the absolute minimum permitted value

(0.5μs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 μs for 3.0V ≤ AVcc < 4.5V).

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. In this case the internal

sampling capacitance CADC will be charged out of this external capacitance.

• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL

(static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and

comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor.

• The accuracy gets worse as |AVRH - AVRL| becomes smaller.

Comparator

Sampling switch

RADC

CADC

Analog

Rext

Cext

input

MCU

Source

Rext: external driving impedance

Cext: capacitance of PCB at A/D converter input

RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V

12kΩ (max) for 3.0V ≤ AVcc < 4.5V

CADC: sampling capacitance within MCU: 10pF (max)

CIN

CIN: capacitance of MCU input pin: 15pF (max)

Document Number: 002-04592 Rev. *B Page 67 of 82

CY96310 Series

14.6 Low Vo lta g e De te ct o r cha r ac te ris tic s

CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.

For correct detection, the slope of the voltage level must satisfy .

Faster variations are regarded as noise and may not be detected.

The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of “Level 0” (VDL0_MIN).

The electrical characteristics however are only valid in the specified range (usually down to 3.0V).

(TA = -40 °C to +125 °C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)

Parameter Symbol Value Unit Remarks

Min Max

Stabilization time TLVDSTAB -110μsAfter power-up or change of detection

level

Level 0 VDL0 2.5 2.9 V CILCR:LVL[3:0]=”0000”

Level 1 VDL1 2.8 3.2 V CILCR:LVL[3:0]=”0001”

Level 2 VDL2 3 3.4 V CILCR:LVL[3:0]=”0010”

Level 3 VDL3 3.35 3.8 V CILCR:LVL[3:0]=”0011”

Level 4 VDL4 3.5 3.95 V CILCR:LVL[3:0]=”0100”

Level 5 VDL5 3.6 4.1 V CILCR:LVL[3:0]=”0101”

Level 6 VDL6 3.7 4.2 V CILCR:LVL[3:0]=”0110”

Level 7 VDL7 3.8 4.3 V CILCR:LVL[3:0]=”0111”

Level 8 VDL8 3.9 4.4 V CILCR:LVL[3:0]=”1000”

Level 9 VDL9 3.95 4.5 V CILCR:LVL[3:0]=”1001”

Level 10 VDL10 not used

Level 11 VDL11 not used

Level 12 VDL12 2.6 3 V CILCR:LVL[3:0]=”1100”

Level 13 VDL13 not used

Level 14 VDL14 not used

Level 15 VDL15 not used

dV ≤ 0.004 V

dt μs

Document Number: 002-04592 Rev. *B Page 68 of 82

CY96310 Series

Low Voltage Detector Operation

In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup

behavior, please refer to the corresponding hardware manual chapter.

Voltage [V]

Time [s]

VCC

VDLx, Min

VDLx, Max

Low Voltage Reset Assertion

Normal Operation Power Reset Extension Time

Document Number: 002-04592 Rev. *B Page 69 of 82

CY96310 Series

14.7 FLASH memory program/erase characteristics

*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high

temperature measurements into normalized value at 85oC)

(TA = -40°C to 105°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Parameter Value Unit Remarks

Min Typ Max

Sector erase time - 0.9 3.6 s Without erasure pre-programming

time

Chip erase time - n*0.9 n*3.6 s

Without erasure pre-programming

time (n is the number of Flash sector

of the device)

Word (16-bit width) programming time - 23 370 us Without overhead time for submitting

write command

Program/Erase cycle 10000 - - cycle

Flash data retention time 20 - - year *1

Document Number: 002-04592 Rev. *B Page 70 of 82

CY96310 Series

15. Example Characteristics

15.1 Temperature dependency of power supply currents

The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes.

Common condition for all operation modes:

•V

CC = AVCC = 5.0V

• Main clock = 4MHz external clock

• Sub clock = 32kHz external clock

Operation mode details:

Mode name Details

PLL Run 56 PLL Run mode current ICCPLL with the following settings:

•f

CLKS1 = fCLKS2 = fCLKB = fCLKP1 = 56MHz

•f

CLKP2 = 28MHz

• Regulator in High Power Mode

• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)

• 2 Flash/ROM wait states (MTCRA=233AH)

• RC oscillator and Sub oscillator stopped

PLL Run 48 PLL Run mode current ICCPLL with the following settings:

•f

CLKS1 = fCLKS2 = 96MHz

•f

CLKB = fCLKP1 = 48MHz

•f

CLKP2 = 24MHz

• Regulator in High Power Mode

• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)

• 1 Flash/ROM wait states (MTCRA=6B09H)

• RC oscillator and Sub oscillator stopped

PLL Run 24 PLL Run mode current ICCPLL with the following settings:

•f

CLKS1 = fCLKS2 = 48MHz

•f

CLKB = fCLKP1 = fCLKP2 = 24MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• 0 Flash/ROM wait states (MTCRA=2208H)

• RC oscillator and Sub oscillator stopped

Main Run Main Run mode current ICCMAIN with the following settings:

•f

CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• 1 Flash/ROM wait states (MTCRA=0239H)

• PLL, RC oscillator and Sub oscillator stopped

RC Run 2M RC Run mode current ICCRCH with the following settings:

• RC oscillator set to 2MHz (CKFCR:RCFS = 1)

•f

CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• 1 Flash/ROM wait states (MTCRA=0239H)

• PLL, Main oscillator and Sub oscillator stopped

Document Number: 002-04592 Rev. *B Page 71 of 82

CY96310 Series

RC Run 100k RC Run mode current ICCRCL with the following settings:

• RC oscillator set to 100kHz (CKFCR:RCFS = 0)

•f

CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz

• Regulator in Low Power Mode A (SMCR:LPMS = 1)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• 1 Flash/ROM wait states (MTCRA=0239H)

• PLL, Main oscillator and Sub oscillator stopped

Sub Run Sub Run mode current ICCSUB with the following settings:

•f

CLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz

• Regulator in Low Power Mode A (by hardware)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• 1 Flash/ROM wait states (MTCRA=0239H)

• PLL, RC oscillator and Main oscillator stopped

PLL Sleep 56 PLL Sleep mode current ICCSPLL with the following settings:

•f

CLKS1 = fCLKS2 = fCLKP1 = 56MHz

•f

CLKP2 = 28MHz

• Regulator in High Power Mode

• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)

• RC oscillator and Sub oscillator stopped

PLL Sleep 48 PLL Sleep mode current ICCSPLL with the following settings:

•f

CLKS1 = fCLKS2 = 96MHz

•f

CLKP1 = 48MHz

•f

CLKP2 = 24MHz

• Regulator in High Power Mode

• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)

• RC oscillator and Sub oscillator stopped

PLL Sleep 24 PLL Sleep mode current ICCSPLL with the following settings:

•f

CLKS1 = fCLKS2 = 48MHz

•f

CLKP1 = fCLKP2 = 24MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• RC oscillator and Sub oscillator stopped

Main Sleep Main Sleep mode current ICCSMAIN with the following settings:

•f

CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• PLL, RC oscillator and Sub oscillator stopped

RC Sleep 2M RC Sleep mode current ICCSRCH with the following settings:

• RC oscillator set to 2MHz (CKFCR:RCFS = 1)

•f

CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• PLL, Main oscillator and Sub oscillator stopped

Mode name Details

Document Number: 002-04592 Rev. *B Page 72 of 82

CY96310 Series

RC Sleep 100k RC Sleep mode current ICCSRCL with the following settings:

• RC oscillator set to 100kHz (CKFCR:RCFS = 0)

•f

CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz

• Regulator in Low Power Mode A (SMCR:LPMSS = 1)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• PLL, Main oscillator and Sub oscillator stopped

Sub Sleep Sub Sleep mode current ICCSSUB with the following settings:

•f

CLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz

• Regulator in Low Power Mode A (by hardware)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• PLL, RC oscillator and Main oscillator stopped

PLL Timer 48 PLL Timer mode current ICCTPLL with the following settings:

•f

CLKS1 = fCLKS2 = 48MHz

• Regulator in High Power Mode

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)

• RC oscillator and Sub oscillator stopped

Main Timer Main Timer mode current ICCTMAIN with the following settings:

•f

CLKS1 = fCLKS2 = 4MHz

• Regulator in Low Power Mode A (SMCR:LPMSS = 1)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• PLL, RC oscillator and Sub oscillator stopped

RC Timer 2M RC Timer mode current ICCTRCH with the following settings:

• RC oscillator set to 2MHz (CKFCR:RCFS = 1)

•f

CLKS1 = fCLKS2 = 2MHz

• Regulator in Low Power Mode A (SMCR:LPMSS = 1)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• PLL, Main oscillator and Sub oscillator stopped

RC Timer 100k RC Timer mode current ICCTRCL with the following settings:

• RC oscillator set to 100kHz (CKFCR:RCFS = 0)

•f

CLKS1 = fCLKS2 = 100kHz

• Regulator in Low Power Mode A (SMCR:LPMSS = 1)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• PLL, Main oscillator and Sub oscillator stopped

Sub Timer Sub Timer mode current ICCTSUB with the following settings:

•f

CLKS1 = fCLKS2 = 32kHz

• Regulator in Low Power Mode A (by hardware)

• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)

• PLL, RC oscillator and Main oscillator stopped

Stop 1.8V Stop mode current ICCH with the following settings:

• Regulator in Low Power Mode B (by hardware)

• Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B)

Stop 1.2V Stop mode current ICCH with the following settings:

• Regulator in Low Power Mode B (by hardware)

• Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B)

Mode name Details

Document Number: 002-04592 Rev. *B Page 73 of 82

CY96310 Series

CY96F313/F315 PLL Run and Sleep mode currents

-60 -40 -20 0 +20 +40 +60 +80 +100 +120

PLL Run 48

Ta [ºC]

Icc [mA]

PLL Sleep 48

PLL Sleep 56

PLL Sleep 24

PLL Run 56

PLL Run 24

Document Number: 002-04592 Rev. *B Page 74 of 82

CY96310 Series

CY96F313/F315 operation modes with medium currents

CY96F313/F315 Low power mode currents

-60 -40 -20 +20 +40 +60 +80 +100 +120

Icc [mA]

Ta [ºC]

PLL Timer 48

RC Run 2 M

Main Run

Main Sleep

RC Sleep 2 M

0.001

0.01

0.1

Icc [mA]

Ta [ºC]

-60 -40 -20 0 +20 +40 +60 +80 +100 +120

RC Run 100 k

Sub Run

Main Timer

RC Timer 2 M

RC Sleep 100 k

Sub Sleep

Sub Timer

RC Timer 100 k

Stop 1.8 V

Stop 1.2 V

Document Number: 002-04592 Rev. *B Page 75 of 82

CY96310 Series

15.2 Frequency dependency of power supply currents in PLL Run mode

The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different

frequencies and Flash timing settings.

Measurement conditions:

•V

CC = AVCC = 5.0V

• Ta = 25°C

•f

CLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram

•f

CLKS2 = fCLKS1

•f

CLKP1 = fCLKB

•f

CLKP2 = fCLKB/2

• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram

• Main clock = 4MHz external clock

• Flash memory timing settings:

•MTCRA=2128

H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB)

•MTCRA=0239

H/2129H (1 Flash wait state, fCLKS1 = fCLKB)

•MTCRA=4C09

H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB)

•MTCRA=233A

H (2 Flash wait states, fCLKS1 = fCLKB)

• Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):

• 0 Flash wait states: 0.5

• 1 Flash wait states: 0.33

• 2 Flash wait states: 0.25

CY96F313/F315 PLL Run mode currents

0 4 8 121620242832364044485256

ICCPLL (mA)

CLKB/CLKP1 (MHz)

1 Flash wait state

(CLKS1=2*CLKB, 1.9 V)

1 Flash wait state

(CLKS1=2*CLKB, 1.8 V)

0 Flash wait states

(CLKS1=2*CLKB, 1.8 V)

1 Flash wait state

(CLKS1=CLKB, 1.8V)

2 Flash wait states

(CLKS1=CLKB, 1.8 V)

2 Flash wait states

(CLKS1=CLKB, 1.9 V)

: Specified in "DC characteristics"

Document Number: 002-04592 Rev. *B Page 76 of 82

CY96310 Series

16. Package Dimension CY96(F)31x LQFP48

127(6

$//',0(16,216$5(,10,//,0(7(56

'$7803/$1(+,6/2&$7('$77+(%277202)7+(02/'3$57,1*

/,1(&2,1&,'(17:,7+:+(5(7+(/($'(;,767+(%2'<

'$7806$%$1''72%('(7(50,1('$7'$7803/$1(+

72%('(7(50,1('$76($7,1*3/$1(&

',0(16,216'$1'('2127,1&/8'(02/'3527586,21

$//2:$%/(3527586,21,6PP35(6,'(

',0(16,216'$1'(,1&/8'(02/'0,60$7&+$1'$5('(7(50,1('

$7'$7803/$1(+

'(7$,/62)3,1,'(17,),(5$5(237,21$/%870867%(/2&$7('

:,7+,17+(=21(,1',&$7('

5(*$5'/(662)7+(5(/$7,9(6,=(2)7+(833(5$1'/2:(5%2'<

6(&7,216',0(16,216'$1'($5('(7(50,1('$77+(/$5*(67

)($785(2)7+(%2'<(;&/86,9(2)02/')/$6+$1'*$7(%8556

%87,1&/8',1*$1<0,60$7&+%(7:((17+(833(5$1'/2:(5

6(&7,2162)7+(02/'(5%2'<

',0(16,21E'2(6127,1&/8'('$0%(53527586,217+('$0%$5

3527586,21

ᤡ

ᤢ

6+$//127&$86(7+(/($':,'7+72(;&(('E

0$;,080%<025(7+$1PP'$0%$5&$1127%(/2&$7('21

7+(/2:(55$',86257+(/($')227

7+(6(',0(16,216$33/<727+()/$76(&7,212)7+(/($'

%(7:((1PP$1'PP)5207+(/($'7,3

$,6'(),1('$67+(',67$1&()5207+(6($7,1*3/$1(72

7+(/2:(6732,172)7+(3$&.$*(%2'<

DIMENSIONS

SYMBOL MIN. NOM. MAX.

A1.70

A1 0.00 0.20

b 0.15 0.27

c 0.09 0.20

D 9.00 BSC

D1 7.00 BSC

e0.50 BSC

L0.45 0.60 0.75

L1 0.30 0.50 0.70

9.00 BSC

7.00 BSC

0° 8°

6(('(7$,/$

112

EE1

0.20 CA-B D

;

0.10 CA-B D

;

0.80 CA-B D

SEATING

PLANE

'(7$,/$

A10.25

SECTION A-A'

0.80 C

6,'(9,(:

7239,(:

%277209,(:

36 25

25 36

7.0X7.0X1.7 MM LQA048 REV**

PACKAGE OUTLINE, 48 LEAD LQFP

002-13731 **

Document Number: 002-04592 Rev. *B Page 77 of 82

CY96310 Series

17. Ordering Information

MCU with CAN controller

MCU without CAN controller

Part number Flash/ROM Subclock Persistent

Low Voltage

Reset Package

CY96F313RSBPMC-GS-UJE2 Flash A (96KB) No No

48 pins Plastic LQFP

(LQA048)

CY96F315RSBPMC-GS-UJE1 Flash A (160KB) No No

NoCY96F315RSBPMC-GS-UJE2 No

Part number Flash/ROM Subclock Persistent

Low Voltage

Reset Package

CY96F313ASBPMC-GS-UJE2 Flash A (96KB) No No 48 pins Plastic LQFP

(LQA048)

Document Number: 002-04592 Rev. *B Page 78 of 82

CY96310 Series

18. Revision History

Revision Date Modification

Prelim 1 2008-12-09 Creation

Prelim 2 2009-01-09 • Interrupt vector table corrected (description of CAN2 interrupt)

• Low voltage detector spec updated (detection levels and stabilization time)

• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted

Document Number: 002-04592 Rev. *B Page 79 of 82

CY96310 Series

19. Major Changes

Spansion Publication Number: DS07-13808-2E

Page Section Change Results

3Features Corrected the sentence “Reload timer overflow” to “Reload timer

underflow” for Programmable Pulse Generator.

5, 6 Product Lineup Removed footnote.

Changed name of evaluation sample.

8Pin Assignments Corrected pin number of X0.

34 → 35

14 Memory Map Changed name of evaluation sample.

17 Serial Programming Communication Interface Corrected device name, package name and pin numbers.

49-50 Electrical Characteristics

3.DC Characteristics

Note added in DC characteristics how to select driving strength of

ports.

51-56

Electrical Characteristics

3.DC Characteristics

Updated Icc specs.

Updated Power Supply current spec in Run/Sleep/Timer/Stop

modes (new spec items in PLL Run/Sleep mode, small adjustment

of most other values).

Electrical Characteristics

4.AC Characteristics

Note added that PLL phase jitter spec does not include jitter coming

from Main clock.

Added specification of RC clock stabilization time.

Electrical Characteristics

5. Analog Digital Converter

Changed the item for “Zero reading voltage” and “Full scale reading

voltage”.

AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA

above 105deg.

Electrical Characteristics

5. Analog Digital Converter

“Notes on A/D Converter Section” was rewrite and renamed to

“Accuracy and setting of the A/D Converter sampling time”.

Impact of input pin capacitance and external capacitance added to

formula for calculation of the sampling time.

69 Electrical Characteristics

6. Low Voltage Detector Characteristics

Detection levels updated.

72-77 Example Characteristics Added.

Package Dimension MB96(F)31x LQFP48 Updated package figure.

Added the following sentence under the figure: “Please check the

latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/”.

Ordering Information Updated part number:

MB96F313/F315**A → MB96F313/F315**B

Removed footnote.

Added Part Numbers “MB96F313RSB PMC-GSE1”,

“MB96F315RSB PMC-GSE1”.

Rev.*B

- Marketing Part Numbers changed from an MB prefix to CY prefix

10,

1. Product Lineup

3. Pin Assignment

5. Pin Circuit Type

17. Ordering Information

Package description modified to JDEC description.

FPT-48P-M26 → LQA048

Document Number: 002-04592 Rev. *B Page 80 of 82

CY96310 Series

NOTE: Please see “Document History” about later revised information.

17. Ordering Information MCU with CAN controller

Deleted the following parts number:

- MB96F313YSBPMC-GSE2

- MB96F313RSBPMC-GSE1

- MB96F313YWBPMC-GSE2

- MB96F313RWBPMC-GSE2

- MB96F315YSBPMC-GSE2

- MB96F315YWBPMC-GSE2

- MB96F315RWBPMC-GSE2

- MB96V300CRB-ES

Changed the following parts number:

- MB96F313RSBPMC-GSE2 → CY96F313RSBPMC-GS-UJE2

- MB96F315RSBPMC-GSE1 → CY96F315RSBPMC-GS-UJE1

- MB96F315RSBPMC-GSE2 → CY96F315RSBPMC-GS-UJE2

MCU without CAN controller

Deleted the following parts number:

- MB96F313AWBPMC-GSE2

- MB96F315AWBPMC-GSE2

- MB96F315ASBPMC-GSE2

Changed the following parts number:

- MB96F313ASBPMC-GSE2 → CY96F313ASBPMC-GS-UJE2

Page Section Change Results

Document Number: 002-04592 Rev. *B Page 81 of 82

CY96310 Series

Document History

Document Title: CY96310 Series F2MC-16FX 16-bit Proprietary Microcontroller

Document Number: 002-04592

Revision ECN Orig. of

Change Submission

Date Description o f Change

** — AKIH 08/04/2010 Migrated to Cypress and assigned document number 002-04592.

No change to document contents or format.

*A 5230360 AKIH 04/22/2016 Updated to Cypress template

*B 6195944 WAFA 06/04/2018

Revised the following items:

Marketing Part Numbers changed from an MB prefix to a CY prefix.

1. Product Lineup

3. Pin Assignment

5. Pin Circuit Type

17. Ordering Information

For details, please see 19. Major Changes.

Document Number: 002-04592 Rev. *B Revised June 4, 2018 Page 82 of 82

CY96310 Series

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Arm® Cortex® Microcontrollers cypress.com/arm

Automotive cypress.com/automotive

Clocks & Buffers cypress.com/clocks

Interface cypress.com/interface

Internet of Things cypress.com/iot

Memory cypress.com/memory

Microcontrollers cypress.com/mcu

PSoC cypress.com/psoc

Power Management ICs cypress.com/pmic

Touch Sensing cypress.com/touch

USB Controllers cypress.com/usb

Wireless Connectivity cypress.com/wireless

PSoC®Solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Cypress Developer Community

Technical Support

cypress.com/support