A6A595 8-Bit Serial Input, DMOS Power Driver Discontinued Product These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available. Date of status change: April 30, 2007 Recommended Substitutions: NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. PRELIMINARY INFORMATION 8-BIT SERIAL-INPUT, DMOS POWER DRIVER (Subject to change without notice) June 11, 2001 A6A595KA (DIP) OUT2 1 OUT3 2 20 OUT1 19 OUT0 18 SERIAL DATA IN 17 LOGIC SUPPLY LATCHES REGISTER CLEAR 3 CLR OUTPUT ENABLE 4 OE POWER GROUND 5 16 POWER GROUND POWER GROUND 6 15 POWER GROUND 14 LOGIC GROUND 13 SERIAL DATA OUT 12 OUT7 11 OUT6 STROBE 7 ST CLOCK 8 CLK REGISTER VDD REGISTER OUT4 9 OUT5 10 LATCHES Dwg. PP-029-15 ABSOLUTE MAXIMUM RATINGS at TA = 25C Output Voltage, VO ............................... 50 V Output Drain Current, Continuous, IO .......................... 350 mA* Peak, IOM ................................. 1100 mA Single-Pulse Avalanche Energy, EAS .. 75 mJ Avalanche Current, IAS ..................... 600 mA Source-Drain Diode Current, IFM ............ 2 A Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ..... -0.3 V to +7.0 V Package Power Dissipation, PD ... See Graph Junction Temperature, TJ .................. +150C Operating Temperature Range, TA ................................. -40C to +125C Storage Temperature Range, TS ................................. -55C to +150C * Each output, all outputs on. Pulse duration 100 s, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Data Sheet 26185.121 6A595 The A6A595KA and A6A595KLB combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. The A6A595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6A595KA is furnished in a 20-pin dual in-line plastic package. The A6A595KLB is furnished in a 24-lead wide-body, smalloutline plastic batwing package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85C. FEATURES 50 V Minimum Output Clamp Voltage 350 mA Output Current (all outputs simultaneously) 1 Typical rDS(on) Internal Short-Circuit Protection Low Power Consumption Replacements for TPIC6A595N and TPIC6A595DW Always order by complete part number: Part Number Package RJA A6A595KA 20-pin DIP 55C/W A6A595KLB 24-lead SOIC 55C/W RJC 25C/W -- RJT -- 6C/W 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS A6A595KLB (SOIC) 5 SUFFIX 'LB', R JT = 6.0C/W 1 OUT3 2 24 OUT1 23 OUT0 22 SERIAL DATA IN 21 LOGIC SUPPLY LATCHES 4 3 SUFFIX 'A', R JC = 25C/W 2 1 OUT2 R JA = 55C/W REGISTER CLEAR 3 CLR OUTPUT ENABLE 4 OE POWER GROUND 5 20 POWER GROUND POWER GROUND 6 19 POWER GROUND POWER GROUND 7 18 POWER GROUND POWER GROUND 8 17 POWER GROUND STROBE 9 ST 16 LOGIC GROUND CLOCK 10 CLK 15 SERIAL DATA OUT 14 OUT7 13 OUT6 REGISTER VDD REGISTER OUT4 11 OUT5 12 LATCHES 0 25 50 75 100 TEMPERATURE IN C 125 150 Dwg. GP-049-5 Dwg. PP-029-16A FUNCTIONAL BLOCK DIAGRAM REGISTER CLEAR (ACTIVE LOW) V DD CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER STROBE D-TYPE LATCHES LOGIC SUPPLY SERIAL DATA OUT OUTPUT ENABLE (ACTIVE LOW) LOGIC GROUND SUB CURRENT LIMIT AND CHARGE PUMP POWER GROUND POWER GROUND OUT 0 OUT N Power grounds must be connected together externally. 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2000, Allegro MicroSystems, Inc. Dwg. FP-013-6 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER V OUT DD IN Dwg. EP-063-5 DMOS POWER DRIVER OUTPUT Dwg. EP-010-10 VDD LOGIC INPUTS OUT RECOMMENDED OPERATING CONDITIONS over operating temperature range Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ 0.85VDD Low-level input voltage, VIL ................................. 0.15VDD Dwg. EP-063-4 SERIAL DATA OUT TRUTH TABLE Shift Register Contents Data Clock Input Input I0 I1 I2 ... I6 H H R0 R1 ... R5 R6 R6 L L R0 R1 ... R5 R6 R6 R0 R1 R2 ... R6 R7 R7 X X ... X X X P0 P1 P2 ... P6 P7 P7 X X L = Low Logic Level I7 Serial Data Output Strobe H = High Logic Level www.allegromicro.com -- X = Irrelevant Latch Contents I0 I1 ... I6 R0 R1 R2 ... R6 R7 P0 P1 P2 ... P6 P7 L P0 P1 P2 ... P6 P7 X ... X H H ... H X I2 Output Contents X P = Present State I7 Output Enable X I0 I1 H I2 H ... I6 I7 H R = Previous State 3 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified). Limits Characteristic Symbol Test Conditions Output Breakdown Voltage V(BR)DSX IDSX Off-State Output Current Static Drain-Source On-State Resistance Source-Drain Diode Voltage rDS(on) VSD Min. Typ. Max. Units IO = 1 mA 50 -- -- V VO = 40 V -- 0.1 1.0 A VO = 40 V, TA = 125C -- 0.2 5.0 A IO = 350 mA -- 1.0 1.5 IO = 350 mA, TA = 125C -- 1.7 2.5 IF = 350 mA -- 0.9 1.1 V Nominal Output Current IO(nom) VDS(on) = 0.5 V, TA = 85C -- 350 -- mA Output Current IO(chop) IO at which chopping starts, TC = 25C 0.6 0.8 1.1 A IIH VI = VDD -- -- 1.0 A IIL VI = 0 -- -- -1.0 A IOH = -20 A 4.9 4.99 -- V IOH = -4 mA 4.5 4.7 -- V IOL = 20 A -- 0 0.1 V IOL = 4 mA -- 0.3 0.5 V tPLH IO = 350 mA, CL = 30 pF -- 100 -- ns tPHL IO = 350 mA, CL = 30 pF -- 60 -- ns Output Rise Time tr IO = 350 mA, CL = 30 pF -- 55 -- ns Output Fall Time tf IO = 350 mA, CL = 30 pF -- 40 -- ns IDD(off) Outputs OFF -- 0.5 5.0 mA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs OFF -- 1.3 -- mA Logic Input Current SERIAL-DATA Output Voltage VOH VOL Prop. Delay Time Supply Current Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 s, duty cycle 2%. 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) LOGIC SYMBOL C 50% CLOCK A SERIAL DATA IN B DATA OUTPUT ENABLE STROBE 50% REGISTER CLEAR CLOCK tp SERIAL DATA OUT DATA 50% D SERIAL DATA IN G3 C2 R SRG8 C1 1D 2 E OUT0 OUT1 STROBE 50% OUTPUT ENABLE LOW = ALL OUTPUTS ENABLED OUT2 OUT3 OUT4 tp OUT5 HIGH = OUTPUT OFF OUT6 DATA 50% OUT N LOW = OUTPUT ON Dwg. WP-029-2 2 OUT7 SERIAL DATA OUT HIGH = ALL OUTPUTS DISABLED OUTPUT ENABLE Dwg. FP-043-2 50% t PLH t PHL tf tr 90% OUT N DATA 10% Dwg. WP-030-2 A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 20 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CLK) ............................................. 40 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) .............................................. 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 s NOTE - Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. www.allegromicro.com Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. 5 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER TEST CIRCUIT +15 V 1 INPUT 210 mH tav IAS = 600 mA IO Single-pulse avalanche energy test circuit and waveforms EAS = IAS x V(BR)DSX x tAV/2 DUT OUT VO V(BR)DSX VO(ON) Dwg. EP-066-2 CHOPPING-MODE OPERATION NORMAL LAMP IN-RUSH CURRENT LAMP CURRENT NOT TO SCALE As shown (the dashed line), when an incandescent lamp is initially turned on, the cold filament is at minimum resistance and will normally allow a 10x peak inrush current. As the lamp warms up, the filament resistance increases to its rated value and the lamp current is reduced to its steady-state rating. When switching a lamp with the A6A595, the internal chopping circuitry limits the current (the solid line) to IO(chop). The device will stay in the chopping mode until the lamp resistance increases and the current requirement is less than IO(chop). A sideeffect of this current-limiting feature is that lamp turn-on time will increase. CURRENT LIMIT (CHOPPING MODE) ON ~ 40 s OFF ~ 2.5 ms IO(chop) TIME 6 High incandescent lamp turn-on currents (commonly called in-rush currents) can contribute to poor lamp reliability and destroy semiconductor lamp drivers. Warming resistors protect both driver and lamp but use significant power when the lamp is off while currentlimiting resistors waste power when the lamp is on. Lamps with steady-state current ratings to 350 mA can be driven by the A6A595 without the need for warming or current limiting resistors. Dwg. WP-008-1 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER 1.50 OUTPUT CURRENT LIMIT IN AMPERES 1.25 VCC = 5.5 V 1.00 Typical output current limit as a function of case temperature VCC = 4.5 V 0.75 0.50 0.25 0 -50 0 50 150 100 CASE TEMPERATURE IN C Dwg. GP-073 TERMINAL DESCRIPTIONS A6A595KA (DIP) Terminal No. A6A595KLB (SOIC) Terminal No. Terminal Name 1-2 1-2 OUT2-3 3 3 REGISTER CLEAR When (active) low, the registers are cleared (set low). 4 4 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 5-6 5-8 7 9 STROBE 8 10 CLOCK Clock input terminal for data shift on rising edge. 9-12 11-14 OUT4-7 Current-sinking, open-drain DMOS output terminals. 13 15 SERIAL DATA OUT CMOS serial-data output to the following shift register. 14 16 LOGIC GROUND Reference terminal for input voltage measurements. 15-16 17-20 POWER GROUND Reference terminal for output voltage measurements. 17 21 LOGIC SUPPLY 18 22 SERIAL DATA IN Serial-data input to the shift-register. 19-20 23-24 Function Current-sinking, open-drain DMOS output terminals. POWER GROUND Reference terminal for output voltage measurements. OUT0-1 Data strobe input terminal; shift register data is latched on rising edge. (VDD) The logic supply voltage (typically 5 V). Current-sinking, open-drain DMOS output terminals. NOTE --Power grounds must be connected together externally. www.allegromicro.com 7 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER A6A595KA Dimensions in Inches (controlling dimensions) 20 0.014 0.008 11 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 10 BSC 0.005 MIN 0.210 MAX 0.015 0.150 0.115 MIN 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 20 0.355 0.204 11 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 3.81 2.93 0.39 MIN 0.558 0.356 Dwg. MA-001-20 mm NOTES:1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below. 8 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER A6A595KLB Dimensions in Inches (for reference only) 24 13 0.0125 0.0091 0.491 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 3 0.050 0.6141 0.5985 BSC 0 TO 8 NOTE 1 NOTE 3 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-25 in Dimensions in Millimeters (controlling dimensions) 24 13 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 3 15.60 15.20 1.27 BSC 0 TO 8 NOTE 1 NOTE 3 2.65 2.35 0.10 MIN. Dwg. MA-008-25A mm NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor's option within limits shown. www.allegromicro.com 9 6A595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 10 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000