NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
8-Bit Serial Input, DMOS Power Driver
A6A595
Date of status change: April 30, 2007
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Discontinued Product
Data Sheet
26185.121
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
The A6A595KA and A6A595KLB combine an 8-bit CMOS shift
register and accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power
loads.
The serial-data input, CMOS shift register and latches allow direct
interfacing with microprocessor-based systems. Serial-data input rates
are over 5 MHz. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in appli-
cations requiring additional drive lines.
The A6A595 DMOS open-drain outputs are capable of sinking up
to 500 mA. All of the output drivers are disabled (the DMOS sink
drivers turned off) by the OUTPUT ENABLE input high.
The A6A595KA is furnished in a 20-pin dual in-line plastic
package. The A6A595KLB is furnished in a 24-lead wide-body, small-
outline plastic batwing package (SOIC) with gull-wing leads. Copper
lead frames, reduced supply current requirements, and low on-state
resistance allow both devices to sink 150 mA from all outputs continu-
ously, to ambient temperatures over 85°C.
FEATURES
■50 V Minimum Output Clamp Voltage
■350 mA Output Current (all outputs simultaneously)
■1 Ω Typical rDS(on)
■Internal Short-Circuit Protection
■Low Power Consumption
■Replacements for TPIC6A595N and TPIC6A595DW
6A595
PRELIMINARY INFORMATION
(Subject to change without notice)
June 11, 2001
Always order by complete part number:
Part Number Package RθJA RθJC RθJT
A6A595KA 20-pin DIP 55°C/W 25°C/W —
A6A595KLB 24-lead SOIC 55°C/W — 6°C/W
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO............................... 50 V
Output Drain Current,
Continuous, IO.......................... 350 mA*
Peak, IOM ................................. 1100 mA†
Single-Pulse Avalanche Energy, EAS .. 75 mJ
Avalanche Current, IAS ..................... 600 mA
Source-Drain Diode Current, IFM ............ 2 A
Logic Supply Voltage, VDD .................. 7.0 V
Input Voltage Range, VI..... -0.3 V to +7.0 V
Package Power Dissipation, PD... See Graph
Junction Temperature, TJ.................. +150°C
Operating Temperature Range,
TA................................. -40°C to +125°C
Storage Temperature Range,
TS................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
LATCHES
REGISTER SERIAL
DATA IN
REGISTER
CLEAR
OUT
3
V
DD
STROBE
CLOCK CLK
ST
Dwg. PP-029-15
OUT
2
OUTPUT
ENABLE OE
LOGIC
GROUND
CLR
13
14
15
16
17
19
12
18
20
11
1
2
3
8
9
4
5
6
7
10
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
OUT
5
OUT
4
OUT
6
OUT
7
OUT
1
OUT
0
SERIAL
DATA OUT
LOGIC
SUPPLY
REGISTER
LATCHES
A6A595KA (DIP)
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Copyright © 2000, Allegro MicroSystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
POWER
GROUND
Dwg. FP-013-6
OUT
0
OUT
N
POWER
GROUND
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
V
DD
LOGIC
SUPPLY
REGISTER
CLEAR
(ACTIVE LOW)
LOGIC
GROUND
CURRENT LIMIT AND CHARGE PUMP
SUB
Power grounds must be connected together externally.
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
LATCHES
REGISTER SERIAL
DATA IN
REGISTER
CLEAR
OUT
3
V
DD
STROBE
CLOCK CLK
ST
Dwg. PP-029-16A
OUT
2
OUTPUT
ENABLE OE
LOGIC
GROUND
CLR
OUT
5
OUT
4
OUT
6
OUT
7
OUT
1
OUT
0
SERIAL
DATA OUT
LOGIC
SUPPLY
REGISTER
LATCHES
1
2
3
817
18
19
20
21
23
4
5
6
7
22
24
12
9
10
11
13
14
15
16
A6A595KLB (SOIC)
50 75 100 125 150
5
1
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
TEMPERATURE IN °C
4
3
2
25
Dwg. GP-049-5
SUFFIX 'LB', R = 6.0°C/W
θJT
R = 55°C/W
θJA
SUFFIX 'A', R = 25°C/W
θJC
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
3
TRUTH TABLE
Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Output
Input Input I0I1I2... I6I7Output Strobe I0I1I2... I6I7Enable I0I1I2…I
6I7
HHR
0R1…R
5R6R6
LLR
0R1…R
5R6R6
XR
0R1R2…R
6R7R7
XXX … XX X — R
0R1R2…R
6R7
P0P1P2…P
6P7P7P0P1P2…P
6P7LP
0P1P2…P
6P7
XXX … XX H HHH … HH
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
SERIAL DATA OUT
LOGIC INPUTS
Dwg. EP-063-4
OUT
VDD
DMOS POWER DRIVER OUTPUT
Dwg. EP-010-10
IN
VDD
Dwg. EP-063-5
OUT
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Breakdown V(BR)DSX IO = 1 mA 50 — — V
Voltage
Off-State Output IDSX VO = 40 V — 0.1 1.0 µA
Current VO = 40 V, TA = 125°C — 0.2 5.0 µA
Static Drain-Source rDS(on) IO = 350 mA — 1.0 1.5 Ω
On-State Resistance IO = 350 mA, TA = 125°C — 1.7 2.5 Ω
Source-Drain VSD IF = 350 mA — 0.9 1.1 V
Diode Voltage
Nominal Output IO(nom) VDS(on) = 0.5 V, TA = 85°C — 350 — mA
Current
Output Current IO(chop) IO at which chopping starts, TC = 25°C 0.6 0.8 1.1 A
Logic Input Current IIH VI = VDD — — 1.0 µA
IIL VI = 0 — — -1.0 µA
SERIAL-DATA VOH IOH = -20 µA 4.9 4.99 — V
Output Voltage IOH = -4 mA 4.5 4.7 — V
VOL IOL = 20 µA — 0 0.1 V
IOL = 4 mA — 0.3 0.5 V
Prop. Delay Time tPLH IO = 350 mA, CL = 30 pF — 100 — ns
tPHL IO = 350 mA, CL = 30 pF — 60 — ns
Output Rise Time trIO = 350 mA, CL = 30 pF — 55 — ns
Output Fall Time tfIO = 350 mA, CL = 30 pF — 40 — ns
Supply Current IDD(off) Outputs OFF — 0.5 5.0 mA
IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs OFF — 1.3 — mA
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%.
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
5
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT
ENABLE
OUT
N
Dwg. WP-029-2
50%
SERIAL
DATA OUT
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OUTN
Dwg. WP-030-2
DATA 10%
50%
PHL
tPLH
t
HIGH = ALL OUTPUTS DISABLED
90% f
tr
t
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D).......................................... 20 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CLK) ............................................. 40 ns
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) .............................................. 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
LOGIC SYMBOL
2
G3
C2
SRG8
C1
R
1D
2
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
SERIAL
DATA OUT
OUTPUT
ENABLE
STROBE
REGISTER
CLEAR
SERIAL
DATA IN
CLOCK
Dw
g
. FP-043-2
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
TEST CIRCUIT
Dwg. EP-066-2
OUT
INPUT
I
O
V
O
t
av
I
AS
= 600 mA
V
(BR)DSX
V
O(ON)
1 Ω
210 mH
+15 V
DUT
Single-pulse avalanche energy test circuit
and waveforms
EAS = IAS x V(BR)DSX x tAV/2
NORMAL LAMP IN-RUSH CURRENT
LAMP CURRENT
TIME
CURRENT LIMIT
(CHOPPING MODE)
ON ~ 40 µs
OFF ~ 2.5 ms
Dwg. WP-008-1
NOT TO SCALE
IO(chop)
CHOPPING-MODE OPERATION
High incandescent lamp turn-on currents (commonly
called in-rush currents) can contribute to poor lamp
reliability and destroy semiconductor lamp drivers.
Warming resistors protect both driver and lamp but use
significant power when the lamp is off while current-
limiting resistors waste power when the lamp is on.
Lamps with steady-state current ratings to 350 mA can be
driven by the A6A595 without the need for warming or
current limiting resistors.
As shown (the dashed line), when an incandescent
lamp is initially turned on, the cold filament is at mini-
mum resistance and will normally allow a 10x peak in-
rush current. As the lamp warms up, the filament resis-
tance increases to its rated value and the lamp current is
reduced to its steady-state rating. When switching a lamp
with the A6A595, the internal chopping circuitry limits
the current (the solid line) to IO(chop). The device will stay
in the chopping mode until the lamp resistance increases
and the current requirement is less than IO(chop). A side-
effect of this current-limiting feature is that lamp turn-on
time will increase.
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
7
TERMINAL DESCRIPTIONS
A6A595KA A6A595KLB
(DIP) (SOIC)
Terminal No. Terminal No. Terminal Name Function
1-2 1-2 OUT2-3 Current-sinking, open-drain DMOS output terminals.
3 3 REGISTER CLEAR When (active) low, the registers are cleared (set low).
4 4 OUTPUT ENABLE When (active) low, the output drivers are enabled; when
high, all output drivers are turned OFF (blanked).
5-6 5-8 POWER GROUND Reference terminal for output voltage measurements.
7 9 STROBE Data strobe input terminal; shift register data is latched
on rising edge.
8 10 CLOCK Clock input terminal for data shift on rising edge.
9-12 11-14 OUT4-7 Current-sinking, open-drain DMOS output terminals.
13 15 SERIAL DATA OUT CMOS serial-data output to the following shift register.
14 16 LOGIC GROUND Reference terminal for input voltage measurements.
15-16 17-20 POWER GROUND Reference terminal for output voltage measurements.
17 21 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V).
18 22 SERIAL DATA IN Serial-data input to the shift-register.
19-20 23-24 OUT0-1 Current-sinking, open-drain DMOS output terminals.
NOTE —Power grounds must be connected together externally.
0
Dwg. GP-073
50 150
100
CASE TEMPERATURE IN °C
-50
1.50
1.00
OUTPUT CURRENT LIMIT IN AMPERES
0.50
0
V
CC
= 5.5 V
0.25
0.75
1.25
V
CC
= 4.5 V
Typical output current limit as a function of
case temperature
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
A6A595KA
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
0.014
0.008
0.300
BSC
Dwg. MA-001-20 in
0.430
MAX
20
110
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
11
1.060
0.980
0.355
0.204
7.62
BSC
Dwg. MA-001-20 mm
10.92
MAX
20
110
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
11
26.92
24.89
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
www.allegromicro.com
9
A6A595KLB
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
0° TO 8
1 2 3
0.2992
0.2914
0.6141
0.5985
0.491
0.394
0.020
0.013
0.0926
0.1043
0.0040 MIN
.
0.0125
0.0091
Dwg. MA-008-25 in
0.050
BSC
24 13
NOTE 1
NOTE 3
0.050
0.016
0° TO 8
1 2 3
7.60
7.40
15.60
15.20
10.65
10.00
0.51
0.33
2.65
2.35
0.10
MIN
.
0.32
0.23
Dwg. MA-008-25A mm
1.27
BSC
24 13
NOTE 1
NOTE 3
1.27
0.40
NOTES:1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
6A595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
10
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
