PRELIMINARY CY7C1011 128K x 16 Static RAM Features (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). * High speed -- tAA = 15 ns * Low active power -- 1150 mW (max.) * Low CMOS standby power (L version) -- 40 mW (max.) * 2.0V Data Retention (4 mW at 2.0V retention) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes. The CY7C1011 is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable The CY7C1011 is available in a standard 44-pin TSOP II package with center power and ground (revolutionary) pinout. Functional Description Logic Block Diagram Pin Configuration 256K x 16 ARRAY 1024 x 4096 TSOP II Top View SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 I/O0 - I/O7 I/O8 - I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 COLUMN DECODER BHE WE CE OE BLE 1011-1 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 1011-2 Selection Guide 7C1011-15 7C1011-20 7C1011-25 15 20 25 230 220 200 8 8 8 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Cypress Semiconductor Corporation Com'l * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 19, 1998 PRELIMINARY CY7C1011 DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Range Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V Commercial Ambient Temperature[2] VCC 0C to +70C 5V 0.5 DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C1011-15 Parameter Description Test Conditions Min. 2.4 Max. 7C1011-20 Min. 7C1011-25 Max. Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC + 0.5 2.2 VCC + 0.5 2.2 VCC + 0.5 V VIL Input LOW Voltage[1] -0.5 0.8 -0.5 0.8 -0.5 0.8 V IIX Input Load Current GND < VI < VCC -1 +1 -1 +1 -1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled -1 +1 -1 +1 -1 +1 A ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 230 220 200 mA ISB1 Automatic CE Power-Down Current --TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 40 40 40 mA ISB2 Automatic CE Power-Down Current --CMOS Inputs Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 8 8 8 mA Max. Unit 8 pF 8 pF 2.4 2.4 0.4 Com'l V 0.4 0.4 V Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms ALL INPUT PULSES R1 481 R1 481 5V 3.0V 5V OUTPUT 90% OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 R2 255 5 pF INCLUDING JIG AND SCOPE (b) GND 3ns 10% 90% 10% 3 ns 1011-3 1011-4 THEVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: 2 PRELIMINARY CY7C1011 Switching Characteristics[4] Over the Operating Range 7C1011-15 Parameter Description Min. Max. 7C1011-20 Min. Max. 7C1011-25 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 15 20 25 ns tDOE OE LOW to Data Valid 7 8 10 ns tLZOE 15 20 15 3 [5] OE LOW to Low Z 20 3 0 [5, 6] 25 ns 25 3 0 ns ns 0 ns tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z[5] tHZCE CE HIGH to High Z[5, 6] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 15 20 25 ns tDBE Byte Enable to Data Valid 7 8 10 ns tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z WRITE 7 3 8 3 7 0 8 0 0 10 5 7 10 0 0 ns ns 0 8 ns ns ns 10 ns CYCLE[7,8] tWC Write Cycle Time 15 20 25 ns tSCE CE LOW to Write End 12 13 15 ns tAW Address Set-Up to Write End 12 13 15 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 12 13 15 ns tSD Data Set-Up to Write End 8 9 10 ns tHD Data Hold from Write End 0 0 0 ns tLZWE WE HIGH to Low Z[5] 3 3 5 ns [5, 6] tHZWE WE LOW to High Z tBW Byte Enable to End of Write 7 12 8 13 10 15 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 3 PRELIMINARY CY7C1011 Data Retention Characteristics Over the Operating Range Parameter Conditions[10] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[9] Operation Recovery Time Min. Max. 2.0 Com'l Unit V VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 2 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V tCDR 3.0V tR CE 1011-5 Switching Waveforms Read Cycle No. 1 [11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1011-6 Notes: 9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 12. WE is HIGH for read cycle. 4 PRELIMINARY CY7C1011 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE V CC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU IICC CC 50% 50% IISB SB 1011-7 Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O 1011-8 Notes: 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 5 PRELIMINARY CY7C1011 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O 1011-9 Write Cycle No.3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE 6 1011-10 PRELIMINARY CY7C1011 Truth Table CE OE WE BLE BHE H X X X X High Z I/O0-I/O7 High Z I/O8-I/O15 Power Down Mode Standby (ISB) Power L L H L L Data Out Data Out Read All bits Active (ICC) L L H L H Data Out High Z Read Lower bits only Active (ICC) L L H H L High Z Data Out Read Upper bits only Active (ICC) L X L L L Data In Data In Write All bits Active (ICC) L X L L H Data In High Z Write Lower bits only Active (ICC) L X L H L High Z Data In Write Upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type 15 CY7C1011-15VC Z44 44-Lead TSOP Type II 20 CY7C1011-20VC Z44 44-Lead TSOP Type II 25 CY7C1011-25ZC Z44 44-Lead TSOP Type II Operating Range Commercial Document #: 38-00744 Package Diagram 44-Pin TSOP II Z44 51-85087-A (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.