PRELIMINARY
128K x 16 Static RAM
CY7C1011
CypressSemiconductorCorporation •3901NorthFirstStreet •SanJose •CA 95134 •408-943-2600
November 19, 1998
Features
•High speed
—tAA = 15 ns
•Low active power
—1150 mW (max.)
•Low CMOS standby power (L version)
—40 mW (max.)
•2.0V Data Retention (4 mW at 2.0V retention)
•Automatic power-down when deselected
•TTL-compatible inputs and outputs
•Easy memory expansion with CE and OE features
Functional Description
The CY7C1011 is a high-performance CMOS static RAM or-
ganized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location speci-
fied on the address pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O0 to I/O7. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011 is available in a standard 44-pin TSOP II pack-
age with center power and ground (revolutionary) pinout.
14
15
Logic Block Diagram Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K x 16
ARRAY
A0
A11
A13
A12
A
A
A16
1011–2
A9
A10
1024 x 4096
I/O0 – I/O7
OE
I/O8 – I/O15
CE
WE
BLE
BHE WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
12
13
41
44
43
42
16
15 29
30
VCC
A16
A15
A14
A13
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
1011–1 A12 NC
NC
TSOP II
Selection Guide 7C1011-15 7C1011-20 7C1011-25
Maximum Access Time (ns) 15 20 25
Maximum Operating Current (mA) 230 220 200
Maximum CMOS Standby Current (mA) Com’l 8 8 8
CY7C1011
PRELIMINARY
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C5V ± 0.5
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C1011-15 7C1011-20 7C1011-25
Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 2.2 VCC + 0.5 2.2 VCC + 0.5 V
VIL Input LOW Voltage[1] –0.5 0.8 –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VOUT < VCC,
Output Disabled –1 +1 –1 +1 –1 +1 µA
ICC VCC Operating
Supply Current VCC = Max.,
f = fMAX = 1/tRC 230 220 200 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40 40 40 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
Com’l 8 8 8 mA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 8pF
COUT I/O Capacitance 8pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
1011–3 1011–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 3ns ≤3ns
OUTPUT
R1 481ΩR1 481Ω
R2
255ΩR2
255Ω
167Ω
Equivalentto: VENIN EQUIVALENT
1.73V
THÉ
CY7C1011
PRELIMINARY
3
Switching Characteristics[4] Over the Operating Range
7C1011-15 7C1011-20 7C1011-25
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 15 20 25 ns
tAA Address to Data Valid 15 20 25 ns
tOHA Data Hold from Address Change 3 3 3 ns
tACE CE LOW to Data Valid 15 20 25 ns
tDOE OE LOW to Data Valid 7 8 10 ns
tLZOE OE LOW to Low Z[5] 0 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 7 8 10 ns
tLZCE CE LOW to Low Z[5] 3 3 5 ns
tHZCE CE HIGH to High Z[5, 6] 7 8 10 ns
tPU CE LOW to Power-Up 0 0 0 ns
tPD CE HIGH to Power-Down 15 20 25 ns
tDBE Byte Enable to Data Valid 7 8 10 ns
tLZBE Byte Enable to Low Z 0 0 0 ns
tHZBE Byte Disable to High Z 7 8 10 ns
WRITE CYCLE[7,8]
tWC Write Cycle Time 15 20 25 ns
tSCE CE LOW to Write End 12 13 15 ns
tAW Address Set-Up to Write End 12 13 15 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE WE Pulse Width 12 13 15 ns
tSD Data Set-Up to Write End 8 9 10 ns
tHD Data Hold from Write End 0 0 0 ns
tLZWE WE HIGH to Low Z[5] 3 3 5 ns
tHZWE WE LOW to High Z[5, 6] 7 8 10 ns
tBW Byte Enable to End of Write 12 13 15 ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1011
PRELIMINARY
4
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions[10] Min. Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current Com’l VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2mA
tCDR[3]Chip Deselect to Data Retention Time 0ns
tR[9]Operation Recovery Time tRC ns
Data Retention Waveform
1011–5
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Notes:
9. tr < 3 ns for the –12 and –15 speeds. tr < 5 ns for the –20 and slower speeds.
10. No input may exceed VCC + 0.5V.
11. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL.
12. WE is HIGH for read cycle.
Read Cycle No. 1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
1011-6
ADDRESS
DATAOUT
[11, 12]
CY7C1011
PRELIMINARY
5
Notes:
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
Read Cycle No. 2(OEControlled)
1011-7
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
[12, 13]
CURRENT
ICC
ISB
Write Cycle No. 1 (CE Controlled)
1011-8
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
BHE, BLE
[14, 15]
t
CY7C1011
PRELIMINARY
6
Switching Waveforms (continued)
Write Cycle No. 2 (BLEorBHE Controlled)
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATAI/O
ADDRESS
BHE,BLE
WE
CE
1011-9
Write Cycle No.3(WE Controlled,OE LOW)
1011-10
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
CY7C1011
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00744
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
HX X X X High Z High Z Power Down Standby (ISB)
L L HL L Data Out Data Out Read All bits Active (ICC)
L L HLHData Out High Z Read Lower bits only Active (ICC)
L L H H LHigh Z Data Out Read Upper bits only Active (ICC)
LXL L L Data In Data In Write All bits Active (ICC)
LXL L HData In High Z Write Lower bits only Active (ICC)
LXLHLHigh Z Data In Write Upper bits only Active (ICC)
LH H X X High Z High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
15 CY7C1011-15VC Z44 44-Lead TSOP Type II Commercial
20 CY7C1011-20VC Z44 44-Lead TSOP Type II
25 CY7C1011-25ZC Z44 44-Lead TSOP Type II
Package Diagram
44-Pin TSOP II Z44
51-85087-A
