AS7C31026C-10TIN - Alliance Memory, Inc.

September 2006

Advance Information

AS7C31026C

3.3 V 64K X 16 CMOS SRAM

9/20/06, v 1.0 Alliance Memory P. 1 of 10

Features

• Industrial (-40o to 85oC) temperature

• Organization: 65,536 words × 16 bits

• Center power and ground pins for low noise

• High speed

- 10 ns address access time

- 5 ns output enable access time

• Low power consumption via chip deselect

• Upper and Lower byte pin

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packaging

- 44-pin 400 mi l SO J

- 44-pin TSOP 2-400

- 48-ball 6 × 8 mm BGA

• ESD protection ≥ 2000 volts

Logic block diagram

65,536 × 16

Array

WE Address decoder

Address decoder

VCC

GND

A10

A11

A12

A13

A14

A15

Control circuit

I/O0–I/O7

I/O8–I/O15

I/O

buffer

A6 5

I/O13

I/O12

GND

VCC

I/O11

I/O10

I/O9

I/O8

A10

A11

I/O0

I/O1

I/O2

I/O3

VCC

GND

I/O4

I/O5

I/O6

I/O7

A15

A14

A13

44-Pin SOJ (400 mil), TSOP 2

A12

I/O15

I/O14

A3 3

A2 4

44 A6

AS7C31026C

Pin arrangement

0000048 - BGA Ball-Grid-Array Package

123456

ALBOE A0A1A2NC

BI/O8UB A3 A4 CE I/O0

CI/O9

I/O10

A5 A6 I/O1 I/O2

I/O11

NC A7 I/O3 VDD

I/O12

NC NC I/O4 VSS

FI/O14

I/O13

A14 A15 I/O5 I/O6

G I/O15 NC A12 A13 WE I/O7

HNC A8 A9A10A11NC

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 2 of 10

Functional description

The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized

as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing

are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10 ns with output enable access times (tOE) of 5 ns are ideal for high-

performance applications.

When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip

enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle

2). To avoid bus contention , external devices should drive I/O pins only after outputs have been disabled with output enable

(OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips

drive I/O pins wit h the data word referenced by t he input add ress. When either chip enable or output enable is inactive or write

enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be

written and read. LB controls the lower bits , I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.

All chip inputs and ou tputs are TTL-compatibl e, and operation is from a single 3.3 V suppl y. The AS7C31026C is packaged in

common industry standard packages.

Note: Stresses greater than those listed under Absolute Maximum Ratings may cau se permanent damage to the device. This is a stress rating only and func -

tional operation of the devic e at these or any other co nditions outsid e those indicated in the operational sectio ns of this specification is not implied. Exposure

to absolute maximum rating co nditions for extended periods may affect reliability.

Key: H = high, L = low, X = don’t care.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on VCC relative to GND Vt1 –0.50 +4.60 V

Voltage on any pin rela tive to GND Vt2 –0.50 VCC +0.50 V

Power dissipation PD–1.25W

Storage temperature (plastic) Tstg –55 +125 °C

Ambient temperature with VCC applied Tbias –55 +125 °C

DC current into outputs (low) IOUT –50mA

Truth table

CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

HXXXXHigh ZHigh Z Standby (I

SB), ISBI)

LHLLHD

OUT High Z Read I/O0–I/O7 (ICC)

LHLHLHigh ZD

OUT Read I/O8–I/O15 (ICC)

LHLLLD

OUT DOUT Read I/O0–I/O15 (ICC)

LLXLL D

IN DIN Write I/O0–I/O15 (ICC)

LLXLH D

IN High Z Write I/O0–I/O7 (ICC)

LLXHLHigh ZD

IN Write I/O8–I/O15 (ICC)

HHigh Z High Z Output disable (ICC)

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 3 of 10

VIL = -2.0V for pulse width less than 5ns, once per cycle.

VIH = VCC +2.0V for pulse width less than 5ns, once per cycle.

Recommended operating conditions

Parameter Symbol Min Nominal Max Unit

Supply voltag e VCC 3.0 3.3 3.6 V

Input voltage VIH 2.0 – VCC + 0.5 V

VIL –0.5 – 0.8 V

Ambient operating temperature (industrial) TA–40 – 85 o C

DC operating characteristics (over the operating range)1

Parameter Sym Test conditions

AS7C31026C-10

UnitMin Max

Input leakage current | ILI | VCC = Max

VIN = GND to VCC –5µA

Output leakage current | ILO |

VCC = Max

CE = VIH,

VOUT = GND to VCC

–5µA

Operating power supply current ICC

VCC = Max,

CE ≤ VIL, IOUT = 0mA

f = fMax

– 160 mA

Standby power supply current

ISB VCC = Max,

CE ≥ VIH, f = fMax –45

ISB1

VCC = Max, CE ≥ VCC–0.2 V,

VIN ≤ 0.2 V or

VIN ≥ VCC–0.2 V, f = 0 –10

Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V

VOH IOH = –4 mA, VCC = Min 2.4 – V

Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2

Parameter Symbol Signals Test cond itions Max Unit

Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0 V 6 pF

I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF

Note:

1. This parameter is guaranteed by device characterization, but is not production tested.

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 4 of 10

Key to switching waveforms

Read waveform 1 (address controlled)3,6,7,9

Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9

Read cycle (over the operating range)3,9

Parameter Symbol

AS7C31026C-10

Unit NotesMin Max

Read cycle time tRC 10 – ns

Address access time tAA –10ns3

Chip enable (CE) access time tACE –10ns3

Output enable (OE) access time tOE –5ns

Output hold from address change tOH 4–ns5

CE low to output in low Z tCLZ 4 – ns 4, 5

CE high to output in high Z tCHZ – 5 ns 4, 5

OE low to output in low Z tOLZ 0 – ns 4, 5

Byte select access time tBA –5ns

Byte select Low to low Z tBLZ 0 – ns 4, 5

Byte select High to high Z tBHZ – 5 ns 4, 5

OE high to output in hi gh Z tOHZ – 5 ns 4, 5

Power up time tPU 0 – ns 4, 5

Power down time tPD –10ns4, 5

Undefined output/do n’t careFalling inputRising input

Data

OUT

Address

Data validPrevious data valid

Data valid

BLZ

OLZ

OHZ

BHZ

ACE

Address

LB, UB

Data

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 5 of 10

Write waveform 1 (WE controlled)10,11

Write cycle (over the operating range) 11

Parameter Symbol

AS7C31026C-10

Unit NotesMin Max

Write cycle time tWC 10 – ns

Chip enable (CE) to write end tCW 7–ns

Address setup to write end tAW 7–ns

Address setup time tAS 0–ns

Write pulse width tWP 7–ns

Write recovery time tWR 0–ns

Address hold from end of write tAH 0–ns

Data valid to write e nd tDW 5–ns

Data hold time tDH 0–ns5

Write enable to output in high Z tWZ – 5 ns 4, 5

Output active from write end tOW 3 – ns 4, 5

Byte select low to end of write tBW 7–ns

Address

LB, UB

Data

OUT

Data undefined high Z

Data valid

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 6 of 10

Write waveform 2 (CE controlled)10,11

AC test conditions

Notes

1 During VCC power-up , a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A and B.

4 These pa rame ters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.

5 Thi s pa rameter is guaranteed, but not tested.

6WE

is high for read cycl e.

7CE

and OE are low for read cy cle.

8 Address is valid prior to or coincident with CE transitio n low.

9 All rea d cycle timings are referenced from the last valid add res s to the first transitioning address.

10 N/A

11 All write cycle timings are referenc ed from the last valid addre ss to the first transitioning address.

12 Not applicable.

13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.

Address

LB, UB

Data

OUT

Data undefined

high Z high Z

Data valid

CLZ

255

320

GND

+3.3 V

Figure B: 3.3 V Output load

168

Thevenin Equivalent:

OUT

+1.728 V

10%

90%

10%

90%

GND

+3.0 V

Figure A: Input pulse

3 ns

OUT

– Output load: see Figure B.

– Input pulse level: GND to 3.0 V. See Figure A.

– Input rise and fall times: 3 ns. See Figure A.

– Input and output timing reference levels: 1.5

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 7 of 10

Package dimensions

44-pin TSOP 2

Min

(mm) Max

(mm)

A1.2

A1 0.05 0.15

A2 0.95 1.05

b0.30 0.45

c0.120 0.21

D18.31 18.52

E10.06 10.26

He 11.68 11.94

e0.80 (typical)

l0.40 0.60

1234567891011121314

444342414039 3837 3635 343332 31

1516

3029

1718 1920

2827 26 25

44-pin TSOP 2

0–5

Seating

plane

44-pin SOJ

400 mil

Min (in) Max (in)

A0.128 0.148

A10.025 –

A20.105 0.115

B0.026 0.032

b0.015 0.020

c0.007 0.013

D1.120 1.130

E0.370 NOM

E10.395 0.405

E20.435 0.445

e0.050 NOM

Pin 1

AA2

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 8 of 10

Notes

1 Bump cou nts: 48 (8 row x 6 co lumn ).

2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ).

3 Units: millimeters.

4 All tolera nce are +/- 0.050 unless otherwise specified.

5 Typ: typical.

6 Y is cop l anarity: 0.010 (max ).

7 “A1” ID corner must be identified by chamfer , ink mark,

metallized marking, indentation or other feature on the pack-

age body.

8 If “A1” ID corner is on the package body, it must be located

within the zone indicated.

Minimum Typical Maximum

A–0.75–

B6.00 BSC

B1 –3.75–

C8.00 BSC

C1 –5.25–

D0.25 0.30 0.40

E0.14 1.24 1..34

E1 –0.68–

E2 0.15 0.20 0.25

Y– – 0.010

48-ball BGA

Bottom View

654321 Ball A1

Side View

Top View

Ball #A1 index (see note 7)

SRAM DIE

Detail View

Die

0.3/T

Die

*pin 1 indicator wi l l sh ow as

engraved circle and/or Inc. trade mark

B/4

C/4

(see note 8)

AS7C31026C

9/20/06, v 1.0 Alliance Memory P. 9 of 10

Ordering codes

Package Volt/Temp 10 ns

Plastic SOJ, 400 mil 3.3V industrial AS7C31026C-10JIN

TSOP 2, 10.2 x 18.4 mm 3.3V industrial AS7C31026C-10TIN

BGA, 7 x 7 mm 3.3V industrial AS7C31026C-10BIN

Part numbering system

AS7C X1026B –XX X X X

SRAM

prefix

Voltage:

3 = 3.3 V

CMOS

Device

number

Access

time

Package:

J = SOJ 400 mil

T = TSOP 2, 10.2 x 18.4 mm

B=BGA, 7 x 7 mm

Temperature

I = industrial: -40° C

to 85° C N = Lead Free Part

Alliance Memory, Inc.

1116 South Amphlett

San Mateo, CA 94402

Tel: 650-525-3737

Fax: 650-525-0449

www.alliancememory.com

Part Number: AS7C31026C

Document Version: v 1.0

All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its

products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents

Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the

product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended

to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user

or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any

express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,

merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are

available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products

from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of

Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may

reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the

manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

AS7C31026C