MAX6746KA23/V+T - Maxim Integrated Products, Inc.

General Description

The MAX6746–MAX6753 low-power microprocessor

(µP) supervisory circuits monitor single/dual system

supply voltages from 1.575V to 5V and provide maxi-

mum adjustability for reset and watchdog functions.

These devices assert a reset signal whenever the VCC

supply voltage or RESET IN falls below its reset thresh-

old or when manual reset is pulled low. The reset output

remains asserted for the reset timeout period after VCC

and RESET IN rise above the reset threshold. The reset

function features immunity to power-supply transients.

The MAX6746–MAX6753 have ±2% factory-trimmed

reset threshold voltages in approximately 100mV incre-

ments from 1.575V to 5.0V and/or adjustable reset

threshold voltages using external resistors.

The reset and watchdog delays are adjustable with

external capacitors. The MAX6746–MAX6751 contain a

watchdog select input that extends the watchdog time-

out period by 128x. The MAX6752/MAX6753 contain a

window watchdog timer that looks for activity outside an

expected window of operation.

The MAX6746–MAX6753 are available with a push-pull

or open-drain active-low RESET output. The MAX6746–

MAX6753 are available in an 8-pin SOT23 package and

are fully specified over the automotive temperature

range (-40°C to +125°C).

Applications

Features

oFactory-Set Reset Threshold Options from 1.575V

to 5V in ~100mV Increments

oAdjustable Reset Threshold Options

oSingle/Dual Voltage Monitoring

oCapacitor-Adjustable Reset Timeout

oCapacitor-Adjustable Watchdog Timeout

oMin/Max (Windowed) Watchdog Option

oManual Reset Input Option

oGuaranteed RESET Valid for VCC ≥1V

o3.7µA Supply Current

oPush-Pull or Open-Drain RESET Output Options

oPower-Supply Transient Immunity

oSmall 8-Pin SOT23 Packages

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

________________________________________________________________

Maxim Integrated Products

WDI

WDSGND

VCC

RESETSWT

SRT

RESET IN (MR)

( ) ARE FOR MAX6746 AND MAX6747 ONLY.

TOP VIEW

MAX6746–

MAX6751

SOT23-8

Pin Configurations

19-2530; Rev 6; 4/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Note: “_ _” represents the two number suffix needed when

ordering the reset threshold voltage value for the

MAX6746/MAX6747 and MAX6750–MAX6753. The reset

threshold voltages are available in approximately 100mV incre-

ments. Table 2 contains the suffix and reset factory-trimmed

voltages. All devices are available in tape-and-reel only. There

is a 2500-piece minimum order increment for standard ver-

sions (see Table 3). Sample stock is typically held on standard

versions only. Nonstandard versions require a minimum order

increment of 10,000 pieces. Contact factory for availability.

Devices are available in both leaded and lead-free packaging.

Specify lead-free by replacing “-T” with “+T” when ordering.

/V Denotes an automotive qualified part.

Medical Equipment

Automotive

Intelligent Instruments

Portable Equipment

Battery-Powered

Computers/Controllers

Embedded Controllers

Critical µP Monitoring

Set-Top Boxes

Computers

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX6746KA_ _-T -40°C to +125°C 8 SOT23

MAX6746KA_ _/V+T -40°C to +125°C 8 SOT23

MAX6747KA_ _-T -40°C to +125°C 8 SOT23

MAX6747KA_ _/V+T -40°C to +125°C 8 SOT23

MAX6748KA-T -40°C to +125°C 8 SOT23

MAX6749KA-T -40°C to +125°C 8 SOT23

MAX6750KA_ _-T -40°C to +125°C 8 SOT23

MAX6750KA_ _/V+T -40°C to +125°C 8 SOT23

MAX6751KA_ _-T -40°C to +125°C 8 SOT23

MAX6752KA_ _-T -40°C to +125°C 8 SOT23

MAX6753KA_ _-T -40°C to +125°C 8 SOT23

MAX6753KA_ _/V+T -40°C to +125°C 8 SOT23

Selector Guide appears at end of data sheet.

Typical Operating Circuit appears at end of data sheet.

Pin Configurations continued at end of data sheet.

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VCC to GND...........................................................-0.3V to +6.0V

SRT, SWT, SET0, SET1, RESET IN, WDS, MR,

WDI, to GND .......................................…-0.3V to (VCC + 0.3V)

RESET (Push-Pull) to GND......................…-0.3V to (VCC + 0.3V)

RESET (Open Drain) to GND .............................…-0.3V to +6.0V

Input Current (All Pins) .....................................................±20mA

Output Current (RESET) ...................................................±20mA

Continuous Power Dissipation (TA= +70°C)

8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW

Operating Temperature Range .........................-40°C to +125°C

Storage Temperature Range ............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TA = 0°C to +125°C 1.0 5.5

Supply Voltage VCC TA = -40°C to 0°C 1.2 5.5 V

VCC ≤ 5.5V 5 10

VCC ≤ 3.3V 4.2 9

Supply Current ICC

VCC ≤ 2.0V 3.7 8

µA

VCC Reset Threshold VTH See VTH

selection table TA = -40°C to+125°C VTH -

VTH +

2% V

Hysteresis VHYST 0.8 %

VCC to Reset Delay VCC falling from VTH + 100mV to VTH -

100mV at 1mV/µs 20 µs

CSRT = 1500pF 5.692 7.590 9.487

Reset Timeout Period tRP CSRT = 100pF 0.506 ms

SRT Ramp Current IRAMP VSRT = 0 to 1.23V; VCC = 1.6V to 5V 200 250 300 nA

SRT Ramp Threshold VRAMP VCC = 1.6V to 5V (VRAMP rising) 1.173 1.235 1.297 V

CSWT = 1500pF 5.692 7.590 9.487

Normal Watchdog Timeout Period

(MAX6746–MAX6751) tWD CSWT = 100pF 0.506 ms

CSWT = 1500pF 728.6 971.5 1214.4

Extended Watchdog Timeout

(MAX6746–MAX6751) tWD CSWT = 100pF 64.77 ms

CSWT = 1500pF 728.6 971.5 1214.4

Slow Watchdog Period

(MAX6752/MAX6753) tWD2 CSWT = 100pF 64.77 ms

CSWT = 1500pF 91.08 121.43 151.80

Fast Watchdog Timeout Period,

SET Ratio = 8,

(MAX6752/MAX6753)

tWD1

CSWT = 100pF 8.09

CSWT = 1500pF 45.53 60.71 75.89

Fast Watchdog Timeout Period,

SET Ratio = 16,

(MAX6752/MAX6753)

tWD1

CSWT = 100pF 4.05

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CSWT = 1500pF 11.38 15.18 18.98

Fast Watchdog Timeout Period,

SET Ratio = 64,

(MAX6752/MAX6753)

tWD1

CSWT = 100pF 1.01

Fast Watchdog Minimum Period

(MAX6752/MAX6753) 2000 ns

SWT Ramp Current IRAMP VSWT = 0 to 1.23V, VCC = 1.6V to 5V 200 250 300 nA

SWT Ramp Threshold VRAMP VCC = 1.6V to 5V (VRAMP rising) 1.173 1.235 1.297 V

VCC ≥ 1.0V, ISINK = 50µA 0.3

VCC ≥ 2.7V, ISINK = 1.2mA 0.3

RESET Output-Voltage LOW

Open-Drain, Push-Pull

(Asserted)

VOL

VCC ≥ 4.5V, ISINK = 3.2mA 0.4

VCC ≥ 1.8V, ISOURCE = 200µA 0.8 x VCC

VCC ≥ 2.25V, ISOURCE = 500µA 0.8 x VCC

RESET Output-Voltage HIGH,

Push-Pull (Not Asserted) VOH

VCC ≥ 4.5V, ISOURCE = 800µA 0.8 x VCC

RESET Output Leakage Current,

Open Drain ILKG VCC > VTH, reset not asserted,

V RESET = 5.5V 1.0 µA

DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS)

VIL 0.8

VIH

VCC ≥ 4.0V 2.4

VIL VCC < 4.0V 0.3 x VCC

Input Logic Levels

VIH 0.7 x VCC

MR Minimum Pulse Width 1µs

MR Glitch Rejection 100 ns

MR to RESET Delay 200 ns

MR Pullup Resistance Pullup to VCC 12 20 28 kΩ

WDI Minimum Pulse Width 300 ns

RESET IN

RESET IN Threshold VRESET IN TA = -40°C to +125°C 1.216 1.235 1.254 V

RESET IN Leakage Current IRESET IN -50 ±1 +50 nA

RESET IN to RESET Delay RESET IN falling at 1mV/µs 20 µs

Note 1: Production testing done at TA= +25°C. Over temperature limits are guaranteed by design.

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

4 _______________________________________________________________________________________

Typical Operating Characteristics

(VCC = +5V, TA = +25°C, unless otherwise noted.)

RESET TIMEOUT PERIOD vs. CSRT

MAX6746 toc01

CSRT (pF)

RESET TIMEOUT PERIOD (ms)

10,0001000

100

1000

0.1

100 100,000

WATCHDOG TIMEOUT PERIOD vs. CSWT

MAX6746 toc02

CSWT (pF)

WATCHDOG TIMEOUT PERIOD (ms)

10,0001000

100

1000

10,000

100,000

0.1

100 100,000

MAX6746–MAX6751

EXTENDED MODE

NORMAL MODE

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX6746 toc03

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (μA)

5432

NORMALIZED RESET TIMEOUT PERIOD

vs. TEMPERATURE

MAX6746 toc04

TEMPERATURE (°C)

NORMALIZED TIMEOUT PERIOD

1007550250-25

0.95

1.00

1.05

1.10

1.15

1.20

0.90

-50 125

CSRT = 100pF

CSRT = 1500pF

NORMALIZED WATCHDOG TIMEOUT PERIOD

vs. TEMPERATURE

MAX6746 toc05

TEMPERATURE (°C)

NORMALIZED TIMEOUT PERIOD

1007550250-25

0.95

0.90

0.85

1.00

1.05

1.10

1.15

1.20

0.80

-50 125

CSWT = 100pF

CSWT = 1500pF

MAXIMUM TRANSIENT DURATION

vs. RESET THRESHOLD OVERDRIVE

MAX6746 toc06

RESET THRESHOLD OVERDRIVE (mV)

TRANSIENT DURATION (μs)

800600400200

100

125

150

175

0 1000

RESET OCCURS

ABOVE THE CURVE

VTH = 2.92V

SUPPLY CURRENT

vs. TEMPERATURE

MAX6746 toc07

TEMPERATURE (°C)

SUPPLY CURRENT (μA)

1007525 500-25

-50 125

VCC = 3.3V

VCC = 1.8V

VCC = 5V

NORMALIZED RESET IN THRESHOLD VOLTAGE

vs. TEMPERATURE

MAX6746 toc08

TEMPERATURE (°C)

NORMALIZED RESET THRESHOLD VOLTAGE

1007550250-25

0.994

0.992

0.996

1.000

0.998

1.004

1.002

1.008

1.006

1.010

0.990

-50 125

VCC = 5V

RESET IN THRESHOLD

vs. SUPPLY VOLTAGE

MAX6746 toc08b

SUPPLY VOLTAGE (V)

RESET IN THRESHOLD (V)

5432

1.236

1.237

1.238

1.239

1.240

1.235

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

_______________________________________________________________________________________ 5

VCC TO RESET DELAY

vs. TEMPERATURE (VCC FALLING)

MAX6746 toc09

TEMPERATURE (°C)

VCC TO RESET DELAY (μs)

1007550250-25

25.4

25.8

26.2

26.6

27.0

25.0

-50 125

VCC FALLING AT 1mV/μs

RESET AND WATCHDOG

TIMEOUT PERIOD vs. SUPPLY VOLTAGE

MAX6746 toc10

VCC (V)

TIMEOUT PERIOD (ms)

5.55.04.0 4.52.5 3.0 3.52.0

0.44

0.48

0.52

0.56

0.60

0.40

1.5 6.0

CSWT = CSRT = 100pF

Typical Operating Characteristics (continued)

(VCC = +5V, TA = +25°C, unless otherwise noted.)

RESET AND WATCHING TIMEOUT

PERIOD vs. SUPPLY VOLTAGE

MAX6746 toc11

VCC (V)

TIMEOUT PERIOD (ms)

5.55.04.54.03.53.02.52.0

6.5

7.0

7.5

8.0

8.5

9.0

6.0

1.5 6.0

CSWT = CSRT = 1500pF

RESET

WATCHDOG

Pin Description

MAX6746

MAX6747

MAX6748–

MAX6751

MAX6752

MAX6753

NAME FUNCTION

1——MR Manual Reset Input. Pull MR low to manually reset the device. Reset

remains asserted for the reset timeout period after MR is released.

— 1 — RESET IN

Reset Input. High-impedance input to the adjustable reset comparator.

Connect RESET IN to the center point of an external resistor-divider to

set the threshold of the externally monitored voltage.

— — 1 SET0 Logic Input. SET0 selects watchdog window ratio or disables the

watchdog timer. See Table 1.

2 2 2 SWT

Watchdog Timeout Input.

MAX6746–MAX6751: Connect a capacitor between SWT and ground to

set the basic watchdog timeout period (tWD). Determine the period by

the formula tWD = 5.06 x 106 x CSWT with tWD in seconds and CSWT in

Farads. Extend the basic watchdog timeout period by using the WDS

input. Connect SWT to ground to disable the watchdog timer function.

MAX6752/MAX6753: Connect a capacitor between SWT and ground to

set the slow watchdog timeout period (tWD2). Determine the slow

watchdog period by the formula: tWD2 = 0.65 x 109 x CSWT with tWD2 in

seconds and CSWT in Farads. The fast watchdog timeout period is set

by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to

disable the watchdog timer function.) See Table 1.

3 3 3 SRT

Reset Timeout Input. Connect a capacitor from SRT to GND to select

the reset timeout period. Determine the period as follows: tRP = 5.06 x

106 x CSRT with tRP in seconds and CSRT in Farads.

4 4 4 GND Ground

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

6 _______________________________________________________________________________________

Pin Description (continued)

MAX6746

MAX6747

MAX6748–

MAX6751

MAX6752

MAX6753

NAME FUNCTION

5 5 — WDS

Watchdog Select Input. WDS selects the watchdog mode. Connect

WDS to ground to select normal mode and the watchdog timeout

period. Connect WDS to VCC to select extended mode, multiplying the

basic timeout period by a factor of 128. A change in the state of WDS

clears the watchdog timer.

— — 5 SET1 Logic Input. SET1 selects the watchdog window ratio or disables the

watchdog timer. See Table 1.

6 6 6 WDI

Watchdog Input.

MAX6746–MAX6751: A falling transition must occur on WDI within the

selected watchdog timeout period or a reset pulse occurs. The

watchdog timer clears when a transition occurs on WDI or whenever

RESET is asserted. Connect SWT to ground to disable the watchdog

timer function.

MAX6752/MAX6753: WDI falling transitions within periods shorter than

tWD1 or longer than tWD2 force RESET to assert low for the reset timeout

period. The watchdog timer begins to count after RESET is deasserted.

The watchdog timer clears when a valid transition occurs on WDI or

whenever RESET is asserted. Connect SET0 high and SET1 low to

disable the watchdog timer function. See the Watchdog Timer section.

777RESET

Push/Pull or Open-Drain Reset Output. RESET asserts whenever VCC or

RESET IN drops below the selected reset threshold voltage (VTH or

VRESET IN, respectively) or manual reset is pulled low. RESET remains

low for the reset timeout period after all reset conditions are deasserted,

and then goes high. The watchdog timer triggers a reset pulse (tRP)

whenever a watchdog fault occurs.

888V

CC Supply Voltage. VCC is the power-supply input and the input for fixed

threshold VCC monitor.

Detailed Description

The MAX6746–MAX6753 assert a reset signal whenever

the VCC supply voltage or RESET IN falls below its reset

threshold. The reset output remains asserted for the

reset timeout period after VCC and RESET IN rise above

its respective reset threshold. A watchdog timer triggers

a reset pulse whenever a watchdog fault occurs.

The reset and watchdog delays are adjustable with

external capacitors. The MAX6746–MAX6751 contain a

watchdog select input that extends the watchdog time-

out period to 128x.

The MAX6752 and MAX6753 have a sophisticated

watchdog timer that detects when the processor is run-

ning outside an expected window of operation. The

watchdog signals a fault when the input pulses arrive too

early (faster that the selected tWD1 timeout period) or too

late (slower than the selected tWD2 timeout period) (see

Figure 1).

Reset Output

The reset output is typically connected to the reset input

of a µP. A µP’s reset input starts or restarts the µP in a

known state. The MAX6746–MAX6753 µP supervisory

circuits provide the reset logic to prevent code-execu-

tion errors during power-up, power-down, and

brownout conditions (see the

Typical Operating Circuit

RESET changes from high to low whenever the moni-

tored voltage, RESET IN and/or VCC drop below the

reset threshold voltages. Once VRESET IN and/or VCC

exceeds its respective reset threshold voltage(s),

RESET remains low for the reset timeout period, then

goes high.

RESET is guaranteed to be in the correct logic state for

VCC greater than 1V. For applications requiring valid

reset logic when VCC is less than 1V, see the section

Ensuring a Valid RESET Output Down to V

= 0V.

RESET IN Threshold

The MAX6748–MAX6751 monitor the voltage on RESET IN

using an adjustable reset threshold (VRESET IN) set with

an external resistor voltage-divider (Figure 2). Use the

following formula to calculate the externally monitored

voltage (VMON_TH):

VMON_TH = VRESET IN x (R1 + R2) / R2

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

_______________________________________________________________________________________ 7

Figure 1. MAX6752/MAX6753 Detailed Watchdog Input Timing Relationship

MAX6748

MAX6749

MAX6750

MAX6751

RESET IN

GND

VCC

VMON_TH

VMON_TH = 1.235 x (R1 + R2) / R2

Figure 2. Calculating the Monitored Threshold Voltage

(VMON_TH)

WDI CONDITION 1

WDI CONDITION 2

WDI CONDITION 3

GUARANTEED TO

NOT ASSERT

RESET

GUARANTEED TO

ASSERT

RESET

tWD1 (MIN) tWD1 (MAX)

*UNDETERMINED *UNDETERMINED

FAST FAULT

NORMAL OPERATION

SLOW FAULT

*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION

GUARANTEED

TO ASSERT

RESET

tWD2 (MIN) tWD2 (MAX)

MAX6746–MAX6753

where VMON_TH is the desired reset threshold voltage

and VTH is the reset input threshold (1.235V). Resistors

R1 and R2 can have very high values to minimize cur-

rent consumption due to low leakage currents. Set R2

to some conveniently high value (500kΩ, for example)

and calculate R1 based on the desired reset threshold

voltage, using the following formula:

R1 = R2 x (VMON_TH/VRESET IN - 1) (Ω)

The MAX6748 and MAX6749 do not monitor VCC sup-

ply voltage, therefore, VCC must be greater than 1.5V to

guarantee RESET IN threshold accuracy and timing

performance. The MAX6748 and MAX6749 can be con-

figured to monitor VCC voltage by connecting VCC to

VMON_TH.

Dual-Voltage Monitoring

(MAX6750/MAX6751)

The MAX6750 and MAX6751 contain both factory-

trimmed threshold voltages and an adjustable reset

threshold input, allowing the monitoring of two voltages,

VCC and VMON_TH (see Figure 2). RESET is asserted

when either of the voltages falls below it respective

threshold voltages.

Manual Reset (MAX6746/MAX6747)

Many µP-based products require manual reset capabil-

ity, to allow an operator or external logic circuitry to initi-

ate a reset. The manual reset input (MR) can connect

directly to a switch without an external pullup resistor or

debouncing network. MR is internally pulled up to VCC

and, therefore, can be left unconnected if unused.

MR is designed to reject fast, falling transients (typically

100ns pulses) and it must be held low for a minimum of

1µs to assert the reset output. A 0.1µF capacitor from

MR to ground provides additional noise immunity. After

MR transitions from low to high, reset remains asserted

for the duration of the reset timeout period.

A manual reset option can easily be implemented

with the MAX6748–MAX6751 by connecting a normally

open momentary switch in parallel with R2 (Figure 3).

When the switch is closed, the voltage on RESET IN

goes to zero, initiating a reset. Similar to the MAX6746/

MAX6747 manual reset, reset remains asserted while

the voltage at RESET IN is zero and for the reset time-

out period after the switch is opened.

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

8 _______________________________________________________________________________________

VCC

WDI tWD tRP

RESET

NORMAL MODE (WDS = GND)

VCC

Figure 4a. Watchdog Timing Diagram, WDS = GND

MAX6748

MAX6749

MAX6750

MAX6751

RESET IN

GND

VCC

VMON_TH

Figure 3. Adding an External Manual Reset Function to the

MAX6748–MAX6751

Watchdog Timer

MAX6746–MAX6751

The watchdog’s circuit monitors the µP’s activity. It the

µP does not toggle the watchdog input (WDI) within

tWD (user-selected), RESET asserts for the reset time-

out period. The internal watchdog timer is cleared by

any event that asserts RESET, by a falling transition at

WDI (which can detect pulses as short as 300ns) or by

a transition at WDS. The watchdog timer remains

cleared while reset is asserted; as soon as reset is

released, the timer starts counting.

The MAX6746–MAX6751 feature two modes of watch-

dog operation: normal mode and extended mode. In nor-

mal mode (Figure 4a), the watchdog timeout period is

determined by the value of the capacitor connected

between SWT and ground. In extended mode (Figure

4b), the watchdog timeout period is multiplied by 128.

For example, in extended mode, a 0.1µF capacitor gives

a watchdog timeout period of 65s (see the Extended-

Mode Watchdog Timeout Period vs. CSWT graph in the

Typical Operating Characteristics

). To disable the watch-

dog timer function, connect SWT to ground.

MAX6752/MAX6753

The MAX6752 and MAX6753 have a windowed watch-

dog timer that asserts RESET for the adjusted reset

timeout period when the watchdog recognizes a fast

watchdog fault (tWDI < tWD1), or a slow watchdog fault

(period > tWD2). The reset timeout period is adjusted

independently of the watchdog timeout period.

The slow watchdog period, tWD2 is calculated as follows:

tWD2 = 0.65 x 109 x CSWT

with tWD2 in seconds and CSWT in Farads.

The fast watchdog period, tWD1, is selectable as a ratio

from the slow watchdog fault period (tWD2). Select the

fast watchdog period by pinstrapping SET0 and SET1,

where HIGH is VCC and LOW is GND. Table 1 illus-

trates the SET0 and SET1 configuration for the 8, 16,

and 64 window ratio ( tWD2/tWD1).

For example, if CSWT is 1500pF, and SET0 and SET1 are

low, then tWD2 is 975ms (typ) and tWD1 is 122ms (typ).

RESET asserts if the watchdog input has two falling

edges too close to each other (faster than tWD1) (Figure

5a) or falling edges that are too far apart (slower than

tWD2) (Figure 5b). Normal watchdog operation is dis-

played in (Figure 5c). The internal watchdog timer is

cleared when a WDI falling edge is detected within the

valid watchdog window or when RESET is deasserted.

All WDI inputs are ignored while RESET is asserted.

The watchdog timer begins to count after RESET is

deasserted. The watchdog timer clears and begins to

count after a valid WDI falling logic input. WDI falling

transitions within periods shorter than tWD1 or longer

than tWD2 force RESET to assert low for the reset time-

out period. WDI falling transitions within the tWD1 and

tWD2 window do not assert RESET. WDI transitions

between tWD1(min) and tWD1(max) or tWD2(min) and

tWD2(max) are not guaranteed to assert or deassert the

RESET. To guarantee that the window watchdog does

not assert the RESET, strobe WDI between tWD1(max)

and tWD2(min). The watchdog timer is cleared when

RESET is asserted or after a falling transition on WDI or

after a state change on SET0 or SET1. Disable the

watchdog timer by connecting SET0 high and SET1 low.

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

_______________________________________________________________________________________ 9

tWD x 128 tRP

VCC

WDI

RESET

EXTENDED MODE (WDS = VCC)

VCC

Figure 4b. Watchdog Timing Diagram, WDS = VCC

SET0 SET1 RATIO

LOW LOW 8

LOW HIGH 16

HIGH LOW Watchdog Disabled

HIGH HIGH 64

Table 1. Min/Max Watchdog Setting

MAX6746–MAX6753

Applications Information

Selecting Reset/Watchdog

Timeout Capacitor

The reset timeout period is adjustable to accommodate

a variety of µP applications. Adjust the reset timeout

period (tRP) by connecting a capacitor (CSRT) between

SRT and ground. Calculate the reset timeout capacitor

as folllows:

CSRT = tRP / (5.06 x 106)

with tRP in seconds and CSRT in Farads.

The watchdog timeout period is adjustable to accom-

modate a variety of µP applications. With this feature,

the watchdog timeout can be optimized for software

execution. The programmer can determine how often

the watchdog timer should be serviced. Adjust the

watchdog timeout period (tWD) by connecting a specif-

ic value capacitor (CSWT) between SWT and GND. For

normal mode operation, calculate the watchdog time-

out capacitor as follows:

CSWT = tWD/(5.06 x 106)

with tRP in seconds and CSRT in Farads.

For the MAX6752 and MAX6753 windowed watchdog

function, calculate the slow watchdog period, tWD2 as

follows:

tWD2 = 0.65 x 109x CSWT

CSRT and CSWT must be a low-leakage (< 10nA) type

capacitor. Ceramic capacitors are recommended.

Transient Immunity

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, these supervi-

sors are relatively immune to short-duration supply tran-

sients (glitches). The Maximum Transient Duration vs.

Reset Threshold Overdrive graph in the

Typical

Operating Characteristics

shows this relationship.

The area below the curves of the graph is the region

in which these devices typically do not generate a reset

pulse. This graph was generated using a falling pulse

applied to VCC , starting above the actual reset threshold

(VTH) and ending below it by the magnitude indicated

(reset-threshold overdrive). As the magnitude of the tran-

sient increases (farther below the reset threshold), the

maximum allowable pulse width decreases. Typically, a

VCC transient that goes 100mV below the reset threshold

and lasts 50µs or less does not cause a reset pulse to be

issued.

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

10 ______________________________________________________________________________________

MAX6747

MAX6749

MAX6451

MAX6753

GND

RESET RESET

VCC

GND

3.3V

μP

100kΩ

Figure 6. Interfacing to Other Voltage Levels

WDI

(a) FAST FAULT

(b) SLOW FAULT

WDI

RESET

WDI

RESET

tWDI < tWD1 (MIN)

tWDI > tWD2 (MAX)

tWD1 (MAX) < tWDI < tWD2 (MIN)

Figure 5. MAX6752/MAX6753 Window Watchdog Diagram

Interfacing to Other Voltages for

Logic Compatibility

The open-drain RESET output can be used to interface

to a µP with other logic levels. As shown in Figure 6, the

open-drain output can be connected to voltages from 0

to 6V.

Generally, the pullup resistor connected to the RESET

connects to the supply voltage that is being monitored

at the IC’s VCC pin. However, some systems can use

the open-drain output to level-shift from the monitored

supply to reset circuitry powered by some other supply.

Keep in mind that as the supervisor’s VCC decreases

towards 1V, so does the IC’s ability to sink current at

RESET. Also, with any pullup resistor, RESET is pulled

high as VCC decays toward zero. The voltage where

this occurs depends on the pullup resistor value and

the voltage to which it is connected.

Ensuring a Valid

RESET

Down to VCC = 0V

(Push-Pull

RESET

)

When VCC falls below 1V, RESET current sinking capabil-

ities decline drastically. The high-impedance CMOS-

logic inputs connected to RESET can drift to undeter-

mined voltages. This presents no problems in most

applications, since most µPs and other circuitry do not

operate with VCC below 1V.

In those applications where RESET must be valid down

to 0V, add a pulldown resistor between RESET and

GND for the MAX6746/MAX6748/MAX6750/MAX6752

push/pull outputs. The resistor sinks any stray leakage

currents, holding RESET low (Figure 7). The value of the

pulldown resistor is not critical; 100kΩis large enough

not to load RESET and small enough to pull RESET to

ground. The external pulldown can not be used with

the open-drain reset outputs.

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

______________________________________________________________________________________ 11

MAX6746

MAX6748

MAX6450

MAX6752

GND

RESET

VCC

100kΩ

Figure 7. Ensuring RESET Valid to VCC = 0V

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

12 ______________________________________________________________________________________

PART TOP MARK

MAX6746KA16 AEDI

MAX6746KA23 AEDJ

MAX6746KA26 AEDK

MAX6746KA29 AALN

MAX6746KA46 AEDL

MAX6747KA16 AALO

MAX6747KA23 AEDM

MAX6747KA26 AEDN

MAX6747KA29 AEDO

MAX6747KA46 AEDP

MAX6748KA AALP

MAX6749KA AALQ

MAX6750KA16 AEDQ

MAX6750KA23 AALR

MAX6750KA26 AEDR

MAX6750KA29 AEDS

MAX6750KA46 AEDT

MAX6751KA16 AEDU

MAX6751KA23 AEDV

MAX6751KA26 AEDW

MAX6751KA29 AEDX

MAX6751KA46 AEDY

MAX6752KA16 AEDZ

MAX6752KA23 AEEA

MAX6752KA26 AALT

MAX6752KA29 AEEB

MAX6752KA46 AEEC

MAX6753KA16 AEED

MAX6753KA23 AEEE

MAX6753KA26 AEEF

MAX6753KA29 AEEG

MAX6753KA46 AEEH

SUFFIX MIN TYP MAX

50 4.900 5.000 5.100

49 4.802 4.900 4.998

48 4.704 4.800 4.896

47 4.606 4.700 4.794

46 4.533 4.625 4.718

45 4.410 4.500 4.590

44 4.288 4.375 4.463

43 4.214 4.300 4.386

42 4.116 4.200 4.284

41 4.018 4.100 4.182

40 3.920 4.000 4.080

39 3.822 3.900 3.978

38 3.724 3.800 3.876

37 3.626 3.700 3.774

36 3.528 3.600 3.672

35 3.430 3.500 3.570

34 3.332 3.400 3.468

33 3.234 3.300 3.366

32 3.136 3.200 3.264

31 3.014 3.075 3.137

30 2.940 3.000 3.060

29 2.867 2.925 2.984

28 2.744 2.800 2.856

27 2.646 2.700 2.754

26 2.573 2.625 2.678

25 2.450 2.500 2.550

24 2.352 2.400 2.448

23 2.267 2.313 2.359

22 2.144 2.188 2.232

21 2.058 2.100 2.142

20 1.960 2.000 2.040

19 1.862 1.900 1.938

18 1.764 1.800 1.836

17 1.632 1.665 1.698

16 1.544 1.575 1.607

Table 2. Reset Threshold Voltage Suffix

(TA= -40°C to +125°C)

Note: Standard versions are shown in bold. There is a 2500-

piece minimum order increment for standard versions.

Sample stock is typically held on standard versions only.

Nonstandard versions require a minimum order increment of

10,000 pieces. Contact factory for availability.

Table 3. Standard Version Table

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

______________________________________________________________________________________ 13

Selector Guide

PART

FIXED VCC

RESET

THRESHOLD

ADJUSTABLE

RESET

THRESHOLD

STANDARD

WATCHDOG

TIMER

MIN/MAX

WATCHDOG

TIMER

PUSH/ PULL

RESET

OPEN-DRAIN

RESET

MANUAL

RESET

INPUT

MAX6746 X — X — X — X

MAX6747 X — X — — X X

MAX6748 — X X — X — —

MAX6749 — X X — — X —

MAX6750 X X X — X — —

MAX6751 X X X — — X —

MAX6752 X — — X X — —

MAX6753 X — — X — X —

TOP VIEW

WDI

SET1GND

VCC

RESETSWT

SRT

SET0

MAX6752

MAX6753

SOT23-8

Pin Configurations (continued)

MAX6748

MAX6749

MAX6750

MAX6751

RESET IN

GND

SRT

VCC

SWT

CSRT

CSWT

VIN

WDI

WDS

I/O

WDS = 0 FOR NORMAL MODE

WDS = VCC FOR EXTENDED MODE

MAX6749

MAX4751

μP

RESET RESET

Typical Operating Circuit

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

8 SOT23 K8-5 21-0078 90-0176

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns,

go to www.maxim-ic.com/packages. Note that a “+”, “#”, or

“-” in the package code indicates RoHS status only. Package

drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

MAX6746–MAX6753

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 7/02 Initial release —

3 12/05 Added the lead-free notation.1

4 9/10 Added the automotive version of the MAX6746 and the MAX6753 and

revised the Typical Operating Characteristics.1, 4

5 12/10 Added the automotive version of the MAX6750. 1

6 4/11 Added the automotive version of the MAX6747. 1