SY58608U
3.2Gbps Precision, 1:2 LVDS Fanout Buf f er
with Internal Termination and Fai l Saf e Input
General Description
The SY58608U is a 2.5V, high-speed, fully differential
1:2 LVDS fanout buffer optimized to provide two
identical output copies with less than 20ps of skew and
130fsRMS typical additive phase jitter. The SY58608U
can process clock signals as fast as 2GHz or data
patterns up to 3.2G bps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVPP) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The outputs are 325mV LVDS, with rise/fall times
guaranteed to be les s t han 100ps.
The SY58608U operates from a 2.5V ±5% supply and is
guaranteed over the full industrial temperature range (–
40°C to +85°C). For applications that require CML or
LVPECL outputs, consider Micrel’s SY58606U and
SY58607U, 1:2 fanout buffers with 400mV and 800mV
output swings respectively. The SY58608U is part of
Micrel’s high-speed, Precision Edge® product line.
Data sheets and support documentation can be found
on Micrel’s web site at : www.micrel.com.
Functional Block Diagram
Features
• Precision 1:2, 325mV LVDS fanout buff er
• Guaranteed A C performance over temperature and
voltage:
– DC-to > 3.2Gbps t hroughput
– <300ps propagation delay (IN-to-Q)
– <20ps within-device skew
– <100ps rise/fall times
• Fail Safe Input
– Prevent s outputs from oscillating when input is
invalid
• Ultra-low jitter design
– 130fsRMS typical additive phase jitter
– High-speed LVDS output s
• 2.5V ±5% power suppl y operation
• Industrial temperat ure rang e: –40° C t o +85°C
• Available in 16-pin (3mm x 3mm) QFN package
Applications
• All SONET clock and data distribution
• Fibre Channel clock and data distribut i on
• Gigabit Ethernet clock and data distri bution
• Backplane distribution
Markets
• DataCom
• Telecom
• Storage
• ATE
• Test and Measurement
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
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SY58608U
Ordering Information(1)
Part Number Package
Type
Operating
Range
Package Marking Lead Finish
SY58608UMG QFN-16 Industrial 608U with Pb-Free bar-line indicator NiPdAu
Pb-Free
SY58608UMGTR(2) QFN-16 Industrial 608U with Pb-Free bar-line indicator NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
1, 4 IN, /IN
Differenti al Inputs: Thi s i nput pair is the differential sign al input to the device. Input
accepts DC-coupl ed different ial signals as small as 100mV (200mVPP). Each pin of this
pair internal ly terminates with 50Ω to the VT pin. If the input swing falls below a certain
threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output
by latching the outputs to its last valid stat e. See “Input Int er face Applications” sec tion for
more details.
2 VT Input Term ination Center-Tap: Each input terminates to t his pin. The VT pin provides a
center-tap for each input (IN, /IN) to a termination net work for maximum interface
flexibility. See “Input Interface Applications” s ection.
3 VREF-AC
Reference Voltage: This output bias to VCC–1.2V . It is used for A C-coupling inputs IN and
/IN. Connect VR E F-AC directly t o the VT pin. Bypass with 0.01µF l ow ESR capacit or to
VCC. Maximum sink/source cur r ent is ±1.5mA. See “Input Interface Applications” section
for more details.
5, 8,13, 16 VCC Positive Power Supply: B ypass with 0.1µF//0.01µF low ESR capacitors as c lose to the
VCC pins as pos s i ble.
6, 7, 14, 15 GND,
Exposed pad Ground. Expos ed pad must be connec ted to a ground plane that is the s ame potential as
the ground pin.
9, 10
11, 12 /Q1, Q1
/Q0, Q0
LVDS Differe ntial Output Pairs: Differential buffered output copy of the input signal. The
output swing is typically 325mV. Normally terminated 100Ω across the output pairs (Q
and /Q). See “LVD S Output Terminat ion” section.
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SY58608U
Absolute Maximum Ratin gs (3)
Supply Voltage (VCC) ............................... –0.5V to +4.0V
Input Voltage (V IN) ............................ –0.5V to VCC +0.3V
LVDS Output Current (I OUT) .................................. ±10mA
Input Current
Source or Sink Current on (IN, /IN) ............... ±50mA
Current (VREF)
Source or sink current on VREF-AC(6) ............... ±1.5mA
Maximum Operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (Ts) .................... –65°C to +150°C
Operating Ratings(4)
Supply Voltage (VIN) ...................... +2.375V to +2.635V
Ambient Temperature (TA) ................... –40°C to +85°C
Package Thermal R esistance(5)
QFN
Still-air (θJA) ........................................... 60°C/W
Junction-to-boar d (ψJB) ......................... 33°C/W
DC Electrical Characteristics(7)
TA = –40°C to +85° C, unl ess otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage Range 2.375 2.5 2.625 V
ICC Power Supply C urrent No load, max. VCC 55 75 mA
RDIFF_IN Differential Input Resistance
(IN-to-/IN) 90 100 110 Ω
VIH Input HIGH Vol tage
(IN, /IN) IN, /IN 1.2 VCC V
VIL Input LOW Voltage
(IN, /IN) IN, /IN 0 VIH–0.1 V
VIN Input Voltage Swing
(IN, /IN) see Figure 4, Note 8 0.1 1.7 V
VDIFF_IN Differential Input Voltage Swing
(|IN - /IN|) see Figure 6 0.2 V
VIN_FSI Input Voltage Threshold that
Triggers FSI 30 100 mV
VREF-AC Output Refere nce Voltage VCC–1.3 VCC–1.2 VCC–1.1 V
IN to VT Voltage from Input to VT 1.28 V
Notes:
3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
4. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
5. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
6. Due to the limited drive capability, use for input of the same package only.
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
8. VIN (max) is specified when VT is floating.
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SY58608U
LVDS Outputs DC Electrical Chara c teristics(9)
VCC = +2.5V ±5%, RL = 100Ω across the output pairs; TA = –40°C to +85°C, unless otherwi se stat ed.
Symbol Parameter Condition Min Typ Max Units
VOUT Output Voltage Swing See Figure 4, 5 250 325 mV
VDIFF_OUT Differential Output Vol tage
Swing See Figur e 6 500 650 mV
VOCM Output Common Mode Voltage See Figure 7 1.125 1.20 1.275 V
∆VOCM Change in Com mon Mode
Voltage See Figure 7 –50 50 mV
Notes:
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY58608U
AC Electrical Characteristics(10)
VCC = +2.5V ±5%, RL = 100Ω across the output pairs, Input tr/tf: ≤300ps; TA = –40°C to +85° C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Frequency NRZ Data 3.2 4.25 Gbps
VOUT > 200mV Clock 2 3 GHz
tPD Propagation Delay IN-to-Q VIN: 100mV-200mV 170 280 420 ps
VIN: 200mV-800mV 130 200 300 ps
tSkew Within Device Sk ew Note 11 5 20 ps
Part-to-Part Skew Note 12 135 ps
tJitter Additive Phase Jit ter Carrier = 622MHz
Integration Range: 12kHz – 20MHz 130 fsRMS
tr, tf Output Rise/Fall Time
(20% to 80%) A t full output swing. 35 60 100 ps
Duty Cycle Differential I/O 47 53 %
Notes:
10. These high-speed parameters are guaranteed by design and characterization.
11. Within-device skew is measured between two different outputs under identical input transitions.
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
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SY58608U
Functional Description
Fail-Safe Input (FSI)
The input includes a special fail-safe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or
when the amplitude of the input signal drops
sufficiently below 100mVPK (200mVPP), typically
30mVPK. Maximum frequency of SY58608U is limited
by the FSI function.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing such that the differential voltage
across the input pair is less than 100mV, the FSI
function will eliminate a metastable condition and latch
the outputs to the last valid state. No ringing and no
indeterminate state will occur at the output under
these conditions. The output recovers to normal
operation once the input signal returns to a valid state
with a differential voltage ≥100mV.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. Refer to “Typical
Characteristics” for detailed information.
Timing Diagrams
Figure 1. Propagation Delay
Figure 2. Fail Safe Feature
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SY58608U
Input Interface Applica ti on s
Figure 8. CML Interface
(DC-Coupled)
Figure 9. CML Interface
(AC-Coupled)
Figure 10. LVPECL Interface
(DC-Coupled)
Figure 11. LVPECL Interface
(AC-Coupled)
Figure 12. LVDS Interface
(DC-Coupled)
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SY58608U
Package Information
16-Pin (3mm x 3mm) QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micr el .com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by
Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or
systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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