W9812G6KH
2M 4 BANKS 16 BITS SDRAM
Publication Release Date: Sep. 19, 2016
Revision: A05
- 1 -
Table of Contents-
1. GENERAL DESCRIPTION .............................................................................................................. 3
2. FEATURES ...................................................................................................................................... 3
3. ORDER INFORMATION .................................................................................................................. 3
4. PIN CONFIGURATION .................................................................................................................... 4
5. PIN DESCRIPTION ......................................................................................................................... 5
6. BLOCK DIAGRAM ........................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1 Power Up and Initialization ................................................................................................. 7
7.2 Programming Mode Register .............................................................................................. 7
7.3 Bank Activate Command .................................................................................................... 7
7.4 Read and Write Access Modes .......................................................................................... 7
7.5 Burst Read Command ........................................................................................................ 8
7.6 Burst Write Command ......................................................................................................... 8
7.7 Read Interrupted by a Read................................................................................................ 8
7.8 Read Interrupted by a Write ................................................................................................ 8
7.9 Write Interrupted by a Write ................................................................................................ 8
7.10 Write Interrupted by a Read ................................................................................................ 8
7.11 Burst Stop Command .......................................................................................................... 8
7.12 Addressing Sequence of Sequential Mode......................................................................... 9
7.13 Addressing Sequence of Interleave Mode .......................................................................... 9
7.14 Auto-precharge Command................................................................................................ 10
7.15 Precharge Command ........................................................................................................ 10
7.16 Self Refresh Command ..................................................................................................... 10
7.17 Power Down Mode ............................................................................................................ 11
7.18 No Operation Command ................................................................................................... 11
7.19 Deselect Command .......................................................................................................... 11
7.20 Clock Suspend Mode ........................................................................................................ 11
8. OPERATION MODE ...................................................................................................................... 12
9. ELECTRICAL CHARACTERISTICS ............................................................................................. 13
9.1 Absolute Maximum Ratings .............................................................................................. 13
9.2 Recommended DC Operating Conditions ........................................................................ 13
9.3 Capacitance ...................................................................................................................... 14
9.4 DC Characteristics ............................................................................................................ 14
9.5 AC Characteristics and Operating Condition .................................................................... 15
10. TIMING WAVEFORMS .................................................................................................................. 17
10.1 Command Input Timing ..................................................................................................... 17
10.2 Read Timing ...................................................................................................................... 18
10.3 Control Timing of Input/Output Data ................................................................................. 19
10.4 Mode Register Set Cycle .................................................................................................. 20
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 2 -
11. OPERATING TIMING EXAMPLE .................................................................................................. 21
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) .......................................... 21
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............... 22
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .......................................... 23
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............... 24
11.5 Interleaved Bank Write (Burst Length = 8) ....................................................................... 25
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................... 27
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ............................................ 29
11.10 Auto Precharge Write (Burst Length = 4) ......................................................................... 30
11.11 Auto Refresh Cycle ........................................................................................................... 31
11.12 Self Refresh Cycle ............................................................................................................ 32
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ................................. 33
11.14 Power Down Mode ............................................................................................................ 34
11.15 Auto-precharge Timing (Read Cycle) ............................................................................... 35
11.16 Auto-precharge Timing (Write Cycle) ............................................................................... 36
11.17 Timing Chart of Read to Write Cycle ................................................................................ 37
11.18 Timing Chart of Write to Read Cycle ................................................................................ 37
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38
11.20 Timing Chart of Burst Stop Cycle (Precharge Command) ................................................ 38
11.21 CKE/DQM Input Timing (Write Cycle) .............................................................................. 39
11.22 CKE/DQM Input Timing (Read Cycle) .............................................................................. 40
12. PACKAGE SPECIFICATION ......................................................................................................... 41
13. REVISION HISTORY ..................................................................................................................... 42
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 3 -
1. GENERAL DESCRIPTION
W9812G6KH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words 4 banks 16 bits. W9812G6KH delivers a data bandwidth of up to 200M words per
second. To fully comply with the personal computer industrial standard, W9812G6KH is sorted into the
following speed grades: -5, -5I, -5J, -6, -6I, -6J and -75.
The -5/-5I grade parts are compliant to the 200MHz/CL3 specification (The -5I industrial grade which
is guaranteed to support -40°C ≤ TA ≤ 85°C, the -5J industrial plus grade which is guaranteed to
support -40°C ≤ TA ≤ 105°C).
The -6/-6I grade parts are compliant to the 166MHz/CL3 specification (The -6I industrial grade which
is guaranteed to support -40°C ≤ TA ≤ 85°C, the -6J industrial plus grade which is guaranteed to
support -40°C ≤ TA ≤ 105°C).
The -75 grade parts is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9812G6KH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V ± 0.3V Power Supply
Up to 200 MHz Clock Frequency
2,097,152 Words 4 banks 16 bits organization
Self Refresh Mode
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and full page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Power Down Mode
Auto-precharge and Controlled Precharge
4K Refresh Cycles/64 mS, @ -40°C ≤ TA ≤ 85°C
4K Refresh Cycles/16 mS, @ -40°C ≤ TA ≤ 105°C
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant
Note: Not support self refresh function with TA > 85°C
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
SELF REFRESH
CURRENT (MAX)
OPERATING
TEMPERATURE
W9812G6KH-5
200MHz/CL3
2mA
0°C ~ 70°C
W9812G6KH-5I
200MHz/CL3
2mA
-40°C ~ 85°C
W9812G6KH-5J
200MHz/CL3
5mA
-40°C ~ 105°C
W9812G6KH-6
166MHz/CL3
2mA
0°C ~ 70°C
W9812G6KH-6I
166MHz/CL3
2mA
-40°C ~ 85°C
W9812G6KH-6J
166MHz/CL3
5mA
-40°C ~ 105°C
W9812G6KH-75
133MHz/CL3
2mA
0°C ~ 70°C
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 4 -
4. PIN CONFIGURATION
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQM
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VDDQ
VDDQ
VSSQ
VSSQ
VDD
VDD
VSS
VSSQ
VSSQ
VDDQ
VSS
VSS
WE
VDD
VDDQ
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 5 -
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
DESCRIPTION
2326, 22,
2935
A0A11
Multiplexed pins for row and column address.
Row address: A0A11. Column address: A0A8
20, 21
BS0, BS1
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
DQ0DQ15
Multiplexed pins for data output and input.
19
CS
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
18
RAS
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the
operation to be executed.
17
CAS
Referred to
RAS
16
WE
Referred to
RAS
39, 15
LDQM,
UDQM
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
System clock used to sample inputs on the rising edge
of clock.
37
CKE
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
1, 14, 27
VDD
Power for input buffers and logic circuit inside DRAM.
28, 41, 54
VSS
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
VDDQ
Separated power from VDD, used for output buffers to
improve noise.
6, 12, 46, 52
VSSQ
Separated ground from VSS, used for output buffers to
improve noise.
36, 40
NC
No connection.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 6 -
6. BLOCK DIAGRAM
DQ0
DQ15
UDQM
LDQM
CLK
CKE
CS
RAS
CAS
WE
A10
A0
A9
A11
BS0
BS1
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
Note: The cell array configuration is 4096 * 512 * 16.
DMn
R
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W
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C
O
D
E
R
R
O
W
D
E
C
O
D
E
R
R
O
W
D
E
C
O
D
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R
R
O
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W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 7 -
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD +0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
7.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
RAS
,
CAS
,
CS
and
WE
at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC
has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to
RAS
activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max).
7.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS
high and
CAS
low at the clock rising edge after minimum of tRCD delay.
WE
pin voltage level
defines whether the access cycle is a read operation (
WE
high), or a write operation (
WE
low). The
address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and precharge operations between multiple banks, seamless data access operation among
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 8 -
7.5 Burst Read Command
The Burst Read command is initiated by applying logic low level to
CS
and
CAS
while holding
RAS
and
WE
high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
7.6 Burst Write Command
The Burst Write command is initiated by applying logic low level to
CS
,
CAS
and
WE
while
holding
RAS
high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
7.7 Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command is satisfied.
7.8 Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9 Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having
RAS
and
CAS
high with
CS
and
WE
low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency
in a burst read cycle interrupted by Burst Stop.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 9 -
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2
A8 A7 A6 A5 A4 A3 A2
A1
A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2
A1
A0
Data 4
A8 A7 A6 A5 A4 A3
A2
A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 6
A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 7
A8 A7 A6 A5 A4 A3
A2
A1
A0
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 10 -
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with Auto-precharge cannot be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or writes cycle with Auto-precharge. Once the precharge operation has started, the bank
cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is
issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the
precharge operation two clock delays from the last burst write cycle. This delay is referred to as Write
tWR. The bank undergoing Auto-precharge cannot be reactivated until tWR and tRP are satisfied. This is
referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge
Command, the interval between the Bank Activate Command and the beginning of the internal
precharge operation must satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when
CS
,
RAS
and
WE
are low and
CAS
is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having
CS
,
RAS
,
CAS
and CKE held low with
WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after
tXSR from the end of Self Refresh Command.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 11 -
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device cannot remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when
CS
is low with
RAS
,
CAS
, and
WE
held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when
CS
is brought high, the
RAS
,
CAS
, and
WE
signals become don’t
cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 12 -
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
DEVICE
STATE
CKEn-1
CKEn
DQM
BS0, 1
A10
A0A9
A11
CS
RAS
CAS
WE
Bank Active
Idle
H
x
x
v
v
v
L
L
H
H
Bank Precharge
Any
H
x
x
v
L
x
L
L
H
L
Precharge All
Any
H
x
x
x
H
x
L
L
H
L
Write
Active (3)
H
x
x
v
L
v
L
H
L
L
Write with Auto-precharge
Active (3)
H
x
x
v
H
v
L
H
L
L
Read
Active (3)
H
x
x
v
L
v
L
H
L
H
Read with Auto-precharge
Active (3)
H
x
x
v
H
v
L
H
L
H
Mode Register Set
Idle
H
x
x
v
v
v
L
L
L
L
No – Operation
Any
H
x
x
x
x
x
L
H
H
H
Burst Stop
Active (4)
H
x
x
x
x
x
L
H
H
L
Device Deselect
Any
H
x
x
x
x
x
H
x
x
x
Auto - Refresh
Idle
H
H
x
x
x
x
L
L
L
H
Self - Refresh Entry
Idle
H
L
x
x
x
x
L
L
L
H
Self Refresh Exit
idle
(S.R.)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
X
Clock suspend Mode Entry
Active
H
L
x
x
x
x
x
x
x
x
Power Down Mode Entry
Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
X
Clock Suspend Mode Exit
Active
L
H
x
x
x
x
x
x
x
x
Power Down Mode Exit
Any
(power down)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Data write/Output Enable
Active
H
x
L
x
x
x
x
x
x
x
Data Write/Output Disable
Active
H
x
H
x
x
x
x
x
x
x
Notes:
(1) v = valid x = Don’t care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode cannot be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 13 -
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Voltage on any pin relative to VSS
VIN, VOUT
-1 ~ VDD + 0.5 (≤ 4.6V max.)
V
1
Voltage on VDD/VDDQ supply relative to VSS
VDD, VDDQ
-1 ~ 4.6
V
1
Operating Temperature for -5/-6/-75
TOPR
0 ~ 70
°C
1
Operating Temperature for -5I/-6I
TOPR
-40 ~ 85
°C
1
Operating Temperature for -5J/-6J
TOPR
-40 ~ 105
°C
1
Storage Temperature
TSTG
-55 ~ 150
°C
1
Soldering Temperature (10s)
TSOLDER
260
°C
1
Power Dissipation
PD
1
W
1
Short Circuit Output Current
IOUT
50
mA
1
Note:
1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device
9.2 Recommended DC Operating Conditions
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Power Supply Voltage
VDD
3.0
3.3
3.6
V
I/O Buffer Supply Voltage
VDDQ
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
-
VDD + 0.3
V
1
Input Low Voltage
VIL
-0.3
-
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH= -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL= 2mA
Input leakage current
II(L)
-5
-
5
µA
3
Output leakage current
IO(L)
-5
-
5
µA
4
Notes:
1. VIH (max.) = VDD/VDDQ+1.5V for pulse width ≤ 5 nS.
2. VIL (min.) = VSS/VSSQ-1.5V for pulse width ≤ 5 nS.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Output disabled, 0V ≤ VOUT ≤ VDDQ.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 14 -
9.3 Capacitance
(VDD = 3.3V ± 0.3V, f = 1 MHz, TA = 25°C)
PARAMETER
SYM.
MIN.
MAX.
UNIT
Input Capacitance
(A0 to A11, BS0, BS1,
CS
,
RAS
,
CAS
,
WE
, LDQM, UDQM, CKE)
CI
-
3.8
pf
Input Capacitance (CLK)
CCLK
-
3.5
pf
Input/Output capacitance (DQ0DQ15)
CIO
-
6.5
pf
Note: These parameters are periodically sampled and not 100% tested.
9.4 DC Characteristics
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -5/-6/-75, TA= -40 to 85°C for -5I/-6I, TA= -40 to 105°C for -5J/-6J)
PARAMETER
SYM.
MAX.
UNIT
NOTES
-5/-5I
-5J
-6/-6I
-6J
-75
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst operation
IDD1
55
55
50
50
45
mA
3
Standby Current
tCK = min.,
CS
= VIH
VIH/L = VIH (min.)/VIL (max.)
IDD2
25
25
20
20
20
3
Bank: Inactive state
CKE = VIL
(Power Down Mode)
IDD2P
2
5
2
5
2
3
Standby Current
CLK = VIL,
CS
= VIH
VIH/L=VIH (min.)/VIL (max.)
IDD2S
12
12
12
12
12
Bank: Inactive state
CKE = VIL
(Power Down Mode)
IDD2PS
2
5
2
5
2
No Operating Current
tCK = min.,
CS
= VIH(min)
IDD3
40
40
35
35
30
Bank: Active state (4 Banks)
CKE = VIL
(Power Down Mode)
IDD3P
12
12
12
12
12
Burst Operating Current
tCK = min.
Read/ Write command cycling
IDD4
80
80
75
75
70
3, 4
Auto Refresh Current
tCK = min.
Auto refresh command cycling
IDD5
70
70
65
65
60
3
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
IDD6
2
5
2
5
2
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 15 -
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -5/-6/-75, TA= -40 to 85°C for -5I/-6I, TA= -40 to 105°C for -5J/-6J)
PARAMETER
SYM.
-5/-5I/-5J
-6/-6I/-6J
-75
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Ref/Active to Ref/Active Command
Period
tRC
55
60
65
Active to precharge Command Period
tRAS
40
100000
42
100000
45
100000
nS
Active to Read/Write Command Delay
Time
tRCD
15
15
20
Read/Write(a) to Read/Write(b)
Command Period
tCCD
1
1
1
tCK
Precharge to Active Command Period
tRP
15
15
20
nS
Active(a) to Active(b) Command Period
tRRD
2
2
2
tCK
Write Recovery Time
CL* = 2
tWR
2
2
2
tCK
CL* = 3
2
2
2
CLK Cycle Time
CL* = 2
tCK
10
1000
7.5
1000
10
1000
CL* = 3
5
1000
6
1000
7.5
1000
CLK High Level width
tCH
2
2
2.5
8
CLK Low Level width
tCL
2
2
2.5
8
Access Time from CLK
CL* = 2
tAC
6
6
6
9
CL* = 3
4.5
5
5.4
Output Data Hold Time
tOH
3
3
3
9
Output Data High
Impedance Time
CL* = 2
tHZ
6
6
6
7
CL* = 3
4.5
5
5.4
Output Data Low Impedance Time
tLZ
0
0
0
9
Power Down Mode Entry Time
tSB
0
5
0
6
0
7.5
nS
Transition Time of CLK (Rise and Fall)
tT
1
1
1
Data-in Set-up Time
tDS
1.5
1.5
1.5
8
Data-in Hold Time
tDH
0.8
0.8
0.8
8
Address Set-up Time
tAS
1.5
1.5
1.5
8
Address Hold Time
tAH
0.8
0.8
0.8
8
CKE Set-up Time
tCKS
1.5
1.5
1.5
8
CKE Hold Time
tCKH
0.8
0.8
0.8
8
Command Set-up Time
tCMS
1.5
1.5
1.5
8
Command Hold Time
tCMH
0.8
0.8
0.8
8
Refresh Time
(4K Refresh Cycles)
0°C ≤ TA ≤ 70°C
tREF
64
64
64
mS
-40°C ≤ TA ≤ 85°C*
64
64
mS
-40°C ≤ TA ≤ 105°C*
16
16
mS
Mode register Set Cycle Time
tRSC
2
2
2
tCK
Exit self refresh to ACTIVE command
tXSR
70
72
75
nS
* CL = CAS Latency
* -40°C ≤ TA ≤ 85°C is for -5I, -5J, -6I and -6J grade parts only. -40°C ≤ TA ≤ 105°C is for -5J and -6J grade parts only.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 16 -
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the “Functional Description” section.
6. AC test load diagram.
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohmsoutput 30pF
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 17 -
10. TIMING WAVEFORMS
10.1 Command Input Timing
CLK
A0-A11
BS0,1
VIH
VIL
tCMH tCMS
tCHtCL
tTtT
tCKS tCKH
tCKH
tCKStCKS tCKH
CS
RAS
CAS
WE
CKE
tCMS tCMH
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS tAH
tCK
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 18 -
10.2 Read Timing
Read CAS Latency
tAC
tLZ tAC
tOH tHZ
tOH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A11
BS0,1
DQ Valid
Data-Out Valid
Data-Out
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 19 -
10.3 Control Timing of Input/Output Data
tCMH tCMS tCMH tCMS
tDS tDH tDS tDH tDS tDH tDS tDH
Valid
Data-Out Valid
Data-Out Valid
Data-Out
Valid
Data-in Valid
Data-in Valid
Data-in Valid
Data-in
tCKH tCKS tCKH tCKS
tDS tDH tDS tDH tDH
tDS tDS tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
tCMH tCMS tCMH tCMS
tOHtAC tOHtAC tOHtHZ
OPEN
tLZ tAC tOH tAC
tCKH tCKS tCKH tCKS
tOH tAC tOH tAC tOH tAC tOH tAC
Valid
Data-Out Valid
Data-Out
Valid
Data-Out
CLK
DQM
DQ0~15
(Word Mask)
(Clock Mask)
CLK
CKE
DQ0~15
CLK
Control Timing of Input Data
Control Timing of Output Data
(Output Enable)
(Clock Mask)
DQM
DQ0~15
CKE
CLK
DQ0~15
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 20 -
10.4 Mode Register Set Cycle
A0
A3 Addressing Mode
0Sequential
1Interleave
A0A9 Single Write Mode
0Burst read and Burst write
1Burst read and single write
A0A2 A1 A0
A00 0 0
A0
0 0 1
A00 1 0
A00 1 1
A01 0 0
A0
1 0 1
A0
1 1 0
A01 1 1
Burst Length
Sequential Interleave
1 1
2 2
4 4
8 8
Reserved Reserved
Full Page
CAS Latency
Reserved
Reserved
2
3
Reserved
A0A6 A5 A4
A00 0 0
A0
0 1 0
A00 1 1
A01 0 0
A00 0 1
* "Reserved" should stay "0" during MRS cycle.
tRSC
tCMS tCMH
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS tAH
CLK
CS
RAS
CAS
WE
A0-A11
BS0,1 Register
set data
next
command
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
A0
A7
A9 A0
Write Mode
A10
BS0
A0
A11
"0"
"0"
"0"
"0"
"0" Reserved
BS1 "0"
Reserved
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 21 -
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
WE
CS tRC tRC
tRC tRC
tRAS tRP tRAS tRP
tRPtRAS tRAS
tRCD tRCD tRCD tRCD
tAC tAC tAC tAC
tRRD tRRD tRRD tRRD
Active Read
Active Read
Active
Active
Active
Read
Read
Precharge
Precharge
Precharge
RAa RBb RAc RBd RAe
RAa CAw RBb CBx RAc CAy RBd CBz RAe
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3
RAS
CAS
BS1
BS0
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 22 -
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
01234567891011 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
tRC tRC
tRC
tRAS tRP tRAS tRP
tRAS tRP
tRCD tRCD tRCD
tAC tAC tAC tAC
tRRD tRRD tRRD tRRD
Active Read
Active Read
Active
Active
Active
Read
Read
tRC
RAa RAc RBd RAe
DQ aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0
* AP is the internal precharge start timing
AP* AP*
RAa CAw RBb CBx RAc CAy RBd RAe
CBz
RBb
AP*
tRCD
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 23 -
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRP tRAS
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
Active Read
Precharge Active Read
Precharge Active
tAC tAC
Read
Precharge
tAC
BS0
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 24 -
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
A0-A9,
A11
0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRAS
tRCD tRCD tRCD
tRRD tRRD
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0
RAa
RAa
CAx
RBb
RBb CBy
RAc
RAc CAz
* AP is the internal precharge start timing
Active Read
Active
Active Read
tAC tAC
tAC
CLK
DQ
CKE
DQM
A10
WE
CAS
RAS
CS
Read
AP*
AP*
BS1
BS0
tRAS
tRP
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 25 -
11.5 Interleaved Bank Write (Burst Length = 8)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRAS
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 by4 by5 by6 by7 CZ0 CZ1 CZ2
Write
Precharge
Active
Active Write
Precharge
Active Write
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
Idle
Bank #0
Bank #1
Bank #2
Bank #3
BS0
ax4 ax5 ax6 ax7 by0 by1 by2 by3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 26 -
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRAS
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAb
RAc
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
CAz
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
Active Write Write
Active
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
Active Write AP*
BS0
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 27 -
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tCCD tCCD tCCD
tRAS
tRAS
tRCD tRCD
tRRD
RAa
RAa CAI
RBb
RBb CBx CAy CAm CBz
a0 a1 a2 a3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
Active Read
Active Read
Read Read
Read
Precharge
tAC
tAC
tAC
tAC
tAC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
BS0
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 28 -
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
01 2 3 456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRAS
tRCD
tWR
RAa
RAa CAx CAy
ax0 ax1 ax2 ax3 ax4 ax5 ay1
ay0 ay2 ay4
ay3
Q Q Q Q Q Q D DD
D
D
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
Active Read Write Precharge
tAC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
BS0
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 29 -
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
01 2 3 456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
WE
CAS
RAS
CS
BS1
tRC
tRAS tRP tRAS
tRCD tRCD
tAC tAC
Active Read AP* Active Read AP*
RAa RAb
RAa CAw RAb CAx
aw0 aw1 aw2 aw3
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
BS0
bx0 bx2
bx1 bx3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 30 -
11.10 Auto Precharge Write (Burst Length = 4)
01 2 3 456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
WE
CAS
RAS
CS
BS1
tRC tRC
tRP tRAS tRP
RAa
tRCD tRCD
RAb RAc
RAa RAb CAx RAc
bx0 bx1 bx2 bx3
Active
Active Write AP* Active Write AP*
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
tRAS
BS0
CAw
aw0 aw1 aw2 aw3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 31 -
11.11 Auto Refresh Cycle
01 2 3 456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23
All Banks
Prechage Auto
Refresh Auto Refresh (Arbitrary Cycle)
tRCtRP tRC
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
WE
CAS
RAS
CS
BS0,1
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 32 -
11.12 Self Refresh Cycle
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0,1
WE
CAS
RAS
CS
tCKS
tSB tCKS
All Banks
Precharge Self Refresh
Entry Arbitrary Cycle
tRP
Self Refresh Cycle tXSR
No Operation / Command Inhibit
Self Refresh
Exit
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 33 -
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BS1
BS0
A10
A0-A9,
A11
DQM
CKE
DQ
tRCD
RBa
RBa CBv CBw CBx CBy CBz
av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3
Q Q Q Q D DD Q Q Q Q
tAC tAC
Read ReadSingle WriteActive
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 34 -
11.14 Power Down Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
RAa CAa RAa CAx
RAa RAa
ax0 ax1 ax2 ax3
tSB
tCKS tCKS tCKS
tSB
tCKS
Active Standby
Power Down mode Precharge Standby
Power Down mode
Active NOP Precharge NOP Active
Note: The Power Down Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS
WE
CAS
RAS
CS
Read
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 35 -
11.15 Auto-precharge Timing (Read Cycle)
Read AP
01110987654321
Q0
Q0
Read AP Act
Q1
Read AP Act
Q1 Q2
AP ActRead
Act
Q0
Q3
(1) CAS Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note )
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0
Read AP Act
Q0
Read AP Act
Q1
Q0
Read AP Act
Q1 Q2 Q3
Read AP Act
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
(2) CAS Latency=3
t
RP
t
RP
t
RP
t
RP
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 36 -
11.16 Auto-precharge Timing (Write Cycle)
Act
0 1 32
(1) CAS Latency = 2
(a) burst length = 1
DQ
4 5 76 8 9 1110
Write
D0
ActAP
Command
(b) burst length = 2
DQ
Write
D0
ActAP
Command
tRP
tRP
D1
(c) burst length = 4
DQ
Write
D0
ActAP
Command tRP
D1
(d) burst length = 8
DQ
Write
D0
ActAP
Command tRP
D1
D2 D3
D2 D3 D4 D5 D6 D7
(2) CAS Latency = 3
(a) burst length = 1
DQ
Write
D0
ActAP
Command
(b) burst length = 2
DQ
Write
D0
ActAP
Command
tRP
tRP
D1
(c) burst length = 4
DQ
Write
D0
ActAP
Command tRP
D1
(d) burst length = 8
DQ
Write
D0
AP
Command tRP
D1
D2 D3
D2 D3 D4 D5 D6 D7
tWR
tWR
tWR
tWR
tWR
tWR
tWR
tWR
12
Act
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
Write
AP
ActAct
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
Note )
CLK
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 37 -
11.17 Timing Chart of Read to Write Cycle
11.18 Timing Chart of Write to Read Cycle
Note: The Output data must be masked by DQM to avoid I/O conflict
1110987654321
0
(1) CAS Latency=2
In the case o f Burst Length = 4
Read
Read
Write
Write
DQ
DQ
( b ) Command
DQM
DQM
D0 D1 D2 D3
D0 D1 D2 D3
( a ) Command
(2) CAS Latency=3
Read Write
Read Write
D0 D1 D2 D3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
D0 D1 D2 D3
ReadWrite
01110987654321
Q0
Read
Q1 Q2 Q3
Read
Read
Write
Write
Q0 Q1 Q2 Q3
Write
Q0 Q1 Q2 Q3
D0 D1
DQ
DQ
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
( a ) Command
( b ) Command
DQM
DQM
In the case of Burst Length=4
(1) CAS Latency=2
(2) CAS Latency=3
D0
D0 D1
Q0 Q1 Q2 Q3D0
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 38 -
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0 1 111098765432
(1) Read cycle
(a) CAS latency =2
Command
Q0 Q1 Q2 Q3 Q4
PRCGRead
(b) CAS latency =3
Command
Q0 Q1 Q2 Q3 Q4
PRCGRead
DQ
DQ
(2) Write cycle
Command
Q0 Q1 Q2 Q3 Q4
PRCG
Write
DQ
DQM
tWR
Read BST
01110987654321
DQ Q0 Q1 Q2 Q3
BST
( a ) CAS latency =2
Command
( b )CAS latency = 3
(1) Read cycle
Q4
(2) Write cycle
Command
Read
Command
Q0 Q1 Q2 Q3 Q4
Q0 Q1 Q2 Q3 Q4
DQ
DQ
Write BST
Note: represents the Burst stop commandBST
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 39 -
11.21 CKE/DQM Input Timing (Write Cycle)
7
6
5432
1
CKE MASK
( 1 )
D1 D6D5D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5432
1
( 2 )
D1 D6
D5
D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
76
5432
1
( 3 )
D1 D6D5D4
D3D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK CKE MASK
CKE MASK
Internal
CLK
CLK
CLK
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 40 -
11.22 CKE/DQM Input Timing (Read Cycle)
7
6
5432
1
( 1 )
Q1 Q6
Q4Q3Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ Open Open
7
6
5432
1
Q1 Q6Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ Open
( 2 )
765432
1
Q1 Q6
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ Q5
Q4
( 3 )
Q4
CLK
CLK
CLK
Q3
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 41 -
12. PACKAGE SPECIFICATION
Package Outline TSOP (TYPE II) 54L 400 MIL (1:3)
Controlling Dimension : Millimeters
R1
0.002
0.012
MAX.MIN. NOM.
A2
b
A
A1
0.30 1.00
0.05
0.45
1.20
0.15
SYMBOL
DIMENSION
(MM)
MAX.
MIN. NOM.
e0.80 BASIC 0.016L 0.40 0.50 0.60 0.020 0.024
0.455E 11.56 11.76 11.96 0.463 0.471
0.870
D22.22
22.09 22.35 0.875 0.880
0.039 0.018
0.047
0.006
DIMENSION
(INCH)
L1 0.80 BASIC
c
0.395
10.1610.03 10.29 0.400 0.405
E1
R 0.25 0.010
SEATING PLANE
D
A2
A1
A
ZD
Y
E1
e b
1 27
54 28
L
RAD. R1
L1
E
0.95 1.05
---
--- ---
---
---
--- ---
---
---
---
---
0.12 0.21
---
0.037 0.041
---
0.005 0.008
---
θ1
Cθ
RAD. R
DETAIL “A”
DETAIL “A”
Y0.004
ZD 0.71 REF
θ
θ10.10
---
---
------
0.12
0.12 ---
0°
10°---
15°20°
8°10°15°20°
---
0°8°
0.031 BASIC
0.031 BASIC
0.028 REF
0.005
0.005 ---
W9812G6KH
Publication Release Date: Sep. 19, 2016
Revision: A05
- 42 -
13. REVISION HISTORY
VERSION
PAGE
DESCRIPTION
A01
All
Initial formally datasheet
A02
3, 4, 13~15
Removed -6A and -6K automotive grades
A03
3, 13~15
Added -5I industrial grade parts
A04
13
Update section 9.1 Absolute Maximum Ratings
Voltage on any pin relative to VSS (VIN, VOUT) and
Voltage on VDD/VDDQ supply relative to VSS (VDD,
VDDQ) minimum voltage from -0.5V to -1V
A05
3, 13~15
Added -5J and -6J industrial plus grade parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.