DS3884A-MIL - National Semiconductor

TL/F/11976

DS3884A BTL Handshake Transceiver MIL-STD-883

PRELIMINARY

April 1994

DS3884A

BTL Handshake Transceiver MIL-STD-883

General DescriptionÐ(MIL Only)

The DS3884A is pin to pin and functionally compatible with

the DS3884. The DS3884A is a speed and power enhanced

version of the DS3884. There are two minor differences be-

tween the DS3884 and DS3884A.

The external resistor used in the DS3884A is different from

that used in the DS3884. REXT for the DS3884 is 6.2k while

REXT for the DS3884A is 15 kX. The available filter settings

for the DS3884A are 5 ns, 10 ns, 14 ns, 20 ns, while the

settings for the DS3884 are 5 ns, 7.5 ns, 15 ns, and 25 ns.

Features

YFast propagation delay

Y6-bit BTL transceiver

YSelective receiver glitch filtering (FR1–FR3)

YMeets 1194.1 Standard on Backplane Transceiver Log-

ic (BTL)

YSupports live insertion

YGlitch free power-up/down protection

YTypically less than 5 pF bus-port capacitance

YLow Bus-port voltage swing (typically 1V) at 80 mA

YTTL compatible driver and control inputs

YSeparate TTL I/O

YOpen collector bus-port outputs allow Wired-OR

connection

YControlled rise and fall time to reduce noise coupling to

adjacent lines

YBuilt in Bandgap reference with separate QVCC and

QGND pins for precise receiver thresholds

YIndividual Bus-port ground pins

YProduct offered in glass sealed CERPAK

Connection Diagram

TL/F/11976–1

Order Number DS3884AW/883

See NS Package Number WA48A

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A. http://www.national.com

Logic Diagram

TL/F/11976– 2

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General Description (Continued)

The DS3884A is one in a series of transceivers designed

specifically for the implementation of high performance Fu-

turebusaand proprietary bus interfaces. The DS3884A is a

BTL 6-bit Handshake Transceiver designed to conform to

IEEE 1194.1 (Backplane Transceiver LogicÐBTL). Utiliza-

tion of the DS3884A simplifies the implementation of all

handshake signals which require Wired-OR glitch filtering.

Three of the six bits have an additional parallel Wired-OR

filtered receive output giving a total of nine receiver outputs.

In Wired-OR applications, the glitch generated as drivers

are released from the bus, is dependent upon the back-

plane and parasitic wiring components causing the charac-

teristics of the glitch to vary in pulse width and amplitude. To

accommodate this variation the DS3884A features two pins

defined as PS1 and PS2 which allow selection of a 5 ns,

10 ns, 14 ns and 24 ns filter setting to optimize glitch filter-

ing for a given situation. The REXT pin is issued in conjunc-

tion with the filtering circuitry and requires a 15 kXresistor

to ground. For additional information on Wired-OR glitch,

reference Application Note AN-774.

The DS3884A driver output configuration is an NPN open

collector which allows Wired-OR connection on the bus.

Each driver output incorporates a Schottky diode in series

with its collector to isolate the transistor output capacitance

from the bus thus reducing the bus loading in the inactive

state. The combined output capacitance of the driver and

receiver input is typically less than 5 pF. The driver also has

high sink current capability to comply with the bus loading

requirements defined within IEEE 1194.1 BTL specification.

Backplane Transceiver Logic (BTL) is a signaling standard

that was invented and first introduced by National Semicon-

ductor, then developed by the IEEE to enhance the per-

formance of backplane buses. BTL compatible transceivers

feature low output capacitance drivers to minimize bus load-

ing, a 1V nominal signal swing for reduced power consump-

tion and receivers with precision thresholds for maximum

noise immunity. The BTL standard eliminates settling time

delays that severely limit TTL bus performance, and thus

provide significantly higher bus transfer rates. The back-

plane bus is intended to be operated with termination resis-

tors (selected to match the bus impedance) connected to

2.1V at both ends. The low voltage is typically 1V.

Separate ground pins are provided for each BTL output to

minimize induced ground noise during simultaneous switch-

ing.

The device’s unique driver circuitry meets a maximum slew

rate of 0.5V/ns which allows controlled rise and fall times to

reduce noise coupling to adjacent lines.

The transceiver’s high impedance control and driver inputs

are fully TTL compatible.

The receiver is a high speed comparator that utilizes a

bandgap reference for precision threshold control allowing

maximum noise immunity to the BTL 1V signaling level.

Separate QVCC and QGND pins are provided to minimize

the effects of high current switching noise. Output pins

FR1–FR3 are the filtered outputs and R1–R6 are the unfil-

tered outputs. All receiver outputs are fully TTL compatible.

The DS3884A supports live insertion as defined for Future-

busathrough the LI (Live Insertion) pin. To implement live

insertion the LI pin should be connected to the live insertion

power connector. If this function is not supported the LI pin

must be tied to the VCC pin. The DS3884A also provides

power up/down glitch free protection during power se-

quencing.

The DS3884A has two types of power connections in addi-

tion to the LI pin. They are the Logic VCC (VCC) and the

Quiet VCC (QVCC). There are two VCC pins on the DS3884A

that provide the supply voltage for the logic and control cir-

cuitry. Multiple connections are provided to reduce the ef-

fects of package inductance and thereby minimize switching

noise. As these pins are common to the VCC bus internal to

the device, a voltage difference should never exist between

these pins and the voltage difference between VCC and

QVCC should never exceed g0.5V because of ESD circuit-

ry. Additionally, the ESD circuitry between the VCC pins and

all other pins except for BTL I/O’s and LI pins requires that

any voltage on these pins should not exceed the voltage on

VCC a0.5V.

There are three different types of ground pins on the

DS3884A. They are the logic ground (GND), BTL grounds

(B1GND–B6GND) and the Bandgap reference ground

(QGND). All of these ground reference pins are isolated

within the chip to minimize the effects of high current switch-

ing transients. For optimum performance the QGND should

be returned to the connector through a quiet channel that

does not carry transient switching current. The GND and

B1GND–B6GND should be connected to the nearest back-

plane ground pin with the shortest possible path.

Since many different grounding schemes could be imple-

mented and ESD circuitry exist on the DS3884A, it is impor-

tant to note that any voltage difference between ground

pins, QGND, GND or B1GND–B6GND should not exceed

g5V including power up/down sequencing.

Additional transceivers included in the military Futurebusa

family are; the DS3885 BTL Arbitration Transceiver with ar-

bitration competition logic for the ABk7:0l/ABP signal

lines, and the DS3886A BTL 9-bit Latching Data Transceiv-

er featuring edge triggered latches in the driver which may

be bypassed during a fall-through mode and a transparent

latch in the receiver.

The DS3875 Arbitration Controller included in the Future-

busafamily supports all the required and optional modes

for Futurebusaarbitration protocol. It is designed to be

used in conjunction with the DS3884A and DS3885 trans-

ceivers.

The Logical Interface FuturebusaEngine (LIFE) is a high

performance FuturebusaProtocol Controller designed for

IEEE 896.1-1991. The LIFE will handle all handshaking sig-

nals between the Futurebusaand the local bus interface.

The Protocol Controller supports the Futurebusacom-

pelled mode data transfer as both master and slave. The

Protocol Controller can be configured to operate in compli-

ance to IEEE 896.2 Profile B mode. The LIFE is 896.5 com-

patible. The LIFE incorporates a DMA controller and 64-bit

FIFO’s for fast queuing.

All of the transceivers are offered in 48-pin Cerpak high

density package styles.

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Typical Application

TL/F/11976– 3

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Absolute Maximum Ratings (Note 1)

The 883 specifications are written to reflect the Reliabil-

ity Electrical Test Specifications (RETS) established by

National Semiconductor for this product. For a copy of

the latest RETS please contact your local National

Semiconductor sales office or distributor.

Supply Voltage 6.5V

Control Input Voltage 6.5V

Driver Input and Receiver Output 5.5V

Receiver Input Current g15 mA

Bus Termination Voltage 2.4V

Power Dissipation at 125§C 0.58W

Storage Temperature Range b65§Ctoa

150§C

Lead Temperature (Soldering, 4 seconds) 260§C

Recommended Operating

Conditions

Supply Voltage, VCC 4.5V–5.5V

Bus Termination Voltage (VT) 2.06V–2.14V

Operating Free Air Temperature b55§Ctoa

125§C

DC Electrical Characteristics (Notes 2 and 3) TAeb

55§Ctoa

125§C, VCC e5V g10%

Symbol Parameter Conditions Min Typ Max Units

DRIVER AND CONTROL INPUT: (Dn, DE*, PS1 and PS2)

VIH Minimum Input High Voltage 2.0 V

VIL Maximum Input Low Voltage 0.8 V

IIInput Leakage Current VIN eVCC e5.5V 100 mA

IIH Input High Current VIN e2.4V 40 mA

IIL Input Low Current VIN e0.5V b100 mA

VCL Input Diode Clamp Voltage ICLAMP eb

12 mA b1.2 V

DRIVER OUTPUT/RECEIVER INPUT: (Bn)

VOLB Output Low Bus Voltage Dn e2.4V, DE*e0V, 0.75 1.0 1.1 V

(Note 5) IOL e80 mA

IOLBZ Output Low Bus Current Dn e0.5V, DE*e2.4V, Bn e0.75V 100 mA

IOHBZ Output High Bus Current Dn e0.5V, DE*e2.4V, Bn e2.1V 100 mA

IOLB Output Low Bus Current Dn e0.5V, DE*e0V, Bn e0.75V 220 mA

IOHB Output High Bus Current Dn e0.5V, DE*e0V, Bn e2.1V 350 mA

VTH Receiver Input Threshold DE*e2.4V 1.47 1.55 1.62 V

VCLP Positive Clamp Voltage VCC eMax or 0V, IBn e1 mA 2.4 3.4 4.5 V

VCC eMax or 0V, IBn e10 mA 2.9 3.9 5.0 V

VCLN Negative Clamp Voltage ICLAMP eb

12 mA b1.2 V

RECEIVER OUTPUT: (FRn and Rn)

VOH Voltage Output High Bn e1.1V, DE*e2.4V, IOH eb

2 mA 2.4 3.2 V

VOL Voltage Output Low Bn e2.1V, DE*e2.4V, IOL e24 mA 0.35 0.5 V

Bn e2.1V, DE*e2.4V, IOL e8 mA 0.35 0.4 V

IOS Output Short Circuit Current Bn e1.1V, DE*e2.4V (Note 4) b40 b70 b100 mA

SUPPLY CURRENT

ICC Supply Current: Includes VCC,DE*

0.5V, All Dn e2.4V 50 90 mA

QVCC and LI DE*e2.4V, All Bn e2.1V 50 80 mA

ILI Live Insertion Current DE*e2.4V, All Dn e0.5V 1 3 mA

DE*e0.5V, All Dn e2.4V 2 5 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should

be operated at these limits. The table of ‘‘Electrical Characteristics’’ provide conditions for actual device operation.

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DC Electrical Characteristics (Notes 2 and 3) TAeb

55§Ctoa

125§C, VCC e5V g10% (Continued)

Note 2: All input and/or output pins shall not exceed VCC plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power-

down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC. There is a diode

between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used when

pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power

sequencing requirements with respect to VCC and QVCC. Furthermore, the difference between VCC and QVCC should never be greater than 0.5V at any time

including power-up.

Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise

specified. All typical values are specified under these conditions.: VCC e5V and TAe25§C unless otherwise stated.

Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second.

Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package.

AC Electrical Characteristics TAeb

55§Ctoa

125§C, VCC e5V g10% (Note 6)

Symbol Parameter Conditions Min Typ Max Units

DRIVER

tPHL Dn to Bn Prop. Delay DE*e0V 1 7 ns

tPLH

(Figures 1

16ns

PHL DE*to Bn Enable Time Dn e3V 2 4 9 ns

tPLH Disable Time

(Figures 1

24 7 ns

rTransition TimeÐRise/Fall

(Figures 1

1 2 3.5 ns

tf20% to 80% 1 2 4.5 ns

SR Skew Rate is Calculated (Note 11) 0.5 V/ns

from 1.3V to 1.8V

tskew Skew between Drivers in (Note 7) 15ns

the Same Package

RECEIVER

tPHL Bn to Rn Prop. Delay DE*e3V 2 6 ns

tPLH

(Figures 4

26ns

skew Skew between Receivers in (Note 7) 3ns

Same Package

FILTERED RECEIVER

tPHL Bn to FRn Prop. Delay PS1 e0V PS2 e0V DE*e3V 61317 ns

(Figures 4

EXT e15 kX

PS1 e0V PS2 e3V DE*e3V 11 16 23 ns

(Figures 4

EXT e15 kX

PS1 e3V PS2 e0V DE*e3V 16 21 29 ns

(Figures 4

EXT e15 kX

PS1 e3V PS2 e3V DE*e3V 22 33 49 ns

(Figures 4

EXT e15 kX

tPLH Bn to FRn Prop. Delay DE*e3V

(Figures 4

(Note 8) 28ns

EXT e15 kX

tGR Glitch Rejection PS1 e0V PS2 e0V DE*e3V 516ns

(Figures 4

EXT e15 kX

PS1 e0V PS2 e3V DE*e3V 10 21 ns

(Figures 4

EXT e15 kX

PS1 e3V PS2 e0V DE*e3V 14 27 ns

(Figures 4

EXT e15 kX

PS1 e3V PS2 e3V DE*e3V 20 47 ns

(Figures 4

EXT e15 kX

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AC Electrical Characteristics TAeb

55§Ctoa

125§C, VCC e5V g10% (Note 6) (Continued)

Symbol Parameter Conditions Min Typ Max Units

FILTERED RECEIVER TIMING REQUIREMENTS

tsPSn to Bn Set-Up Time (

Figure 7

), REXT e15 kX250 ns

PARAMETERS NOT TESTED

Coutput Capacitance at Bn (Note 9) 5 pF

tNR Noise Rejection (Note 10) 1 ns

Note 6: Input waveforms shall have a rise/fall time of 3 ns.

Note 7: tskew is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions.

Note 8: Filtered receiver tPLH is independent of filter setting.

Note 9: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide.

Note 10: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width.

Note 11: Futurebusatransceivers are required to limit bus signal rise and fall times to no faster than 0.5V/ns, measured between 1.3V and 1.8V (approximately

20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Xtied to a2.1V DC.

Pin Descriptions

Pin Name Number of Input/ Description

Pins Output

B1–B6 6 I/O BTL receiver input and driver output

B1GND–B6GND 6 NA Driver output ground reduces bounce due to

high current switching of driver outputs

(Note 12)

DE*1 I Driver Enable Low

D1–D6 6 I TTL Driver Input

FR1–FR3 3 O TTL Filtered Receiver Output

GND 3 NA Ground reference for switching circuits.

(Note 12)

LI 1 NA Power supply for live insertion. Boards that

require live insertion should connect LI to the

live insertion pin on the connector. (Note 13)

NC 8 NA No Connect

PS1, PS2 2 I Pulse Width Selection pin determines glitch filter

setting (Note 14)

R1–R6 6 O TTL Receiver Output

REXT 1 NA External Resistor pin. External resistor is used

for internal biasing of filter circuitry. The 15 kX

resistor shall be connected between REXT and

GND. The resistor shall have a tolerance of 1%

and a temperature coefficient of 100 ppm/§Cor

better.

QGND 2 NA Ground reference for receiver input bandgap

reference and non-switching circuits (Note 12)

QVCC 1NAV

CC supply for bandgap reference and non-

switching circuits (Note 13)

VCC 2NAV

CC supply for switching circuits (Note 13)

Note 12: the multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground

path. The various ground pins can be tied together provided that the external ground has low inductance (i.e., ground plane with power pins and many signal pins

connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from

moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage

offset between their grounds will degrade the noise margin.

Note 13: The same considerations for ground are used for VCC in reducing lead inductance (see Note 12). QVCC and VCC should be tied together externally. If live

insertion is not supported, the LI pin can be tied together with QVCC and VCC.

Note 14: See AC characteristics for filter setting.

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Truth Table

DE*Dn FRn Rn Bn

HXHHL

HXL LH

LHHHL

LLLLH

Note 1: X: High or low logic state

Note 2: L: Low state

Note 3: H: High state

Note 4: L-H: Low to high transition

Glitch Filter Table

PS1 PS2 Filter Setting

LL 5ns

L H 10 ns

H L 14 ns

H H 20 ns

TL/F/11976– 4

TL/F/11976– 5

FIGURE 1. Driver Propagation Delay Set-Up FIGURE 2. Driver: Dn to Bn

TL/F/11976– 6

TL/F/11976– 7

FIGURE 3. Driver: DE*to Bn

Switch Position

tPLH tPHL

S1 open close

FIGURE 4. Receiver Propagation Delay Set-Up

TL/F/11976– 8

FIGURE 5. Receiver: Bn to FRn, Bn to Rn

TL/F/11976– 9

FIGURE 6. Receiver: tGR, FRn(min) e2V

TL/F/11976– 10

FIGURE 7. Receiver: PSn to Bn

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DS3884A BTL Handshake Transceiver MIL-STD-883

Physical Dimensions inches (millimeters)

48-Pin CERPAK

Order Number DS3884AW

NS Package Number WA48A

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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