©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
HUF76132P3 , HUF76132S3S
75A, 30V, 0.011 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
inn o v at ive Ul tr aF ET ™ pr oces s. T his
advanced pr ocess tech nology
achie ves the lo west pos sible on-resi stance per sil icon area,
resultin g in outstanding performanc e. This dev ice is capable
of wit hstanding hi gh energ y in the avalanche mode and the
diode e xhibits v ery lo w revers e recovery time and stored
charge. It w as designed for use in applica ti ons where po wer
efficiency is important, such as switching regulators,
switching converters , motor drivers , relay drivers, low-
voltage bus s w itches, and power management in portab le
and battery-operated products.
Formerly deve lopmental type TA76132.
Features
• Logic Level Gate Driv e
• 75A, 30V
• Ultra Low On- Resistance, rDS(ON) = 0.011Ω
• Tem peratur e Com pensating PSPI CE® Model
• Tem peratur e Com pensating SABER© Model
• Thermal Impedanc e SPICE Model
• Thermal Impedanc e SABER Model
• Peak Current vs Pulse Widt h Curve
• UIS Rating Curve
• Related Literature
- TB334, “G uidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76132P3 TO-220AB 76132P
HUF76132S3S TO-263AB 76132S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76132S3ST.
D
G
S
JEDEC TO-220AB JEDEC TO-263AB
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data S heet Janu ary 2003
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specif ied UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 30 V
Drain to G ate Vo lt ag e (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 30 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Drain C urr e nt
Continuo us (TC = 2 5oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuo us (TC = 1 00 oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Continuo us (TC = 1 00 oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
75
44
41
Figu re 4
A
A
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 17, 1 8
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Der ate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
0.97 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T STG -40 to 150 oC
Maximu m Tempe rature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUT ION: St ress es above those list ed in “Abs olute Maximum Rati ngs” may cause per mane nt damage to the device. This is a str ess only rating and operati on of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Speci fications TA = 25oC, Unless Otherwise Specified
PARAM ETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Dr ain t o Sou rce Breakdown Voltag e BVDSS ID = 25 0µA, VGS = 0V (Fig ure 1 2) 30 - - V
Z ero Gat e V ol tag e D rain C urr e nt IDSS VDS = 25V, VGS = 0V - - 1 µA
VDS = 25V, VGS = 0V, TC = 150oC--250µA
Ga te t o Sour c e Le ak ag e C urr e nt IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain t o Source On Resistance rDS(ON) ID = 75A , VGS = 10V (Fig ure 9, 10) - 0.0085 0.011 Ω
ID = 44A, VGS = 5V (Figure 9) - 0.013 0.016 Ω
ID = 41A, VGS = 4.5V (Figure 9) - 0.015 0.018 Ω
THERMAL SPECIFICATIONS
T her m al Res ista nc e Ju ncti on to Case R θJC (Figur e 3) - - 1.03 oC/W
Thermal Resistance Junction to Ambient RθJA TO-2 20, T O- 26 2 an d TO - 26 3 - - 6 2 oC/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn -On Time tON VDD = 15V, ID ≅ 41A ,
RL = 0.366Ω, VGS = 4.5V,
RGS = 6.2Ω
(Figures 15, 21, 22)
--185ns
Turn-O n Delay Time td(ON) -17-ns
Rise Time tr-105- ns
Turn-O ff Delay Time td(OFF) -33-ns
Fa ll Time tf-42-ns
Turn -Off Time tOFF --113ns
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
SWITCHING SPECIFICATIONS (VG S = 10V)
Turn -On Time tON VDD = 15V, ID ≅ 75A ,
RL = 0.20, VGS = 10V,
RGS = 6.8Ω
(Figures 16, 21, 22)
--72ns
Turn-O n Delay Time td(ON) -11-ns
Rise Time tr-37-ns
Turn-O ff Delay Time td(OFF) -65-ns
Fa ll Time tf-42 -ns
Turn -Off Time tOFF --160ns
GATE CHARGE SPECIFICATIONS
T otal G ate Charg e Qg(TOT) VGS = 0V to 10 V VDD = 15V, ID ≅ 44A,
RL = 0.341Ω
Ig(REF) = 1.0mA
(Figur es 1 4, 19, 20)
-4452nC
Gat e Charg e at 5V Qg(5) VGS = 0V to 5V - 25 3 0 nC
T hresh old G ate Ch ar g e Qg(TH) VGS = 0V to 1V - 1. 8 2.2 nC
Ga te to Sourc e Gate Charg e Qgs -4.80- nC
Ga te t o Drai n “M iller” C ha rge Qgd -13.50- nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 1 3)
- 1650 - pF
Output Capacitance COSS -850-pF
Reverse Transfer Capacitance CRSS -200-pF
Electrical Speci fications TA = 25oC, Unless Otherwise Specified (C on tinue d)
PARAM ETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specific ations
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Volta ge VSD ISD = 44 A - - 1 .25 V
Reverse Recovery Time trr ISD = 44A, dISD/dt = 100A/µs--71ns
Reverse Recovered Charge QRR ISD = 44 A, dISD/dt = 100A/µs - - 104 nC
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPER ATURE
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTI PLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
20
025 50 75 100 125 150
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
80
40
60
VGS = 10V
VGS = 4.5V
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fai rchi ld Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
Typical Performance Curves Unless Otherwise Specified (Continued)
t, RECTANGULAR PULSE DURATION (s)
10-5 10-1 100
2
0.1
1
10-2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
0.01 10-4 10-3
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
101
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
TC = 25oC
I = I25 150 - TC
125
FOR TEMPERAT URES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 1 0V
IDM, PEAK CURRENT (A)
2000
5010-5 10-4 10-3 10-2 10-1 100101
t, PULSE WIDTH (s)
100
V
GS
= 5V
1000
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGIO N
1001VDS, DRAIN TO SOURCE VOLTAGE (V)
1
100
1000
10
ID, DRAIN CURRENT (A)
10
10ms
TJ = MAX RATED
TC = 25oC
1ms
100µs
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
BVDSS MAX = 30V
110
100
0.01
500
10
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0.1
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GA TE THRESHOLD V OLTAGE vs
JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN T O S OURCE BREAKDOW N
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
0 23451
0
20
60
100
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
150oC
-40oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
120
80 25oC
40
VGS = 4.5V VGS = 4V
01234
0
20
40
80
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VO LTAGE (V)
VGS = 5V
VGS = 10V
VGS = 3V
120
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VO LTAGE (V)
VGS = 3.5V
100
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
10
12
14
18
64
VGS, GATE TO SOURCE VOLTAGE (V)
26108
ID = 75A
ID = 25A
rDS(ON), DRAIN T O SOURCE
ON RESISTANCE (mΩ)
8
16
ID = 51A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.4
-60 0 60 120 180
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
1.2
1.6 PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 75A
-60 0 60 120 180
0.6
0.8
1.2
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
1.2
1.1
1.0
0.9-60 0 60 120 180
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fai rchi ld Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
COSS
2500
1500
005 15 25
C, CAPACITANCE (pF)
2000
VDS, DRAIN TO SOURCE VOLTAGE (V)
1000
30
500
CISS
CRSS
10 20
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
10
8
6
4
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 15V
2
30 500Qg, GATE CHARGE (nC)
10
ID = 75A
ID = 51A
ID = 25A
WAVEFORMS IN
DESCENDING ORDER:
20 40
100
20 30 40 500
400
300
200
010
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 41A, RL= 0.312Ω
td(OFF)
td(ON)
tr
tf
20 30 40 500
400
200
100
010
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 1 0V, VDD = 15V, ID = 75A, RL= 0.20Ω
300
tr
tf
td(OFF)
td(ON)
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWI TCHING TIME TEST CIRCUIT FIGURE 22. SWITCHIN G TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
VDS
VGS
Ig(REF)
0
0
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
PSPICE Electric al Model
SUBCKT HUF76132 2 1 3 ; REV Ma y 1998
C A 12 8 2. 35e -9
CB 15 14 2.35e -9
CIN 6 8 1.45e-9
D BODY 7 5 DBODYM O D
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 33.34
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH RES 6 21 19 8 1
EVTEM P 20 6 18 22 1
IT 8 1 7 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.42e- 9
LSOU RCE 3 7 4.16e-9
MMED 16 6 8 8 M M EDMOD
MSTR O 16 6 8 8 M S T ROM O D
MWEAK 16 21 8 8 M WE AKMO D
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.5e-4
R G A T E 9 20 2.61
RL DRAIN 2 5 10
RLGATE 1 9 54 .2
RLSOURCE 3 7 41.6
RSLC1 5 51 R SL CM OD 1e-6
RSLC2 5 50 1e 3
R SOUR CE 8 7 RS OURC E M O D 6.5-3
RVT HRE S 2 2 8 RVTHRESM OD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1A M OD
S1B 13 12 13 8 S1BMO D
S2A 6 15 14 13 S2AMO D
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*450),3))}
.MO DE L DB ODYM OD D (IS = 1.7 9e-12 IKF = 20 RS = 5.32e-3 TR S 1 = 7e-4 TRS 2 = 1. 21e-6 CJO = 2.65e -9 T T = 3.24e- 8 M = 4.2e-1 XTI =6)
.MO DE L DB REAK M OD D (RS = 8.25e-2 TRS 1 = 9. 12e-4 TRS2 = 8.14e- 7)
.MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 6.1e-1)
.MODE L M M E DM OD NMOS (V T O = 1.86 KP = 4 IS = 1e- 30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.61)
.MO DEL M STROMOD NMOS (VTO = 2. 2 K P = 120 IS = 1e-3 0 N = 10 T OX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.63 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.1 RS=1e-1)
.MO DE L RB REAK M OD RES (TC1 = 9.97e-4 TC2 = 1.24e-7)
.MODEL RDRAINMOD RES (TC1 = 7.2e-2 TC2 = 1e-4)
.MO DE L RS LCMO D RES (TC1 = 1.07e-3 TC2 = 1.2 5e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-11 TC2 = 1e-11)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -9.2e-6)
.MO DE L RVTE M P M O D RES (TC1 = -1. 08e-3 TC2 = 9.73e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.00 VOFF= -1.00)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.00 VOFF= -6.00)
.MO DE L S 2A M OD VSWI T CH (RO N = 1e-5 ROFF = 0. 1 VO N = 0. 00 V OF F= 1. 65)
.MO DE L S 2B M OD VSWI T CH (RO N = 1e-5 ROFF = 0. 1 VO N = 1. 65 V OF F= 0. 00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperat ure O ptions; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
SABER Electrical Model
nom tem p=25 deg c 30v LL Ultrafet
REV Ma y 1998
templ ate hu f76132 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbody m od = (i s=1. 79e-12,cjo=2.6 5e-9, tt=3.24 e-8, m=4.2e -1, xti= 6)
d..model dbreakmod = ()
d..model dplcap m od = (cjo=1. 3e-9, i s=1e- 30, n=10, m =6.1e- 1)
m..model mmedmod = (type=_n,vto=1.86,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.2,kp=120,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.63,kp=1e-1,is=1e-30, tox=1)
sw_v cs p..mo del s1amod = (ron=1e- 5, roff= 0. 1,von=-6. 00,voff =-1. 00)
sw_v cs p..mo del s1bmod = (ron=1e- 5, roff= 0. 1,von=-1. 00,voff =-6. 00)
sw_v cs p..mo del s2amod = (ron=1e- 5,roff=0.1,vo n=0,vof f=1. 65)
sw_v cs p..mo del s2bmod = (ron=1e- 5,roff=0.1,vo n=1.6 5,voff= 0)
c.ca n12 n8 = 2.35e-9
c.c b n15 n14 = 2.35e-9
c.cin n6 n8 = 1.45 e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = m odel=dbreak m od
d.dplcap n10 n5 = m odel= dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 5.42e-9
l.lg ate n1 n9 = 1.00e-9
l.lsource n3 n7 = 4.16e -9
m.mmed n16 n6 n8 n8 = model=m m edmod, l=1u, w=1u
m.ms t rong n16 n6 n8 n8 = model=m strongmod, l=1u, w=1u
m.mw eak n16 n21 n8 n8 = model =m wea km od, l=1u , w = 1u
res. rbreak n17 n18 = 1, tc1=9. 97e-4, tc2= 1. 24e-7
res. rdbody n71 n5 =5.32e -3, tc1=7.0 e-4, tc2=1.21e-6
res. rdbreak n7 2 n5 =8. 2 5e-2, tc1 =9.12e -4, tc2=8. 14e-7
res. rdrain n50 n16 = 3.5e-4, tc1=7. 2e-2, tc2= 1e-4
res.rgate n9 n20 = 2.61
res. rl drain n2 n5 = 10
res. rl gate n1 n9 = 54.2
res. rl sour ce n3 n7 = 41. 6
res. rslc1 n5 n51 = 1e- 6, tc1=1. 07e-3,tc 2=-1.2 5e-6
res. rslc2 n5 n50 = 1e 3
res.rsource n8 n7 = 6.5e-3, tc1=1e-11,tc2=1e-11
res.rvtemp n18 n19 = 1, tc1=-1.08e-3,tc2=9.73e-7
res. rvth res n22 n8 = 1, tc1=-2e- 3,tc2=-9. 2e-6
spe. ebreak n11 n7 n17 n18 = 33.34
spe. eds n14 n8 n5 n8 = 1
spe. egs n13 n8 n6 n8 = 1
spe. esg n6 n10 n6 n8 = 1
spe. evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_v cs p.s1a n6 n12 n13 n8 = model =s 1am od
sw_v cs p.s1 b n13 n12 n1 3 n8 = m odel =s1bmod
sw_v cs p.s2 a n6 n15 n14 n13 = m odel =s2amod
sw_v cs p.s2 b n13 n15 n1 4 n13 = mod el =s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl : v (n51, n50) = ((v (n5, n51)/ (1e-9+abs (v(n5 ,n51) )))*((abs (v(n5 ,n51) *1e6/ 450))** 3))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76132P3, HUF76132S3S
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1
SPICE Thermal Model
REV May 19 98
HUF76132
CTHERM1 th 6 5.00e-3
CTHERM2 6 5 1.18e-2
CTHERM3 5 4 15.5e-2
CTHERM4 4 3 1.85e-2
CTHERM5 3 2 2.00e-2
CTHERM6 2 tl 2.5e-2
RTHERM1 th 6 1.51e-2
RTHERM2 6 5 1.51e-2
RTHERM3 5 4 3.03e-2
RTHERM4 4 3 6.05e-2
RTHERM5 3 2 1.81e-1
RTHERM6 2 tl 2.45e-1
SABER Thermal Mod el
SABER thermal model HUF76132
template thermal_model th tl
thermal_c th, tl
{
c therm.ctherm1 th 6 = 6.50e-3
ctherm.ctherm2 6 5 = 1.18e-2
ctherm.ctherm3 5 4 = 1.55e-2
ctherm.ctherm4 4 3 = 1.85e-2
ctherm.ctherm5 3 2 = 2.00e-2
ctherm.ctherm6 2 tl = 2.50e-2
rtherm.rtherm1 th 6 = 1 .51e-2
rtherm.rtherm2 6 5 = 1.51e- 2
rtherm.rtherm3 5 4 = 3.03e- 2
rtherm.rtherm4 4 3 = 6.05e- 2
rtherm.rtherm5 3 2 = 1.81e- 1
rtherm.rtherm6 2 tl = 2.45e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF76132P3, HUF76132S3S
Rev. I2
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