DC-DC
Converter
PWM Controller
Current Mode
IEEE 802.3af Interface
UVLO
Signature Detection
Classification
VOUT
Feedback
+
_
AUX
AC
Adapter
Jack Auxiliary
Power
Enable
PoE (+)
PoE (-)
Hot Swap
In-rush and Fault
Current Limiting
LM5071
LM5071
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LM5071 Power Over Ethernet PD Controller with Auxiliary Power Interface
Check for Samples: LM5071
1FEATURES PACKAGES
2• Compatible with 12V AC Adapters • TSSOP-16
• Fully Compliant 802.3af Power Interface Port DESCRIPTION
• 80V, 1Ω, 400 mA Internal MOSFET The LM5071 power interface port and pulse width
• Detection Resistor Disconnect Function modulation (PWM) controller provides a complete
• Programmable Classification Current integrated solution for Powered Devices (PD) that
connect into Power over Ethernet (PoE) systems.
• Programmable Under-voltage Lockout with The LM5071 is specifically designed for the PD
Programmable Hysteresis that must accept power from auxiliary sources
• Thermal Shutdown Protection such as AC adapters. The auxiliary power interface
• Auxiliary Power Enable Pin of the LM5071 activates the PWM controller when the
ac adapter is connected to power the PD when PoE
• Current Mode Pulse Width Modulator network power is unavailable. The LM5071 integrates
• Supports both Isolated and Non-Isolated an 80V, 400mA line connection switch and
Applications associated control for a fully IEEE 802.3af compliant
• Error Amplifier and Reference for Non-Isolated interface with a full featured current mode pulse width
Applications modulator dc-dc converter. All power sequencing
requirements between the controller interface and
• Programmable Oscillator Frequency switch mode power supply (SMPS) are integrated into
• Programmable Soft-Start the IC.
• 80% Maximum Duty Cycle Limiter, Slope
Compensation (-80 device)
• 50% Maximum Duty Cycle Limiter, No Slope
Compensation (-50 device)
Block Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
RSIG
RCLASS
AUX
UVLO
UVLORTN
VEE
RTN
VIN
RT
CS
COMP
FB
VCC
OUT
SS
ARTN
14
13
12
11
10
8 9
15
16
1
2
3
4
5
7
6
VEE
LM5071
RT
SS
VEE
OUT
VIN VCC
CS
RTN
ARTN
RCLASS
VIN
RSIG
SMPS
Controller
Internal
High Voltage
Regulator
Current Limit
Bandgap
Regulator
VIN < 10V
Switch 5V
FB
+
-
UVLO
UVLORTN
AUX
+3.3V
COMP
Inrush /DC
LM5071
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Figure 1. Simplified Block Diagram
Connection Diagram
Figure 2. 16 Lead TSSOP
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PIN DESCRIPTIONS
Pin Name Description Application Information
1 VIN System high potential input. The diode “OR” of several lines entering the PD, it is the more positive
input potential.
2 RSIG Signature resistor pin. Connect a resistor from VIN to this pin for signature detection. The
resistor is in parallel with the UVLO resistors and should be valued
accordingly.
3 RCLASS Classification resistor pin. Connect the classification programming resistor from this pin to VEE.
4 AUX Auxiliary input power startup pin. A resistor divider between the AUX voltage input to VEE programs the
startup levels with a 2.5V threshold. A high value (>300kΩ) internal pull
down resistor is present to pull the pin low if it is left open. In practice,
the divider voltage should be set well above 2.5V by the programming
resistors.
5 UVLO Line under-voltage lockout. An external resistor divider from VIN to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis is
set by a switched internal 10uA current source that forces additional
current into the resistor divider.
6 UVLORTN Return for the external UVLO resistors. Connect the bottom resistor of the resistor divider between the UVLO pin
and this pin.
7 VEE System low potential input. Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is the
more negative input potential.
8 RTN System return for the PWM converter. The drain of the internal current limiting power MOSFET which connects
VEE to the return path of the dc-dc converter.
9 OUT Output of the PWM controller. DC-DC converter gate driver output with 800mA peak sink current
capability.
10 VCC Output of the internal high voltage series When the auxiliary transformer winding (if used) raises the voltage on
pass regulator. Regulated output voltage this pin above the regulation set point, the internal series pass regulator
is nominally 7.8V. will shutdown, reducing the controller power dissipation.
11 FB Feedback signal. Inverting input of the internal error amplifier. The non-inverting input is
internally connected to a 1.25V reference.
12 COMP The output of the error amplifier and input COMP pull-up is provided by an internal 5K resistor which may be used
to the Pulse Width Modulator. to bias an opto-coupler transistor.
13 CS Current sense input. Current sense input for current mode control and over-current protection.
Current limiting is accomplished using a dedicated current sense
comparator. If the CS pin voltage exceeds 0.5V the OUT pin switches
low for cycle-by-cycle current limiting. CS is held low for 50ns after OUT
switches high to blank leading edge current spikes.
14 RT / SYNC Oscillator timing resistor pin and An external resistor connected from RT to ARTN sets the oscillator
synchronization input. frequency. This pin will also accept narrow ac-coupled synchronization
pulses from an external clock.
15 SS Soft-start input. An external capacitor and an internal 10uA current source set the soft-
start ramp rate.
16 ARTN Analog PWM supply return. RTN for sensitive analog circuitry including the SMPS current limit
amplifier.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
VIN ,RTN to VEE -0.3V to 80V
RSIG to VIN -12V to 0V
AUX to VEE -0.3V to 57V
UVLO to VEE -0.3V to 13V
RCLASS to VEE -0.3V to 7V
ARTN to RTN -0.3V to 0.3V
VCC, OUT to ARTN -0.3V to 16V
All other inputs to ARTN -0.3V to 7V
ESD Rating Human Body Model 2000V
Lead Temperature(3) Wave (4 seconds) 260°C
Infrared (10 seconds) 240°C
Vapor Phase (75 seconds) 219°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics. The absolute
maximum rating of VIN, RTN to VEE is derated to (-0.3V to 76V) at -40°C.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For detailed information on soldering the plastic TSSOP package, refer to the Packaging Databook available from Texas Instruments.
Operating Ratings
VIN voltage 1.8V to 60V
External voltage applied to VCC 8.1V to 15V
Operating Junction Temperature -40°C to 125°C
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Electrical Characteristics(1)
Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
Powered Interface
IOS Offset Current VIN < 10.0V 10 uA
VCLSS(ON) Signature Resistor Disable / VIN with respect to VEE 10.0 11.5 12.5 V
Classification Current Turn On
VCLSS(OFF) Classification Current Turn Off VIN with respect to VEE 23.5 25.0 26.5 V
Classification Voltage With respect to VEE 1.43 1.5 1.57 V
ICLASS Supply Current During VIN =17V 0.5 1.0 mA
Classification
IDC Supply Current During Normal OUT floating 1 1.9 mA
Operation
UVLO Pin Reference Voltage VIN > 27V 1.95 2.00 2.05 V
UVLO Hysteresis Current VIN > UVLO 8.0 10 11.5 uA
Softstart Release RTN falling with respect to VEE 1.2 1.45 1.7 V
Softstart Release Hysteresis RTN rising with respect to VEE 0.8 1.1 1.3 V
RDS(ON) PowerFET Resistance I = 350mA, VIN = 48V 1 2.2 Ω
ILEAK SMPS Bias Current VEE = 0V, VIN = RTN = 57V 100 uA
AUX Pin Threshold AUX pin rising with respect to VEE 2.4 2.5 2.65 V
AUX Pin Threshold Hysteresis AUX pin falling with respect to VEE 0.4 0.5 0.6 V
ZAUX AUX Pin Input Impedance AUX = 0.5V 350 kΩ
IINRUSH Inrush Current Limit VEE = 0V, RTN = 3.0V 70 100 130 mA
ILIM DC Current Limit VEE = 0V, RTN = 3.0V, 350 390 420 mA
Temp = 0°C to 85°C
ILIM DC Current Limit VEE = 0V, RTN = 3.0V, Temp = - 325 390 420 mA
40°C to 125°C
Startup Regulator
VinMin Operational VIN Input Voltage AUX = 5V, Vcc = Vin(2) 9.5 V
VccReg VCC Regulation Open ckt 7.5 7.8 8.1 V
VCC Current Limit See(3) 15 20 mA
VCC Supply
VCC UVLO (Rising) VccReg VccReg –
– 300mV 100mV
VCC UVLO (Falling) 5.9 6.25 6.6 V
Supply Current (Icc) Cload = 0 1.5 3mA
Error Amplifier
GBW Gain Bandwidth 4 MHz
DC Gain 75 dB
Input Voltage FB = COMP 1.219 1.281 V
1.212 1.288
COMP Sink Capability FB=1.5V COMP=1V 520 mA
Current Limit
ILIM Delay to Output CS step from 0 to 0.6V, time to 20 ns
onset of OUT transition (90%)
Cycle by Cycle Current Limit 0.44 0.5 0.56 V
Threshold Voltage
(1) Min and Max limits are 100% production tested at 25 °C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instruments’ Average Outgoing Quality Level
(AOQL).
(2) The Vcc regulator requires an external source whenever the Vin pin is below 13V with respect to RTN. An external load on Vcc
increases this startup voltage requirement.
(3) Device thermal limitations may limit usable range.
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Electrical Characteristics(1) (continued)
Specifications in standard type face are for TJ= +25°C and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified: VIN = 48V, VCC = 10V, RT = 30.3kΩ.
Symbol Parameter Conditions Min Typ Max Units
Leading Edge Blanking Time 55 ns
CS Sink Impedance (clocked) 25 55 Ω
Soft-Start
Softstart Current Source 710 13 uA
Oscillator(4)
Frequency1 175 200 225 KHz
(RT = 30.3K)
Frequency2 505 580 665 KHz
(RT = 10.5K)
Sync threshold 3.1 3.8 V
PWM Comparator
Delay to Output COMP set to 2V 25 ns
CS stepped 0 to 0.4V, time to onset
of OUT transition low
Min Duty Cycle COMP=0V 0%
Max Duty Cycle (-80 Device) 80 %
Max Duty Cycle (-50 Device) 50 %
COMP to PWM Comparator Gain 0.33
COMP Open Circuit Voltage 4.5 5.4 6.3 V
COMP Short Circuit Current COMP= 0V 0.6 1.1 1.5 mA
Slope Compensation
Slope Comp Amplitude Delta increase at PWM Comparator 105 mV
(LM5071-80 Device Only) to CS
Output Section
Output High Saturation Iout = 50mA, 0.25 0.75 V
VCC - VOUT
Output Low Saturation Iout = 100mA 0.25 0.75 V
Rise time Cload = 1nF 15 ns
Fall time Cload = 1nF 15 ns
Thermal Shutdown
Tsd Thermal Shutdown Temp. 165 °C
Thermal Shutdown 25 °C
Hysteresis
Thermal Resistance
θJA Junction to Ambient PW Package 125 °C/W
(4) Specification applies to the oscillator frequency. The operational frequency of the LM5071-50 devices is divided by two.
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-60 -40 -20 0 20 40 60 80 100 120 140
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
SMPS BG (V)
TEMPERATURE (oC)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
390
392
394
396
398
400
402
404
406
FREQUENCY (kHz)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
8
8.5
9
9.5
10
10.5
11
11.5
12
UVLO HYSTERESIS CURRENT (PA)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
SOFTSTART CURRENT (PA)
8
8.5
9
9.5
10
10.5
11.5
12
11
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (oC)
360
365
370
375
380
385
390
395
400
DEFAULT CURRENT LIMIT (mA)
0 5 10 15 20 25 30 35 40 45 50
RT RESISTANCE (k:)
OSCILLATOR FREQUENCY (kHz)
0
200
400
600
800
1000
LM5071
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Typical Performance Characteristics
Default Current Limit vs Temperature Oscillator Frequency vs RT Resistance
Figure 3. Figure 4.
UVLO Hysteresis Current vs Temperature Softstart Current vs Temperature
Figure 5. Figure 6.
Oscillator Frequency vs Temperature
Error Amp Input Voltage vs temperature RT = 15.2 kΩ
Figure 7. Figure 8.
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-60 -40 -20 0 20 40 60 80 100 120 140
1.95
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
2.05
UVLO VTH (V)
TEMPERATURE (oC)
0 5 10 15 20 25
1
2
3
4
5
6
7
8
9
VCC (V)
ICC (mA)
010 20 30 40 50 60 70 80
INPUT VOLTAGE (V)
0.5
1
1.5
2
2.5
3
INPUT CURRENT (mA)
0
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Typical Performance Characteristics (continued)
VCC vs ICC Input Current vs Input Voltage
Figure 9. Figure 10.
UVLO Threshold vs Temperature
Figure 11.
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5
VIN
AUX
VEE
RCLASS
RTN
ARTN
OUT OUT
VCC
RSIG Thermal
Limit
UVLO
+
_
EN
VBG
+
_
+
_
+
_
EN
+
_
VIN
UVLORTN
+
-
VIN
+
_
Hysteresis
60V
2V
2V
-
+
1.5V
force_enable
LT25V
10PA
350k:
10V
2.5V
Gate
Control
Power OK
1V
1.5V
SS
RT
CS
COMP
FB FB
COMP
CS
RT
SS
Controller
SMPS
LOCAL_EN
VCC
See Figure 4
LM5071
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Specialized Block Diagrams
Figure 12. Top Level Block Diagram
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CS
LOGIC
OUT
DRIVER
PWM
100k
50k
CLK
SS
VCC
2k
CLK +LEB
80% MAX
DUTY LIMIT (-80)
50% MAX
DUTY LIMIT (-50)
COMP
OSC RT
0.5V
0
45 PA
R
S
Q
Q
+
-
+
-
5k
1.4V
SS
FB
1.25V
5V
+
-
10 PASS
Slope
Compensation
Generator
-50 Device Has
No Slope
Compensation
CURRENT
LIMIT
LM5071
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Figure 13. PWM Controller Block Diagram
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DETAILED OPERATING DESCRIPTION
The LM5071 power interface port and pulse width modulation (PWM) controller provides a complete integrated
solution for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. Major features of the
PD interface portion of the IC include detection, classification, thermal limit, programmable undervoltage lockout,
and current limit monitoring. The device also includes a high-voltage start-up bias regulator that operates over a
wide input range up to 60V. The switch mode power supply (SMPS) control portion of the IC includes power
good sensing, VCC regulator under-voltage lockout, cycle-by-cycle current limit, error amplifier, slope
compensation, soft-start, and oscillator sync capability. This high speed BiCMOS IC has total propagation delays
less than 100ns and a 1MHz capable oscillator programmed by a single external resistor. The LM5071 PWM
controller provides current-mode control for dc-dc converter topologies requiring a single drive output, such as
Flyback and Forward topologies. The LM5071 PWM enables all of the advantages of current-mode control
including line feed-forward, cycle-by-cycle current limit and simplified loop compensation. The oscillator ramp is
internally buffered and added to the PWM comparator input ramp to provide slope compensation necessary for
current mode control at duty cycles greater than 50% (-80 suffix only).
Modes of Operation
The LM5071 PD interface is designed to provide a fully compliant IEEE 802.3af system. As such, the modes of
operation take into account the barrel rectifiers often utilized to correctly polarize the dc input from the Ethernet
cable.
Table 1. Operating Modes With Respect to Input Voltage
Input Voltage VIN wrt VEE Mode of Operation
1.8V to 10.0V Detection (Signature)
12.5V to 25.0V Classification
25.0V to UVLO Rising Vth Awaiting Full Power
60V to UVLO Falling Vth Normal Powered Operation
An external signature resistor is connected to VEE when VIN exceeds 1.8V, initiating detection mode. During
detection mode, quiescent current drawn by the LM5071 is less than 10uA. Between 10.0V and 12.5V, the
device enters classification mode and the signature resistor is disabled. The nominal range for classification
mode is 11.5V to 25.0V. The classification current is turned off once the classification range voltage is exceeded,
to reduce power dissipation. Between 25.0V and UVLO release, the device is in a standby state, awaiting the
input voltage to reach the operational range to complete the power up sequence. Once the VIN voltage increases
above the upper UVLO threshold voltage, the internal power MOSFET is enabled to deliver a constant current to
charge the input capacitor of the dc-dc converter. When the MOSFET Vds voltage falls below 1.5V, the internal
Power Good signal enables the SMPS controller. The LM5071 is specified to operate with an input voltage as
high as 60.0V. The SMPS controller and internal MOSFET are disabled when VIN falls to the lower UVLO
threshold.
Detection Signature
To detect a potential powered device candidate, the PSE (Power Sourcing Equipment) will apply a voltage from
2.8V to 10V across the input terminals of the PD. The voltage can be of either polarity so a diode barrel network
is required on both lines to ensure this capability. The PSE will take two measurements, separated by at least 1V
and 2ms of time. The voltage ramp between measurement points will not exceed 0.1V/us. The delta voltage /
delta current calculation is then performed; if the detected impedance is above 23.75kΩand below 26.25kΩ, the
PSE will consider a PD to be present. If the impedance is less than 15kΩor greater than 33kΩa PD will be
considered not present and will not receive power. Impedances between these values may or may not indicate
the presence of a valid PD. The LM5071 will enable the signature resistor at a controller input voltage of 1.5V to
take into account the diode voltage drops. An external signature resistor should be placed between the VIN and
RSIG pins. The signature resistor is in parallel with the external UVLO resistor divider, and its value should be
calculated accordingly. Targeting 24.5kΩincreases margin in the signature design as the input bridge rectifier
diodes contribute to the series resistance measured at the PD input terminals. The PSE will tolerate no more
than 1.9V of offset voltage (caused by the external diodes) or more than 10uA of offset current (bias current).
The input capacitance must be greater than 0.05uF and less than 0.12uF. To increase efficiency, the signature
resistor is disabled by the LM5071 controller once the input voltage is above the detection range (> 11V).
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Classification
To classify the PD, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5071 enables
classification mode at a nominal input voltage of 11.5V. An internal 1.5V linear regulator and an external resistor
connected to the RCLASS pin provide classification programming current. Table 1 shows the external
classification resistor required for a particular class.
The classification current flows through the IC into the classification resistor. The suggested resistor values take
into account the bias current flowing into the IC. A different desired RCLASS can be calculated by dividing 1.5V
by the desired classification current.
Per the IEEE 802.3af specification, classification is optional, and the PSE will default to class 0 if a valid
classification current is not detected. If PD classification is not desired (i.e., Class 0), simply leave the RCLASS
pin open. The classification time period may not last longer than 75ms as per IEEE 802.3af. The LM5071 will
remain in classification mode until VIN is greater than 25V.
Table 2. Classification Levels and Required External Resistors
Class PMIN PMAX ICLASS ICLASS RCLASS
(MIN) (MAX)
0 0.44W 12.95W 0mA 4mA Open
1 0.44W 3.84W 9mA 12mA 150Ω
2 3.84W 6.49W 17mA 20mA 82.5Ω
3 6.49W 12.95W 26mA 30mA 54.9Ω
4 Reserved Reserved 36mA 44mA 38.3Ω
Undervoltage Lockout (UVLO)
The IEEE 802.3af specification states that the PSE will supply power to the PD within 400ms after completion of
detection. The LM5071 contains a programmable line Under Voltage Lock Out (UVLO) circuit. The first resistor
should be connected between the VIN to UVLO pins; the bottom resistor in the divider should be connected
between the UVLO and UVLORTN pins.
The divider must be designed such that the voltage at the UVLO pin equals 2.0V when VIN reaches the desired
minimum operating level. If the UVLO threshold is not met, the interface control and SMPS control will remain in
standby.
UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the
impedance of the UVLO set point divider. When the UVLO threshold is exceeded, the current source is activated
to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the
current source is turned off, causing the voltage at the UVLO pin to fall. The LM5071 UVLO thresholds cannot be
programmed lower than 25V, the AUX pin should be used to force UVLO release below 25V.
There are many additional uses for the UVLO pin. The UVLO function can also be used to implement a remote
enable / disable function. Pulling the UVLO pin down below the UVLO threshold disables the interface and SMPS
controller unless forced on via AUX pin operation.
AUX Pin Operation
The AUX pin can be used to force operation (UVLO release) of the interface and switching regulator at any input
voltage above 9.5V. This is especially useful for auxiliary input (wall transformer) input voltages. The pin has a
2.5V threshold (0.5V hysteresis) and an input impedance of approximately 350kΩ. The input resistor provides a
defined pull down impedance if the pin is left open by the user. An external pull down resistor should be used to
provide additional noise immunity. The resultant pin voltage from the external resistor divider should be well
above the 2.5V threshold to ensure proper auxiliary operation. See Figure 14 for an example of a simple yet
robust auxiliary configuration.
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Figure 14. Simplified Schematic Showing Auxiliary Implementation
Power Supply Operation
Once the UVLO threshold has been satisfied, the interface controller of the LM5071 will charge up the SMPS
input capacitor through the internal power MOSFET. This load capacitance provides input filtering for the power
converter section and must be at least 5uF per the IEEE 802.3af specification. To accomplish the charging in a
controlled manner, the power MOSFET is current limited to 100mA.
The SMPS controller will not initiate operation until the load capacitor is completely charged. The power
sequencing between the interface circuitry and the SMPS controller occurs automatically within the LM5071.
Detection circuitry monitors the RTN pin to detect interface startup completion. When the RTN pin potential drops
below 1.5V with respect to VEE, the VCC regulator of the SMPS controller is enabled. The soft-start function is
enabled once the VCC regulator achieves minimum operating voltage. The inrush current limit only applies to the
initial charging phase. The interface power MOSFET current limit will revert to the default protection current limit
of 390mA once the SMPS is powered up and the soft-start pin sequence begins.
High Voltage Start-up Regulator
The LM5071 contains an internal high voltage startup regulator that allows the input pin (VIN) to be connected
directly to line voltages as high as 60V. The regulator output is internally current limited to 15mA. The
recommended capacitance range for the VCC regulator output is 0.1uF to 10uF. When the voltage on the VCC pin
reaches the regulation point of 7.8V, the controller output is enabled. The controller will remain enabled until VCC
falls below 6.25V.
In typical applications, a transformer auxiliary winding is diode connected to the VCC pin. This winding should
raise the VCC voltage above 8.1V to shut off the internal startup regulator. Though not required, powering VCC
from an auxiliary winding improves conversion efficiency while reducing the power dissipated in the controller.
The external VCC capacitor must be selected such that the capacitor maintains the VCC voltage greater than the
VCC UVLO falling threshold (6.25V) during the initial start-up. During a fault condition when the converter auxiliary
winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the
start-up regulator does not exceed the maximum power dissipation capability of the LM5071 package.
If the VCC auxiliary winding is used with a low voltage auxiliary supply (wall transformer), the VCC pin could back
feed through the LM5071 to the VIN pin. A diode from VCC to VIN should be used to clamp the VCC pin and
prevent this internal back feed. The winding voltage will remain the same and extra power will be dissipated in
the series resistor. Also, note that when using a very low voltage auxiliary supply (<14V), a diode from the AUX
supply to the VCC pin should be used to ensure VCC startup.
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SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
www.ti.com
Figure 15. Simplified Schematic Showing Low Voltage Auxiliary Supply
Error Amplifier
An internal high gain error amplifier is provided within the LM5071. The amplifier’s non-inverting reference is set
to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated applications,
the power converter output is connected to the FB pin via voltage scaling resistors. Loop compensation
components are connected between the COMP and FB pins. For most isolated applications the error amplifier
function is implemented on the secondary side of the converter and the internal error amplifier is not used. The
internal error amplifier is configured as an open drain output and can be disabled by connecting the FB pin to
ARTN. An internal 5K pull-up resistor between a 5V reference and COMP can be used as the pull-up for an
optocoupler in isolated applications.
Current Limit / Current Sense
The LM5071 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an
internal current sense comparator. If the voltage at the current sense comparator input CS exceeds 0.5V with
respect to RTN/ARTN, the output pulse will be immediately terminated. A small RC filter, located near the CS pin
of the controller, is recommended to filter noise from the current sense signal. The CS input has an internal
MOSFET which discharges the CS pin capacitance at the conclusion of every cycle. The discharge device
remains on an additional 50ns after the beginning of the new cycle to attenuate the leading edge spike on the
current sense signal.
The LM5071 current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be located very close to the device and connected directly to the pins of the controller (CS
and ARTN). If a current sense transformer is used, both leads of the transformer secondary should be routed to
the sense resistor and the current sense filter network. A sense resistor located in the source of the primary
power MOSFET may be used for current sensing, but a low inductance resistor is required. When designing with
a current sense resistor, all of the noise sensitive low power ground connections should be connected together
local to the controller and a single connection should be made to the high current power return (sense resistor
ground point).
14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5071
RT = 1
F x 330 x 10-12
RT = 1
F x 165 x 10-12
LM5071
www.ti.com
SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
Oscillator, Shutdown and Sync Capability
A single external resistor connected between the RT and ARTN pins sets the LM5071 oscillator frequency.
Internal to the LM5071–50 device (50% duty cycle limited option) is an oscillator divide by two circuit. This divide
by two circuit creates an exact 50% duty cycle clock which is used internally to create a precise 50% duty cycle
limit function. Because of this divide by two, the internal oscillator actually operates at twice the frequency of the
output (OUT). For the LM5071–80 device the oscillator frequency and the operational output frequency are the
same. To set a desired output operational frequency (F), the RT resistor can be calculated from:
LM5071-80:
(1)
LM5071-50:
(2)
The LM5071 can also be synchronized to an external clock. The external clock must have a higher frequency
than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled
into the RT pin with a 100pF capacitor. A peak voltage level greater than 3.7 volts at the RT pin is required for
detection of the sync pulse. The sync pulse width should be set between 15 to 150ns by the external
components. The RT resistor is always required, whether the oscillator is free running or externally synchronized.
The voltage at the RT pin is internally regulated to a 2 volts. The RT resistor should be located very close to the
device and connected directly to the pins of the controller (RT and ARTN).
PWM Comparator / Slope Compensation
The PWM comparator compares the current ramp signal with the loop error voltage derived from the error
amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated
by a 3:1 resistor divider. The PWM comparator polarity is such that 0 Volts on the COMP pin will result in zero
duty cycle at the controller output. For duty cycles greater than 50 percent, current mode control circuits are
subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation)
to the current sense signal, this oscillation can be avoided. The LM5071-80 integrates this slope compensation
by summing a current ramp generated by the oscillator with the current sense signal. Additional slope
compensation may be added by increasing the source impedance of the current sense signal (with an external
resistor between the CS pin and current sense resistor). Since the LM5071-50 is not capable of duty cycles
greater than 50%, there is no slope compensation feature in this device.
Soft-Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thereby
reducing start-up stresses, output overshoot and current surges. At power on, after the VCC undervoltage lockout
threshold is satisfied, an internal 10μA current source charges an external capacitor connected to the SS pin.
The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output
pulses.
Gate Driver and Maximum Duty Cycle Limit
The LM5071 provides an internal gate driver (OUT), which can source and sink a peak current of 800mA. The
LM5071 is available in two duty cycle limit options. The maximum output duty cycle is typically 80% for the
LM5071-80 option and precisely equal to 50% for the LM5071-50 option. The maximum duty cycle function for
the LM5071-50 is accomplished with an internal toggle flip-flop which ensures an accurate duty cycle limit. The
internal oscillator frequency of the LM5071-50 is therefore twice the operating frequency of the PWM controller
(OUT pin).
The 80% maximum duty cycle limit of the LM5071-80 is determined by the internal oscillator and varies more
than the 50% limit of the LM5071-50. For the LM5071-80, the internal oscillator frequency and the operational
frequency of the PWM controller are equal.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5071
LM5071
SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
www.ti.com
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. This feature prevents catastrophic failures from accidental device overheating. When
activated, typically at 165 degrees Celsius, the controller is forced into a low power standby state, disabling the
output driver, bias regulator, main interface pass MOSFET, and classification regulator if enabled. After the
temperature is reduced (typical hysteresis = 25°C) the VCC regulator will be enabled and a softstart sequence
initiated.
Thermal shutdown is not enabled during auxiliary power operation as the power MOSFET is not running any
current and should not experience an over-temperature condition. If the drain of the MOSFET exceeds 2.5V with
respect to VEE (internal Power Good de-assertion), PoE UVLO becomes de-asserted (insertion of PoE or other
48V supply), or the auxiliary power is removed, thermal limit will be re-enabled immediately.
LM5071 Application Circuit Diagrams
Figure 16. Single Isolated Output with Diode Rectification and 12V Auxiliary Supply
16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5071
LM5071
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SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
Figure 17. Dual Isolated Output with Diode Rectification
Figure 18. Non-Isolated Output Buck with Diode Rectification
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5071
LM5071
SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 17
18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5071
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5071MT-50/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5071MT
-50
LM5071MT-80/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5071MT
-80
LM5071MTX-50/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5071MT
-50
LM5071MTX-80/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5071MT
-80
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5071MTX-50/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LM5071MTX-80/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5071MTX-50/NOPB TSSOP PW 16 2500 853.0 449.0 35.0
LM5071MTX-80/NOPB TSSOP PW 16 2500 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
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