Philips Semiconductors Product specification Remote 8-bit I/O expander for I?C-bus PCF8574 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 CHARACTERISTICS OF THE I2C-BUS 6.1 Bit transfer 6.2 Start and stop conditions 6.3 System configuration 6.4 Acknowledge 7 FUNCTIONAL DESCRIPTION 7.1 Addressing 7.2 Interrupt 7.3 Quasi-bidirectional I/Os 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS 11 l2C-BUS TIMING CHARACTERISTICS 12 PACKAGE OUTLINES 13 SOLDERING 13.1 Introduction 13.2 DIP 13.2.1 Soldering by dipping or by wave 13.2.2 Repairing soldered joints 13.3 SO and SSOP 13.3.1 Reflow soldering 13.3.2 Wave soldering 13.3.3 Repairing soldered joints 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I?@ COMPONENTS 1997 Apr 02 2Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 1 FEATURES Operating supply voltage 2.5 to 6 V Low standby current consumption of 10 uA maximum e [2C to parallel port expander Open-drain interrupt output 8-bit remote I/O port for the I?C-bus Compatible with most microcontrollers e Latched outputs with high current drive capability for directly driving LEDs e Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A) e DIP16, or space-saving SO16 or SSOP20 packages. 3 ORDERING INFORMATION 2 GENERAL DESCRIPTION The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I?C). The device consists of an 8-bit quasi-bidirectional port and an l?C-bus interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I?C-bus. This means that the PCF8574 can remain a simple slave device. The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.9. PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF8574P; DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-1 PCF8574AP PCF8574T; SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 PCF8574AT PCF8574TS SSOP20_ | plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 1997 Apr 02 3Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 4 BLOCK DIAGRAM INT AO Al A2 SCL SDA Vss INTERRUPT LOGIC LP FILTER PCF8574 INPUT 12C-BUS FILTER CONTROL SHIFT SBIT REGISTER WRITE pulse READ POWER-ON RESET MBD980 Fig.1 Block diagram (SOT38-1 and SOT162-1). 1997 Apr 02Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 5 PINNING PIN SYMBOL DESCRIPTION DIP16; SO16 SSOP20 AO 1 6 address input 0 Al 2 7 address input 1 A2 3 9 address input 2 PO 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 Vss 8 15 supply ground P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line Vpp 16 5 supply voltage n.c. - 3 not connected n.c. - 8 not connected n.c. - 13 not connected n.c. - 18 not connected INT [4 | U [20] P7 ao [1 U 6] Yop scL [2] 19] Pe At [2] 15] SDA ne. |3 18] nc. a2 [3 4] Sct SpA [4] 7] Ps PO[4] pcresza [13] INT Yoo Ls] fie] Pa PCF8574A PCF8574TS P1 [5 12] P7 ao [6 | 15] Yss pe [6 | 11] Pe Ai [7 14] P3 P3 [7] 10] PS nc. | 8 13] nc. Vss La | fo] Pa A2 [9 | 12] P2 MBD979 Po [79] 4] Py MBD978 Fig.2 Pin configuration (DIP16; SO16). Fig.3 Pin configuration (SSOP20). 1997 Apr 02 5Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 6 CHARACTERISTICS OF THE I?C-BUS The I#C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 6.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.4). 6.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.5). 6.3. System configuration A device generating a message is a transmitter, a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Fig.6). | | a A | I I I I | I | I I | data line | | stable; | | data valid | sof Nf NL Fig.4 Bit transfer. X \ I change | of data | allowed | MBC621 cTT TT cTT -- | --- | -- SDA \ / \ / SDA | I 77 I | I I __. I I __ SCL | | \ / \ / | | SCL 1; Ss | 1 P | START condition STOP condition MBC622 Fig.5 Definition of start and stop conditions. SDA SCL MASTER SLAVE MASTER TRANSMITTER / REOENER TRANSMITTER / TRANSMIEGER TRANSMITTER / RECEIVER RECEIVER RECEIVER Fig.6 System configuration. MBA605 1997 Apr 02Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 6.4 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by net generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. XX / not acknowledge \ 4 DATA OUTPUT | | / BY TRANSMITTER | I | | DATA OUTPUT rt BY RECEIVER | || SCL FROM 1 MASTER | | Ls | START CONDITION YY acknowledge clock pulse for MBC602 acknowledgement Fig.7 Acknowledgment on the |@#C-bus. 1997 Apr 02Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 7 FUNCTIONAL DESCRIPTION Vpp write pulse +p+ data from . shift register DQ : 0 FF C "| PO to P7 = I, _] A power-on x reset " [| Vss D Q FF Cc read pulse _, | ~~) > I, data to . _}) > to merupl shift register . 7 9g MBD977 Fig.8 Simplified schematic diagram of each I/O. 7.1. Addressing For addressing see Figs 9, 10 and 11. slave address slave address oS oaq\""M UAL c ~ T T T T T T T T T T T T T }s[o. 10,0 2 a1 ao ola] |s[o 1.1.1 a2 ar aololfa MBD973 a b. (a) PCF8574. (b) PCF8574A. Fig.9 PCF8574 and PCF8574A slave addresses. Each of the PCF8574s eight I/Os can be independently used as an input or output. Input data is transferred from the port to the microcontroller by the READ mode (see Fig.11). Output data is transmitted to the port by the WRITE mode (see Fig.10). 1997 Apr 02 8Product specification Philips Semiconductors PCF8574 Remote 8-bit I/O expander for I2C-bus (Indjno) epow FLIYM O}bi4 rzeqaan ad ad | ot oe | | | L T T | 1YOd WOuds anvazviva X | aIvA | Viva x | | TNO VLWG T 7 l ! ! | | T 41uOd Li U OL SLIM | | | SAR|S LOY | SAR|S LOY | OAB|S WO | abpejmouyoe | abpejmouyoe | aBpajmouyoe | M/d UOT}IPUCD pes | | | ! ! "wy ' TTT TTT TT TTT TIT Vv 2eVivd V | VLVG V Oo OV IV ev iO 0 I 0 Ss vas | | | \ | | | | | | | ! | | | | | | | | | | | | nN Zot d a _ oN pod 0} Byep (p26840d) sseippe anes | | pod 0} eyep | | | | TOS 1997 Apr 02Product specification Philips Semiconductors PCF8574 Remote 8-bit I/O expander for I2C-bus Qndul) epow qyay 1164 "JSO] SI Byep yndu| (apow yndjno) plea si eseud abpajmouyoe jse] Oy} ye jugsaid eyep sino90 siy} USYAA UOIPUCD dojs e Aq jUBLUOW Aue ye paddojs oq ued Byep Jo Jaysues| (q) UO!}|PUOD do}s aU} SB PEUYap SI HD|H SI TOS aIlyM WOS Jo UOISsUBI} HD|H-O}-MO7 V S/eqan | 4 um a 4 mm aad ~ | | LT L_! LNI | | | | | >| $4) a Uy ! Ll - | T T | 41uOd | viva | X viva Xz vivo | 3 OINI viva T | | | ! | | | 4LYOd I U U WOuS ava uOl}I|PUoS ! SARIS WO ! SARIS WO ! dois | abpaymouyoe | aBpajmouyoe | M/Y UOT}IPUCD pes | | | r v my 1 ne ee ee ee | T rs ee ee | es es ee ee d I vvivd V | VLVG Vv | OV IV ev Oo 0 I 0 Ss vds | | | | | | | | | | | | | | | | | | | | | | | v Jo J ~~ ~Y ~Y pod woy eyep od woy eyep (p26840d) Sseippe anes 10 1997 Apr 02Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 7.2 Interrupt (see Figs 12 and 13) The PCF8574 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time ti, the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. Resetting occurs as follows: Inthe READ mode at the acknowledge bit after the rising edge of the SCL signal e In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal e Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. 7.3. Quasi-bidirectional I/Os (see Fig. 14) A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode only a current source to Vpp is active. An additional strong pull-up to Vpp allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. Vop PCF8574 (1) PCF8574 (2) PCF8574 (16) MICROCOMPUTER INT INT Fig.12 Application of multiple PCF8574s with interrupt. MBD976 slave address (PCF8574) .__~ data from port T T T T soa fsfo 1 0 0) f start condition R/W | acknowledge P5 stop from slave condition | sch iLL | | | | DATA INTO | P5 _* | | | | IN | _ | INT | MBD972 wt iv Le +l tir Le. Fig.13 Interrupt generated by a change of input to I/O P5. 1997 Apr 02 11Product specification Philips Semiconductors PCF8574 Remote 8-bit I/O expander for I2C-bus "MO7] 0} YORG PUB HDIH-O}- M07] Wo seBueyo eg aylym IHO} Juauno dn-|ind juaisuesl py} 64 | .zeqaw | HO} | | HHO] INaYHNO | iy INdLNo | df-Tind d | ADVLIOA INdLNo ed | | | | 70s ! ! BAR|S WO | ed | Ed eBpejmouyoe = M/Y uo}pucd pe}s | ' | 1 1 ' | | | | T T T T T T T | | | T T T T T T T | | T T T T T T T | | d |v 0 v IL v|o ov Ww ewioe. ot +t oj|fs] yas | ! ! ! ! ! ! ! | ! ! ! ! ! ! ! ! ! ! ! ! ! ! KX A KX A xX J Y a pod 0} eyep pod 0} eyep (V29840d) sseippe ones 12 1997 Apr 02Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT Vpp supply voltage 0.5 +7.0 Vv Vi input voltage Vss 0.5 Vpp + 0.5 V I DC input current - +20 mA lo DC output current - +25 mA Ipp supply current - +100 mA Iss supply current - +100 mA Prot total power dissipation - 400 mW Po power dissipation per output - 100 mW Tstg storage temperature 65 +150 C Tamb operating ambient temperature 40 +85 C 9 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under Handling MOS Devices. 10 DC CHARACTERISTICS Vpp = 2.5 to 6 V; Vgg = 0 V; Tamb = 40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply Vpp supply voltage 2.5 - 6.0 Vv Ipp supply current operating mode; Vpp = 6 V; | - 40 100 HA no load; V| = Vpp or Vss; fsc_ = 100 kHz Istb standby current standby mode; Vpp = 6 V;_ | - 2.5 10 HA no load; V| = Vpp or Vss Vpor Power-on reset voltage Vpp = 6 V; no load; - 1.3 2.4 Vv Vi = Vpp or Vgg; note 1 Input SCL; input/output SDA Vit LOW level input voltage -0.5 - +0.3Vpp Vv Vin HIGH level input voltage 0.7Vpp - Vpp + 0.5 |V lot LOW level output current VoL = 0.4 V 3 - - mA IL leakage current Vi = Vpp or Vss -1 - +1 HA Ci input capacitance Vi = Vss - - 7 pF 1997 Apr 02 13Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Os VIL LOW level input voltage -0.5 - +0.3Vpp Vv Vin HIGH level input voltage 0.7Vpp - Vpp + 0.5 |V IHL(max) maximum allowed input Vi = Vpp or Vi < Vss - - +400 HA current through protection diode lot LOW level output current Vo_=1V; Vpp =5 V 10 25 - mA lou HIGH level output current Vou = Vss 30 - 300 HA lout transient pull-up current HIGH during acknowledge | - -1 - mA (see Fig.14); Vou = Vss; Vpp = 2.5 V Ci input capacitance - - 10 pF Co output capacitance - - 10 pF Port timing; C, < 100 pF (see Figs 10 and 11) tov output data valid - - 4 us tsu input data set-up time 0 - - us th input data hold time 4 - - us Interrupt INT (see Fig. 13) lot LOW level output current VoL = 0.4 V 1.6 - - mA IL leakage current Vi = Vpp or Vss -1 - +1 HA TIMING; CL < 100 PF tiy input data valid time - - 4 us tir reset delay time - - 4 us Select inputs AO to A2 VIL LOW level input voltage -0.5 - +0.3Vpp Vv Vin HIGH level input voltage 0.7Vpp - Vpp + 0.5 |V Iu input leakage current pin at Vpp or Vss 250 - +250 nA Note 1. The Power-on reset circuit resets the I?C-bus logic with Vpp < Vpor and sets all I/Os to logic 1 (with current source to Vpp). 1997 Apr 02 14Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 11 12C-BUS TIMING CHARACTERISTICS SYMBOL PARAMETER MIN. TYP. MAX. UNIT l2C-BUS TIMING (see Fig. 15; note 1) fse SCL clock frequency - - 100 kHz tsw tolerable spike width on bus - - 100 ns tBuF bus free time 4.7 - - us tsu:STA START condition set-up time 4.7 - - us tHD-STA START condition hold time 4.0 - - us tLow SCL LOW time 4.7 - - ps tHIGH SCL HIGH time 4.0 - - ps tr SCL and SDA rise time - - 1.0 us tr SCL and SDA fall time - - 0.3 us tsu-DAT data set-up time 250 - - ns tuD-DAT data hold time 0 - - ns tvp:DAT SCL LOW to data out valid - - 3.4 us tsu-sto STOP condition set-up time 4.0 - - us Note 1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to Vi_ and Vjy with an input voltage swing of Vgg to Vpp. START BIT7 BIT6 BITo | ACKNOWLEDGE STOP PROTOCOL CONDITION MSB (A6) LSB (A) CONDITION (S) (A7) (R/W) (P) tsu-sTa tlow. 'HIGH 1/FscL_m SCL / \ \ L tf oe k aA ' HD:STA 'supat "Hp -DaAT ' yp:DAT mep820 tsu:sTo Fig.15 |#C-bus timing diagram. 1997 Apr 02 15Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 12 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 tt D > Me Q 5 a 2 P| pin 1 index 0 5 10 mm be dd scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay A2 (1) (1) z UNIT max. min. | max. b by c D E e e L Me Mu w max. 1.40 | 053 | 032 | 218 | 648 3.9 8.25 9.5 mm 47) 051 | 37 | 444 | 038 | 023 | 214 | 620 | 254 | 762 | 34 | 780 | 93 | 0254) 22 . 0.055 | 0.021 | 0.013 | 086 | 0.26 015 | 032 | 037 inches | 0.19 | 0.020 | 015 | jase | gois | 0009 | os | ona | 219 | 930 | gag | 931 | ogg | 0:01 | 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 92-40-02 SOT38-1 050G09 MO-001 AE on On 01 10 1997 Apr 02 16Product specification Philios Semiconductors Remote 8-bit I/O expander for I2C-bus $016: plastic small outline package; 16 leads; body width 7.5 mm PCF8574 $OT162-1 WW RAL ALB: i a Row TER pin 1 index | i me L wile H Hb HH Ho a ley. 0 oo 5 oo, 10 mm scale SOT162-1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT ma Ai | Az | Az | bp e | DM) EM) e@ HE L Ly Q v w y | 2] 6 mm | 265) 915 | 525 925 36/023 tor 74 | 127 i000 14 og | to 028) 025} 04 | OF | a nes | 010 oo oe oo ote ere. Oat | O30 laos] 942 |ooss 2042 2082 01 | oor |aoos 2008 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION Ec JeDEC was PROJECTION | 'SSUEDATE 075E03 MS-013AA oe Soataa 1997 Apr 02 17Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 8 aaa iT iT iT T 5 | iT iT iT iT pin 1 index | AY TEEUEDOEEE. Ger deere ~ oO 0 25 5mm scale DIMENSIONS (mm are the original dimensions) UNIT max. Ay A2 A3 bp c bp | &@) e He L Lp Q v w y 20 mm 15 | ) 15 (025) Ooo lors | ea 43 | 295| o> | 12 Gas oss | 02 013) 01 | OT | Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT266-1 EI 95-02-25 ISSUE DATE 1997 Apr 02 18Philios Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 13 SOLDERING 13.1. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). 13.2 DIP 13.2.1. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 13.2.2 REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 13.3. SO and SSOP 13.3.1 REFLOW SOLDERING Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Apr 02 19 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 13.3.2 WAVE SOLDERING Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.3.3. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.