TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETS (SWIFT™)
6,4 mm X 9,7 mm
FEATURES
D30-mΩ MOSFET Switches for High Efficiency
at 8-A Continuous Output
D0.9-V to 3.3-V Adjustable Output Voltage
Range With 1% Accuracy
DExternally Compensated
DFast Transient Response
DWide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
DLoad Protected by Peak Current Limit and
Thermal Shutdown
DIntegrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
DLow-Voltage, High-Density Systems With
Power Distributed at 5 V
DPoint of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
DBroadband, Networking, and Optical
Communications Infrastructure
DPortable Computing/Notebook PCs
DESCRIPTION
As a member of the SWIFT™ family of dc/dc regulators,
the TPS54810 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3.8 V; an internally or
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
The TPS54810 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
VSENSE
VIN PH
BOOT
PGND
Output
COMP
AGND
VBIAS
Input
TPS54810
SIMPLIFIED SCHEMATIC
VSENSE
Compensation Network
IL − Load Current − A
Efficiency − %
EFFICIENCY AT 700 HZ
50
55
60
65
70
75
80
85
90
95
100
012345678910
VI = 5 V
VO = 3.3 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
PowerPAD and SWIFT are trademarks of Texas Instruments.
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAOUTPUT VOLTAGE PACKAGE PART NUMBER
−40°C to 85°C0.9 V to 3.3 V PLASTIC HTSSOP (PWP)(1) TPS54810PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54810PWPR). See the application section
of the data sheet for PowerPAD™ drawing and layout information.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54810 UNIT
VIN, SS/ENA, SYNC −0.3 to 7
I t lta a V
RT −0.3 to 6
V
Input voltage range, VIVSENSE −0.3 to 4 V
BOOT −0.3 to 17
O t t lta a V
VBIAS, COMP, PWRGD −0.3 to 7
V
Output voltage range, VOPH −0.6 to 10 V
S t I
PH Internally Limited
Source current, IOCOMP, VBIAS 6 mA
PH 12 A
Sink current, ISCOMP 6
A
Sink current, IS
SS/ENA, PWRGD 10 mA
Voltage differential AGND to PGND ±0.3 V
Operating virtual junction temperature range, TJ−40 to 125 °C
Storage temperature, Tstg −65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage range, VI4 6 V
Operating junction temperature, TJ−40 125 °C
DISSIPATION RATINGS(1) (2)
PACKAGE THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28-Pin PWP with solder 18.2 °C/W 5.49 W(2) 3.02 W 2.20 W
28-Pin PWP without solder 40.5 °C/W 2.48 W 1.36 W 0.99 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test Board Conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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3
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN 4.0 6.0 V
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open 11 15.8
I(Q) Quiescent current fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open 16 23.5 mA
Shutdown, SS/ENA = 0 V 1.0 1.4
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO 3.8 3.85 V
Stop threshold voltage, UVLO 3.40 3.50 V
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch, UVLO (1) 2.5 µs
BIAS VOLTAGE
Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 2.90 V
Output current, VBIAS (2) 100 µA
CUMULATIVE REFERENCE
Vref Accuracy 0.882 0.891 0.900 V
REGULATION
Line regulation(1) (3)
IL = 4 A, fs = 350 kHz, TJ = 85°C 0.04
%/V
Line regulation
(1)
(3)
IL = 4 A, fs = 550 kHz, TJ = 85°C 0.04 %/V
Load regulation(1) (3)
IL = 0 A to 8 A, fs = 350 kHz, TJ = 85°C 0.03
%/A
Load regulation
(1)
(3)
IL = 0 A to 8 A, fs = 550 kHz, TJ = 85°C 0.03 %/A
OSCILLATOR
Internally set free running frequency range
SYNC ≤ 0.8 V, RT open 280 350 420
kHz
Internally set—free running frequency range SYNC ≥ 2.5 V, RT open 440 550 660 kHz
RT = 180 kΩ (1% resistor to AGND) 252 280 308
Externally set—free running frequency range RT = 100 kΩ (1% resistor to AGND) 460 500 540 kHz
Externally set free running frequency range
RT = 68 kΩ (1% resistor to AGND) 663 700 762
kHz
High level threshold, SYNC 2.5 V
Low level threshold, SYNC 0.8 V
Pulse duration, external sychronization, SYNC (1) 50 ns
Frequency range, SYNC (1) 330 700 kHz
Ramp valley (1) 0.75 V
Ramp amplitude (peak-to-peak) (1) 1 V
Minimum controllable on time (1) 200 ns
Maximum duty cycle (1) 90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 9
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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4
ELECTRICAL CHARACTERISTICS CONTINUED
TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain 1 kΩ COMP to AGND(1) 90 110 dB
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND(1) 3 5 MHz
Error amplifier common mode input voltage
range Powered by internal LDO(1) 0 VBIAS V
Input bias current, VSENSE VSENSE = Vref 60 250 nA
Output voltage slew rate (symmetric), COMP 1.0 1.4 V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding dead-
time)
10-mV overdrive(1) 70 85 ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA 0.82 1.20 1.40 V
Enable hysteresis voltage, SS/ENA (1) 0.03 V
Falling edge deglitch, SS/ENA (1) 2.5 µs
Internal slow-start time 2.6 3.35 4.1 ms
Charge current, SS/ENA SS/ENA = 0V 3 5 8 µA
Discharge current, SS/ENA SS/ENA = 1.3 V, VI = 1.5 V 1.5 2.3 4.0 mA
POWER GOOD
Power good threshold voltage VSENSE falling 90 %Vref
Power good hysteresis voltage(1) 3 %Vref
Power good falling edge deglitch(1) 35 µs
Output saturation voltage, PWRGD I(sink) = 2.5 mA 0.18 0.3 V
Leakage current, PWRGD VI = 3.6 V 1µA
CURRENT LIMIT
Current limit
VI = 4.5 V(1), output shorted 911
A
Current limit VI = 6 V(1), output shorted 10 12 A
Current limit leading edge blanking time 100 ns
Current limit total response time 200 ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1) 135 150 165 _C
Thermal shutdown hysteresis(1) 10 _C
OUTPUT POWER MOSFETS
P MOSFET it h
VI = 6 V(2) 26 47
Ω
rDS(on) Power MOSFET switches VI = 4.5 V(2) 30 60 mΩ
(1) Specified by design
(2) Matched MOSFETs, low-side rDS(on) production tested, high-side rDS(on) production tested.
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
Terminal Functions
TERMINAL
DESCRIPTION
NAME NO. DESCRIPTION
AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point
connection to AGND is recommended.
PH 6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD 4 Power good open drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or the internal shutdown signal is active.
RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC 27 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low-ESR 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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6
FUNCTIONAL BLOCK DIAGRAM
Falling
Edge
Deglitch
Enable
Comparator
1.2 V
VIN
3.8 V
Hysteresis: 0.03 V 2.5 µs
Falling
and
Rising
Edge
Deglitch
2.5 µs
VIN UVLO
Comparator
Hysteresis: 0.16 V
Internal/External
Slow-Start
(Internal Slow-Start Time = 3.35 ms)
Reference
VREF = 0.891 V
−
+
Error
Amplifier
Thermal
Shutdown
150°C
SHUTDOWN
SS_DIS
PWM
Comparator
OSC
Leading
Edge
Blanking
100 ns
RQ
S
Adaptive Dead-Time
and
Control Logic
SHUTDOWN
30 mΩ
VIN
REG
VBIAS
VIN
BOOT
VIN
PH
CO
PGND
PWRGD
Falling
Edge
Deglitch
35 µs
VSENSE
SHUTDOWN
0.90 Vref
Hysteresis: 0.03 Vref
Powergood
Comparator
AGND VBIAS
ILIM
Comparator 3 − 6 V
VO
SYNC
RTCOMPVSENSE
SS/ENA
TPS54810
30 mΩ
LOUT
RELATED DC/DC PRODUCTS
DTPS56300—dc/dc controller
DPT6600 series—9-A plugin modules
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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7
TYPICAL CHARACTERISTICS
Figure 1
0
10
20
30
40
50
60
−40 −15 10 35 60 85 110 135
VI = 5 V,
IO = 8 A
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
Drain Source On-State Reststance − mΩ
Figure 2
250
350
450
550
650
750
−40 0 25 85 125
TJ − Junction Temperature − °C
f − Internally Set Oscillator Frequency − kHz
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
SYNC ≥ 2.5 V
SYNC ≤ 0.8 V
Figure 3
200
300
400
500
600
700
800
−40 0 25 85 125
TJ − Junction Temperature − °C
f − Externally Set Oscillator Frequency − kHz
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
RT = 68 k
RT = 100 k
RT = 180 k
Figure 4
0.885
0.887
0.889
0.891
0.893
0.895
−40 0 25 85 125
TJ − Junction Temperature − °C
− Voltage Reference − V
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
Vref
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
012345678
IL − Load Current − A
Device Power Losses − W
DEVICE POWER LOSSES
vs
LOAD CURRENT
TJ = 125°C
fs = 700 kHz
VI = 5 V
Figure 5
Figure 6
VI − Input Voltage − V
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
− Output Voltage Regulation − V
VO
0.885
0.887
0.889
0.891
0.893
0.895
4.5 4.8 5.1 5.4 5.7 6
Figure 7
−20
0
20
40
60
80
100
120
140
1 100 1 k 1 M
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
10 10 k 100 k 10 M
f − Frequency − Hz
Gain − dB
ERROR AMPLIFIER
OPEN LOOP RESPONSE
Phase − De
g
rees
Phase
Gain
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
Figure 8
2.75
2.90
3.05
3.20
3.35
3.50
3.65
−40 0 25 85 125
TJ − Junction Temperature − °C
Internal Slow-Start Time − ms
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
3.80
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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8
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical
TPS54810 application. The TPS54810 (U1) can provide
up to 8 A of output current at a nominal output voltage of
1.8 V. For proper thermal performance, the PowerPAD
underneath the integrated circuit TPS54810 needs to be
soldered well to the printed-circuit board.
28
6
VIN 24
23
22
21
20
VIN
VIN
VIN
VIN
14
13
12
11
10
9
8
7
PH
PH
PH
PH
PH
PH
PH
PH
PH
5
BOOT
19
18
17
16
15
PGND
PGND
PGND
PGND
PGND
PWRPAD
AGND
VSENSE
COMP
PWRGD
SS/ENA
SYNC
RT
27
26
VBIAS
25
4
3
2
1
U1
TPS54810PWP
0.047 µF
C9
0.047 µF
L1
0.65 µH
C8
22 µF
C10
10 µF
C12
10 µF
VO
3300 pF
VI
R7
2.4 Ω
C11
3300 pF
C7
22 µF
C5
22 µF
R6
71.5 kΩ
C6
1 µF
C3
R5
10 kΩ
C4
R3
10 kΩ
150 pF
C2
R2
301 Ω
1000 pF
C1
R1
10 kΩ
R4
9.76 kΩ
Analog and Power Grounds are Tied at the Pad Under the Package of IC
Figure 9. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional design information is available
at www.ti.com.
INPUT FILTER
The input voltage is a nominal 5 VDC. The input filter C10
is a 10-µF ceramic capacitor (Taiyo Yuden). C12, also a
10-µF ceramic capacitor (Taiyo Yuden) provides high
frequency decoupling of the TPS54810 from the input
supply and must be located as close as possible to the
device. Ripple current is carried in both C10 and C12, and
the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, and C8.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R1 and R4 sets the output voltage for the circuit
at 1.8 V. R1, along with R2, R3, C1, C2, and C4 forms the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5 kΩ
resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68 kΩ to 180 kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default of 350 kHz. The resistance can
be approximated using the following equation:
R+500 kHz
Switching Frequency 100 [kW]
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Pulse Engineering PA0277. The
capacitors used are 22-µF, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.
(1)
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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9
PCB LAYOUT
Figure 10 shows a generalized PCB layout guide for the
TPS54810
The VIN pins are connected together on the printed-circuit
board (PCB) and bypassed with a low-ESR
ceramic-bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS54810 ground
pins. The minimum recommended bypass capacitance is
10-µF ceramic capacitor with a X5R or X7R dielectric and
the optimum placement is closest to the VIN pins and the
PGND pins.
The TPS54810 has two internal grounds (analog and
power). Inside the TPS54810, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54810, particularly at higher output currents. Ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground traces are
recommended. There is an area of ground on the top layer
directly under the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to
any internal ground planes. Additional vias are also used
at the ground side of the input and output filter capacitors.
The AGND and PGND pins are tied to the PCB ground by
connecting them to the ground area under the device as
shown. The only components that tie directly to the power
ground plane are the input capacitors, the output
capacitors, the input voltage decoupling capacitor, and the
PGND pins of the TPS54810. Use a separate wide trace
for the analog ground signal path. The analog ground is
used for the voltage set point divider, timing resistor RT,
slow-start capacitor and bias capacitor grounds. Connect
this trace directly to AGND (Pin 1).
The PH pins are tied together and routed to the output
inductor. Since the PH connection is the switching node,
the inductor is located close to the PH pins. The area of the
PCB conductor is minimized to prevent excessive
capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, LOUT, COUT and PGND as small as
practical.
Place the compensation components from the VOUT trace
to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of
the IC package and the device pin-out, they must be routed
close, but maintain as much separation as possible while
still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350-kHz operating frequency, connect
them to this trace.
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
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10
AGND
BOOT
VSENSE
COMP
PWRGD
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
VOUT
PH
VIN
TOPSIDE GROUND AREA
VIA to Ground Plane
ANALOG GROUND TRACE
EXPOSED
POWERP AD
AREA
COMPENSA TION
NETWORK
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
FREQUENCY SET RESISTOR
SLOW ST ART
CAPACITOR
BIAS CAP ACITOR
Figure 10. PCB Layout
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
11
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 8 A or greater
operation is desired. Connection from the exposes area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance should be included in
areas not under the device package.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Top
Side Analog Ground Area
0.3478
0.0150
0.06
0.0256
0.1700
0.1340
0.0630
0.0400
Ø0.01804 PL
0.2090
Ø0.0130
8 PL
Minimum Recommended Exposed
Copper Area for Powerpad. 5-mil
Stencils May Require 10 Percent
Larger Area
0.0650
0.0500
0.0500
0.0650
0.0339
0.0339
0.0500
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
0.3820
Figure 11. Recommended Land Pattern for the 28−Pin PWP PowerPAD
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
12
PERFORMANCE GRAPHS (FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9)
Fi
g
ure 12
IO − Output Current − A
Efficiency − %
EFFICIENCY
vs
OUTPUT CURRENT
50
55
60
65
70
75
80
85
90
95
100
0246810
VI = 5 V
VO = 1.8 V
fs = 700 kHz
Figure 13
0.997
0.998
0.999
1
1.001
1.002
1.003
0246810
IO − Output Current − A
Load Regulation
LOAD REGULATION
vs
OUTPUT CURRENT
VI = 5 V
VO = 1.8 V
TA = 25°C
fs = 700 kHz
Figure 14
0.999
0.9992
0.9994
0.9996
0.9998
1
1.0002
1.0004
1.0006
1.0008
1.001
4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9
0 A
4 A
8 A
VI − Input Voltage − V
Line Regulation
LINE REGULATION
vs
INPUT VOLTAGE
VI = 5 V
VO = 1.8 V
TA = 25°C
fs = 700 kHz
Figure 15
25
35
45
55
65
75
85
95
105
115
125
01234
− Ambient Temperature −
AMBIENT TEMPERATURE
vs
OUTPUT CURRENT (1)
IO − Output Current − A
C
°
TA
567 8
VI = 5 V
TJ = 25°C
fs = 700 kHz
Figure 16
t − Time − 1 µs/div
Output Ripple Voltage − 10 mV/div
OUTPUT RIPPLE VOLTAGE
VI = 5 V
VO = 1.8 V
IO = 6 A
fs = 700 kHz
Fi
g
ure 17
t − Time − 20 µs/div
− Output Voltage − 100 mV/div
TRANSIENT RESPONSE
VO
− Output Current − 2 A/div
IO
VI = 5 V
2 A to 6.5 A
Figure 18
4.0 ms/div
Input Voltage − 2 V/div
SLOW-START TIMING
VI = 5 V,
0.04 µF
Slow-start Cap
Output Voltage − 2 V/div
(1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
13
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54810 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 3.80 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
3.5 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
td+C(SS) 1.2 V
5mA
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
ramp-up time set by the capacitor is approximately:
t(d) +C(SS) 0.7 V
5mA
The actual ramp-up time is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54810, since it cancels
offset errors in the scale and error amplifier circuits.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
required for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
Switching Frequency +100 kW
R 500 [kHz]
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose an RT resistor which
sets the free running frequency to 80% of the
synchronization signal. The following table summarizes
the frequency selection configurations:
SWITCHING FRE-
QUENCY
SYNC PIN RT PIN
350 kHz, internally set Float or AGND Float
550 kHz, internally set =2.5 V Float
Externally set 280 kHz
to 700 kHz
Float R = 68 k to 180 k
Externally synchro-
nized frequency
Synchronization
signal
R = RT value for 85%
of external synchro-
nization frequency
Error Amplifier
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54810 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
(2)
(3)
(4)
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
14
particular application needs. Type 2 or type 3 compensa-
tion can be employed using external compensation
components.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54810 is capable of sinking current continuously
until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge
blanking circuit prevents false tripping of the current limit
when the high side switch is turning on. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
Power Good (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low. When
VIN ≥ UVLO threshold, SS/ENA ≥ enable threshold, and
VSENSE > 90% of Vref, the open drain output of the
PWRGD pin is high. A hysteresis voltage equal to 3% of
Vref and a 35 µs falling edge deglitch circuit prevent
tripping of the power good comparator due to high
frequency noise.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS54810PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54810PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54810PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54810PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jul-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54810PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jul-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54810PWPR HTSSOP PWP 28 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jul-2009
Pack Materials-Page 2
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