Xicor, Inc. 1994, 1995, 1996 Patents Pending
9900-3003.1 4/1/99
1
Characteristics subject to change without notice
16K 2-Wire
RTC
Real Time Clock/Calendar/Alarm with EEPROM
FEATURES
• 2 Alarms—Interrupt Output
—Settable on the Second, 10s of Seconds,
Minute, 10s of Minutes, Hour, Day, Month, or
Day of the Week
—Repeat alarm for time base generation
• 2 Wire Interface interoperable with I
2
C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1
µ
A Operating Current
—<3mA Active Current during Program
—<400
µ
A Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1243 is a Real Time Clock with clock/calendar
circuits and two alarms. The dual port clock and alarm
registers allow the clock to operate, without loss of
accuracy, even during read and write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
An alarm match of the RTC sets an interrupt flag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1243 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
X1
X2 Oscillator Frequency Timer
Logic
Divider Calendar
8
32.768kHz
Control
Registers
1Hz Time
Keeping
Registers
Alarm Regs
Compare
Mask
IRQ
Control
Decode
Logic Alarm
(EEPROM)
(EEPROM)
(SRAM)
SCL
SDA
Serial
Interface
Decoder
Interrupt Enable 16K
EEPROM
Array
Register
Status
(SRAM) Alarm
Alarm
X1243
X1243
2
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and
may be wire ORed with other open drain or open col-
lector outputs. The input buffer is always active (not
gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz 2-wire
interface speeds.
V
BACK
This input provides a backup supply voltage to the
device. V
BACK
supplies power to the device in the
event the V
CC
supply fails.
Interrupt Output— IRQ
This is an interrupt signal output. This signal notifies a
host processor that alarm has occurred and requests
action. It is an open drain active LOW output.
X1, X2
The X1 and X2 pins are the input and output, respec-
tively, of an inverting amplifier that can be configured
for use as an on-chip oscillator. A 32.768kHz quartz
crystal is used. Recommeded crystals are Sieko VT-200
or Epson C-002RX. The crystal supplies a timebase
for a clock/oscillator. The internal clock can be driven
by an external signal on X1, with X2 left unconnected.
Figure 1. Recommended Crystal connection
POWER CONTROL OPERATION
The Power control circuit accepts a V
CC
and a V
BACK
input. The power control circuit will switch to V
BACK
when V
CC
< V
BACK
- 0.2V. It will switch back to V
CC
when V
CC
exceeds V
BACK
.
Figure 2. Power Control
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external, 32.768KHz
quartz crystal to maintain an accurate internal repre-
sentation of the year, month, day, date, hour, minute,
and seconds. The RTC has leap-year correction and a
century byte. The clock will also correct for months hav-
ing fewer than 31 days and will have a bit that controls
24 hour or AM/PM format. When the X1243 powers up
after the loss of both V
CC
and V
BACK
, the clock will not
increment until at least one byte is written to the clock
register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change dur-
ing the course of a read operation. In this device, the
time is latched by the read command (falling edge of
X1243
X1
X2
V
Back
V
CC
IRQ
SCL
SDA
VSS
1
2
3
4
7
8
6
5
8 pin TSSOP
X1243
X1
X2 VBack
VCC
IRQ SCL
SDA
VSS
1
2
3
4
7
8
6
5
8 pin SOIC
X1
X2
43pF
18pF
220K
10M
VBACK
VCC = VBACK -0.2V
Internal
Voltage
VCC
X1243
3
the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run. Alarms occuring
during a read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a seperate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the first “one second” clock cycle after
the stop bit. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any nonvolatile write sequences.
A single byte may be written to the RTC without affect-
ing the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
logically separated from the array and are only acces-
sible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address in
the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to
the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes)
2. Alarm 1 (8 bytes)
3. Control (2 bytes)
4. Real Time Clock (8 bytes)
5. Status (1 byte)
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The non-volatile portion (or the counter
portion of the RTC) is updated only if RWEL is set and
only after a valid write operation and stop bit. A sequen-
tial read or page write operation provides access to the
contents of only one section of the CCR per operation.
Access to another section requires a new operation.
Continued reads or writes, once reaching the end of a
section, will wrap around to the start of the section. A
read or page write can begin at any address in the CCR.
Section 5) is a volatile register. It is not necessary to set
the RWEL bit prior to writing the status register. Section 5)
supports a single byte read or write only. Continued reads
or writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
—The user can set the X1242 to alarm every Wednes-
day at 8:00 AM by setting the EDWn, the EHRn and
EMNn enable bits to ‘0’ and setting the DWAn,
HRAn and MNAn Alarm registers to 8:00 AM
Wednesday.
—A daily alarm for 9:30PM results when the EHRn
and EMNn enable bits are set to ‘0’ and the HRAn
and MNAn registers set 9:30 PM.
—Setting the EMOn bit in combination with other
enable bits and a specific alarm time, the user can
establish an alarm that triggers at the same time
once a year.
When there is a match, an alarm flag is set. The occur-
ance of an alarm can be determined by polling the AL0
and AL1 bits, or by setting the AL0E and AL1E bits to ‘1’
and monitoring the IRQ output. The AL0E and AL1E
bits enable the circuit that triggers the output IRQ pin
when an alarm occurs. Writing a ‘0’ to one of the bits
X1243
4
disables the output IRQ for that alarm condition, but the
alarm condition can still be checked by polling the
alarm flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Table 1. Clock/Control Memory Map
Addr. Type Reg
Name
Bit
Range
Factroy
Settings
76 5 4 3 21 0
(optional)
003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF
0037
RTC
(SRAM)
Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20
0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6
0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99
0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12
0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31
0032 HR T24 0 H21 H20 H13 H12 H11 H10 0-23
0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59
0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59
0011 Control
(E2PROM) INT IM AL1E AL0E 0 0 0 0 0 00h
0010 BL BP2 BP1 BP0 0 0 0 0 0 00h
000F
Alarm1
(E2PROM)
unused
000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 0h
000D YRA1 Unused - Default = RTC Year value
000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 0h
000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 0h
000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 0h
0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 0h
0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 0h
0007
Alarm0
(E2PROM)
unused
0006 DWA1 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 0h
0005 YRA0 Unused - Default = RTC Year value
0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 0h
0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 0h
0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 0h
0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 0h
0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 0h
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
The X1243 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical
X1243
5
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The Clock
Default values define 0=Sunday.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the time.
As such, SC (Seconds) and MN (Minutes) range from
00 to 59, HR (Hour) is 1 to 12 with an AM or PM indica-
tor (H21 bit) or 0 to 23 (with T24=1), DT (Date) is 1 to
31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
24 Hour Time
If the T24 bit of the HR register is 1, the RTC will use a
24-hour format. If the T24 bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
Standard Time with H21=0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible by
400. This means that the year 2000 is a leap year, the
year 2100 is not. The X1243 does not correct for the
leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read an optional Low Voltage Sense bit, and
read the two alarm bits. This register is logically seper-
ated from both the array and the Clock/Control Regis-
ters (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V
BACK
, not V
CC
. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective bit
is set to ‘1’. The falling edge of the last data bit in a SR
Read operation resets the flags. Note: Only the AL bits
that are set when an SR read starts will be reset. An
alarm bit that is set by an alarm occuring during an SR
read operation will remain set after the read operation
is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part pow-
ers up again. Writes to WEL bit do not cause a non-vol-
atile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware when the device
powers up after having lost all power to the device. The
bit is set regardless of whether V
CC
or V
BACK
is applied
first. The loss of one or the other supplies does not
result in setting the RTCF bit. The first valid write to the
RTC (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
Unused Bits:
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output during
a SR read will contain zeros in these bit locations.
Addr 7 6 5 4 3 2 1 0
003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF
Default 0 0 0 0 0 0 0 0
X1243
6
CONTROL REGISTERS
Block Protect Bits - BP2, BP1, BP0 - (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write
to a protected block of memory is ignored. The block
protect bits will prevent write operations to one of eight
segments of the array. The partitions are described in
Table 3.
Table 3. Block Protect Bits
Interrupt Control Bits (AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output. The interrupt output is enabled when either bit is
set to ‘1’. Two volatile bits (AL1 and AL0), associated
with these alarms, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the alarm interrupts are enabled. The AL1
and AL0 bits are reset by the falling edge of the 8th
clock of a read of the register containing the bits.
In an alternative mode (called pulsed interrupt mode),
controlled by an interrupt mode (IM) bit, the alarm 0
setting provides an output pulse on IRQ each time the
alarm matches the RTC. In this case the AL0 bit is not
used. Alarm 1 works as before (i.e. the AL1 bit is set
when an alarm occurs), but it is necessary to poll the sta-
tus register to determine whether a match has occurred.
This read operation is necessary to reset the AL1 flag.
Normal Mode (IM bit =0)
A match of the RTC and the contents of the alarm 0
registers automatically sets the AL0 bit. If the AL0E bit
is also set, the output IRQ signal goes active (LOW). If
the AL0E bit is not set, the AL0 bit is set, but the IRQ
signal remains unchanged.
A match of the RTC and the contents of the alarm 1
registers automatically sets the AL1 bit. If the AL1E bit
is also set, the output IRQ signal goes active (LOW). If
the AL1E bit is not set, the AL1 bit is set, but the IRQ
signal remains unchanged.
Reading the status register, containing the AL0 and
AL1 bits, resets the bits. The bits do not reset until the
falling edge of the 8th output clock of the status regis-
ter containing the Alarm bits. When the bits reset, the
output IRQ signal returns to the inactive state.
Pulsed Interrupt Mode (IM bit =1)
In this mode, the alarm interrupt enable bits (AL0E and
AL1E) are not used. Alarm 1 operates as before, so a
match of the RTC and Alarm 1 sets the AL1 bit. Since
the interrupt enable bits have no function, it is neces-
sary for the host processor to poll the AL1 bit to deter-
mine if an alarm has occurred.
Alarm 0 provides an output response. In this case,
when the RTC matches the Alarm 0 registers, the out-
put IRQ pulses one time. This pulse can be used to
control some outside circuit or event, without the need
for a local processor. The duration of the pulse is 1024
cycles of the 32.748kHz oscillator. All alarm 0 enable
options are available, so this becomes a very flexible
long term repeat trigger.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
—Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
—Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
—Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
BP2
BP1
BP0
Protected Addresses
X1243 Array Lock
0 0 0 None None
0 0 1 600h - 7FFh Upper 1/4
0 1 0 400h - 7FFh Upper 1/2
0 1 1 000h - 7FFh Full Array
1 0 0 000h - 03Fh First Page
1 0 1 000h - 07Fh First 2 pgs
1 1 0 000h - 0FFh First 4 pgs
1 1 1 000h - 1FFh First 8 Pgs
X1243
7
initiate another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
—Writing all zeros to the status register resets both
the WEL and RWEL bits.
—A read operation occurring between any of the pre-
vious operations will not interrupt the register write
operation.
—The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable Data Change Data Stable
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 4.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus Refer to
Figure 4.
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start Stop
X1243
8
Figure 5. Acknowledge Response From Receiver
SCL from Master
Data Output from
Transmitter
Data Output
from Receiver
81 9
Start Acknowledge
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
—The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
—All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
—The 2nd Data Byte of a Register Write Operation
(when only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
Slave Address Byte and the Word Address Bytes. This
gives the master access to any one of the words in the
array or CCR. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status regis-
ter in preceding operations to enable the write opera-
tion. See “Writing to the Clock/Control Registers” on
page 6.) Upon receipt of each address byte, the
X1243 responds with an acknowledge. After receiving
both address bytes the X1243 awaits the eight bits of
data. After receiving the 8 data bits, the X1243 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X1243 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 6.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1243 will not initiate an internal
write cycle, and will continue to ACK commands.
X1243
9
Page Write
The X1243 has a page write operation. It is initiated in
the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit up to 63
more bytes
to the memory array and up to 7 more bytes to the
clock/control registers. (Note: Prior to writing to the
CCR, the master must write a 02h, then 06h to the sta-
tus register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Reg-
isters” on page 6.)
After the receipt of each byte, the X1243 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
Figure 6. Byte Write Sequence
Figure 7. Writing
30
bytes to a
64
-byte page starting at adress
40
.
Figure 8. Page Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address Word
Address 1
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0A
C
K
Word
Address 0
1111 00000
address
address
40
23 bytes
63
7 bytes
address
= 6
address pointer
ends here
Addr = 7
Word
Address 0
S
t
a
r
t
S
t
o
p
Slave
Address Word
Address 1 Data
(n)
A
C
K
A
C
KA
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1 < n < 64)
111100000
X1243
10
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte
at a time.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the device to begin
the non-volatile write cycle. As with the byte write
operation, all inputs are disabled until completion of
the internal write cycle. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The disabling of the inputs during non-volatile write
cycles can be used to take advantage of the typical
5mS write cycle time. Once the stop condition is
issued to indicate the end of the master’s byte load
operation, the device initiates the internal non-volatile
write cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start con-
dition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the non-
volatile write cycle then no ACK will be returned. If the
device has completed the write operation, an ACK will
be returned and the host can then proceed with the read
or write operation. Refer to the flow chart in Table 9.
READ OPERATIONS
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read can be initiated immediately after the
power on reset to download the contents of memory
starting at the first location.
Figure 9. Acknowledge Polling Sequence
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 10
for the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
ACK
returned?
Issue Slave
Address Byte
(Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Issue STOP
NO
Continue normal
Read or Write
command
sequence
PROCEED
YES
nonvolatile write
Cycle complete.
Continue command
sequence?
X1243
11
Figure 10. Current Address Read Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
11111
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 11 for the address,
acknowledge, and data transfer sequence.
In a similar operation, called “Set Current Address,”
the device sets the address if a stop is issued instead of
the second start shown in Figure 11. The X1243 then
goes into standby mode after the stop and all bus activity
will be ignored until a start is detected. This operation
loads the new address into the address counter. The next
Current Address Read operation will read from the
newly loaded address. This operation could be useful
if the master knows the next address it needs to read,
but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory
contents to be serially read during one operation. At
the end of the address space the counter “rolls over” to
the start of the address space and the device continues
to output data for each acknowledge received. Refer
to Figure 12 for the acknowledge and data transfer
sequence.
Figure 11. Random Address Read Sequence
0
Slave
Address Word
Address 1
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
A
C
K
Word
Address 0
1111 00000 1 1111
X1243
12
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to the EEPROM array or
to the CCR. Slave bits ‘1010’ access the EEPROM
array. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 12.
After loading the entire Slave Address Byte from the
SDA bus, the device compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master device must supply the 2 Word
Address Bytes.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be ‘1010111x’ in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be ‘1101111x’
in both places.
Figure 12. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
X1243
13
Figure 13. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Slave Address Byte
Byte 0
D7 D6 D5 D2D4 D3 D1 D0
A0A7 A2A4 A3 A1
Data Byte
Byte 3
A6 A5
0 0 0 A10 A9 A80
1
10
11
01
0
11R/W
1
Device Identifier
Array
CCR
0High Order Word Address
Byte 1
Low Order Word Address
Byte 2
X1243
14
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias.................. -65˚C to +135˚C
Storage Temperature....................... -65˚C to +150˚C
Voltage on any pin with respect to ground-1.0V to 7.0V
DC Output Current.............................................5 mA
Lead Temperature (Soldering, 10 Seconds).... 300˚C
Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and the functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
DC OPERATING CHARACTERISTICS Temperature = -40°c to +85°c, unless otherwise stated.)
Notes:
1: The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
2: Periodically sampled and not 100% tested.
Symbol Parameter Min Typ Max Unit Notes
Vcc Main Power Supply 2.7 5.5 V
VBACK Backup Power Supply 1.8 5.5 V
VCB Switch to Backup Supply VCC =V
BACK -0.2 VBACK -0.1 V 2:
VBC Switch to Main Supply VCC =V
BACK VBACK +0.1 2:
ICC1 Supply Current VCC = 2.7V 1.2 µA 3:, 5:, 10:
VCC = 5.5V 1.7 µA
ICC2 Supply Current
(External crystal network) VCC = 2.7V 3.8 5 2:, 3:, 5:, 11:
VCC = 5.5V 7.5 15 µA
ICC3 Program Supply Current
(non-volatile) VCC = 2.7V 1.5 mA 1:, 3:, 5:, 10:
VCC = 5.5V 3.0 mA
IBACK1 Timekeeping Current VBACK = 1.8V 1.0 µA 2:, 4:, 6:, 10:
VBACK = 5.5V 1.5 µA
IBACK2 Timekeeping Current
(External crystal network) VCC= 1.8V 1.6 3 µA 2:, 4:, 6:, 11:
VCC = 5.5V 7.5 15 µA
ILI Input Leakage Current 10 µA7:
ILO Output Leakage Current 10 µA7:
VIL Input LOW Voltage -0.5 VCC x 0.3 or
VBACK x 0.3 V 2:, 9:
VIH Input HIGH Voltage VCC x 0.7 or
VBACK x 0.7 VCC + 0.5
VBACK + 0.5 V 2:, 9:
VOL Output LOW Voltage 2.7V 0.4 V 8:
5.5V 0.4
X1243
15
3: VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz, SDA = Open
4: VCC = 0V.
5: VBACK= 0V.
6: VSDA=VSCL=VBACK, Others=GND or VBACK
7: VSDA = GND to VCC, VCLK = GND or VCC
8: IOL = 3.0mA at 5V, 1.5mA at 1.8V
9: Threshold voltages based on the higher of Vcc or Vback.
10: Driven by external 32.768KHz square wave oscillator on X1, X2 open.
11: Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
Capacitance (TA = 25˚C, f = 1.0 MHz, VCC = 5V)
1. This parameter is periodically sampled and not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
Symbol Parameter Max Units Test Conditions
COUT (1) Output Capacitance (SDA, IRQ) 8pF VOUT = 0V
CIN (1) Input Capacitance (SCL) 6pF VIN = 0V
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times 10ns
Input and Output Timing
Levels VCC x 0.5
Output Load Standard Output Load
Equivalent AC Output Load Circuit for VCC = 5V
Figure 14. Standard Output Load for testing the
device with VCC = 5.0V
SDA.
IRQ
1533Ω
100pF
5.0V
For V OL= 0.4V
and IOL = 3 mA
X1243
16
AC Specifications - TA = -40˚C to +85˚C, VCC = +2.7V to +5.5V, unless otherwise specified.
1. This parameter is periodically sampled and not 100% tested.
2. Cb = total capacitance of one bus line in pF.
Timing Diagrams
Bus Timing
Symbol Parameter 400kHz Option
Min Max Units
fSCL SCL Clock Frequency 0 400 KHz
tIN(1) Pulse width Suppression Time at inputs 50 nS
tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µS
tBUF Time the bus must be free before a new transmission
can start 1.3 µS
tLOW Clock LOW Time 1.3 µS
tHIGH Clock HIGH Time 0.6 µS
tSU:STA Start Condition Setup Time 0.6 µS
tHD:STA Start Condition Hold Time 0.6 µS
tSU:DAT Data In Setup Time 100 nS
tHD:DAT Data In Hold Time 0 µS
tSU:STO Stop Condition Setup Time 0.6 µS
tDH Data Output Hold Time 50 nS
tR(1) SDA and SCL Rise Time 20 +.1Cb(2) 300 nS
tF(1) SDA and SCL Fall Time 20 +.1Cb(2) 300 nS
Cb Capacitive load for each bus line 400 pF
tSU:STO
tDH
tHIGH
tSU:STA tHD:STA tHD:DAT
tSU:DAT
SCL
SDA IN
SDA OUT
tFtLOW
tBUF
tAA
tR
X1243
17
Write Cycle Timing
Power Up Timing
1. Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are peri-
odically sampled and not 100% tested.
Nonvolatile Write Cycle Timing
1. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile
write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is
used.
Symbol Parameter Min. Max. Units
tPUR(1) Time from Power Up to Read 1 mS
tPUW(1) Time from Power Up to Write 5 mS
Symbol Parameter Min. Typ.(1) Max. Units
tWC(1) Write Cycle Time 5 10 mS
SCL
SDA
tWC
8th bit of last byte ACK
Stop
Condition Start
Condition
X1243
18
ORDERING INFORMATION
Part Mark Information
Vcc Range Package Operating
Temperature Range
PART NUMBER
16Kb EEPROM
RESET (LOW)
2.7-5.5V 8L SOIC 0oC - 70oCX1243S8
-40oC - 85oCX1243S8I
8L TSSOP 0oC - 70oCX1243V8
8-Lead TSSOP
EYWW
XXXXX
X1243 = 2.7 to 5.5V, 0 to +70°C
1243I = 2.7 to 5.5V, -40 to +85°C
8-Lead SOIC
X1243 X
XX Blank = 8-Lead SOIC
Blank = 2.7 to 5.5V, 0 to +70°C
I = 2.7 to 5.5V, -40 to +85°C
LIMITED W ARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U .S . PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. F oreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up f eatures to pre v ent such an occurence.
Xicor's products are not authorized for use in critical components in lif e support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or
sustain life, and whose failure to perform, when properly used in accordance with instr uctions for use provided in the labeling, can be
reasonably e xpected to result in a significant injury to the user .
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably e xpected to cause
the failure of the life support device or system, or to aff ect its saf ety or eff ectiv eness.
