1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
IN1IN2
D1D2
S1S2
V– V+
GND VL
S4S3
D4D3
IN4IN3
Dual-In-Line
and SOIC
DG611
Top View
S1S2
V– V+
NC NC
GND VL
S4S3
LCC
NC IN3D3
D4IN4
NC IN2D2
D1IN1
Key
910111213
4
5
6
7
8
1231920
14
15
16
17
18
DG611
DG611/612/613
Vishay Siliconix
Document Number: 70057
S-00399—Rev. G, 13-Sep-99 www.vishay.com FaxBack 408-970-5600
4-1
High-Speed, Low-Glitch D/CMOS Analog Switches
Fast Switching— tON: 12 ns
Low Charge Injection: 2 pC
Wide Bandwidth: 500 MHz
5-V CMOS Logic Compatible
Low rDS(on): 18
Low Quiescent Power : 1.2 nW
Single Supply Operation
Improved Data Throughput
Minimal Switching Transients
Improved System Performance
Easily Interfaced
Low Insertion Loss
Minimal Power Consumption
Fast Sample-and-Holds
Synchronous Demodulators
Pixel-Rate Video Switching
Disk/Tape Drives
DAC Deglitching
Switched Capacitor Filters
GaAs FET Drivers
Satellite Receivers
The DG611/612/613 feature high-speed low-capacitance
lateral DMOS switches. Charge injection has been minimized
to optimize performance in fast sample-and-hold applications.
Each switch conducts equally well in both directions when on
and blocks up to 16 Vp-p when off. Capacitances have been
minimized to ensure fast switching and low-glitch energy. To
achieve such fast and clean switching performance, the
DG611/612/613 are built on the Vishay Siliconix proprietary
D/CMOS process. This process combines n-channel DMOS
switching FETs with low-power CMOS control logic and
drivers. An epitaxial layer prevents latchup.
The DG611 and DG612 differ only in that they respond to
opposite logic levels. The versatile DG613 has two normally
open and two normally closed switches. It can be given various
configurations, including four SPST, two SPDT, one DPDT.
For additional information see Applications Note AN207
(FaxBack number 70605).
Four SPST Switches per Package
Logic DG611 DG612
0 ON OFF
1 OFF ON
Logic “0” 1 V
Logic “1” 4 V
IN1IN2
D1D2
S1S2
V– V+
GND VL
S4S3
D4D3
IN4IN3
Dual-In-Line
and SOIC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
DG613
NC
S3
NC
D4
NC
IN1
VL
IN4
S2
Key
S4
IN3
D1
Top View
D3
V–
NC LCC
IN2
V+
9
GND
10 11 12 13
4
D2
5
6
7
8
123 1920
14
15
16
17
18
S1
DG613
DG611/612/613
Vishay Siliconix
www.vishay.com S FaxBack 408-970-5600
4-2 Document Number: 70057
S-00399—Rev. G, 13-Sep-99
Four SPST Switches per Package
Logic SW1, SW4SW2, SW3
0 OFF ON
1 ON OFF
Logic “0” 1 V
Logic “1” 4 V
Temp Range Package Part Number
DG611/612
40 85 C
16
-
Pin Plastic DIP
DG611DJ
–
40 to 85
_
C
16
-
Pin
Plastic
DIP
DG612DJ
–
40
to
85_C
16
-
Pin Narrow SOIC
DG611DY
16
-
Pin
Narrow
SOIC
DG612DY
55 125 C
16
-
Pin CerDIP
DG61 1AK/883, 5962-9325501MEA
–
55 to 125
_
C
16
-
Pin
CerDIP
DG612AK/883, 5962-9325502MEA
–
55
to
125_C
LCC
-
20
DG61 1AZ/883, 5962-9325501M2A
LCC
-
20
DG612AZ/883, 5962-9325502M2A
DG613
–
40 to 85
_
C
16-Pin Plastic DIP DG613DJ
–
40
to
85_C
16-Pin Narrow SOIC DG613DY
–
55 to 125
_
C
16-Pin CerDIP DG613AK/883, 5962-9325503MEA
–
55
to
125_C
LCC-20 DG613AZ/883, 5962-9325503M2A
V+ to V– –0.3 V to 21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V+ to GND –0.3 V to 21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V– to GND –19 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL to GND –1 V to (V+) + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
VINa(V–) –1 V to (V+) + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
VS, VDa(V–) –0.3 V to (V–) + 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
Continuous Current (Any Terminal) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Current, S or D (Pulsed at 1 ms, 10% Duty Cycle) 100 mA. . . . . . . . . . . . .
Storage Temperature: CerDIP –65 to 150_C. . . . . . . . . . . . . . . . . . . . .
Plastic –65 to 125_C. . . . . . . . . . . . . . . . . . . . . .
Power Dissipation (Package)b
16-Pin Plastic DIPc470 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Narrow SOICd600 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin CerDIPe900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin LCCe900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/_C above 75_C
d. Derate 7.6 mW/_C above 75_C
e. Derate 12 mW/_C above 75_C
V+ 5 V to 21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V– –10 V to 0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL4 V to V+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIN 0 V to VL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VANALOG V– to (V+) – 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG611/612/613
Vishay Siliconix
Document Number: 70057
S-00399—Rev. G, 13-Sep-99 www.vishay.com S FaxBack 408-970-5600
4-3
P
Sbl
Test Conditions
Unless Otherwise Specified
V15VV 3V
Tb
Tc
A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Ui
Parameter Symbol V+ = 15 V, V– = –3 V
VL = 5 V, VIN = 4 V, 1 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG V– = –5 V, V+ = 12 V Full –5 7 –5 7 V
Switch On-Resistance rDS(on)
IS
=
–
1 mA, VD
=
0 V
Room
Full 18 45
60 45
60
W
Resistance
Match Bet Ch. DrDS(on)
I
S = –
1
mA
,
V
D =
0
V
Room 2
W
Source Off Leakage IS(off) VS = 0 V, VD = 10 V Room
Hot 0.001
–0.25
–20 0.25
20 –0.25
–20 0.25
20
A
Drain Off
Leakage Current ID(off) VS = 10 V, VD = 0 V Room
Hot 0.001 –0.25
–20 0.25
20 –0.25
–20 0.25
20 nA
Switch On
Leakage Current ID(on) VS = VD = 0 V Room
Hot 0.001 –0.4
–40 0.4
40 –0.4
–40 0.4
40
Digital Control
Input Voltage High VIH Full 4 4
V
Input V oltage Low VIL Full 1 1
V
Input Current IIN Room
Hot 0.005 –1
–20 1
20 –1
–20 1
20 mA
Input Capacitance CIN Room 5 pF
Dynamic Characteristics
Off State Input Capacitance CS(off) VS = 0 V Room 3
F
Off State Output Capacitance CD(off) VD = 0 V Room 2 pF
On State Input Capacitance CS(on) VS = VD = 0 V Room 10
Bandwidth BW RL = 50 WRoom 500 MHz
T urn-On TimeetON RL = 300 W, CL = 3 pF, VS = 2 V
STtCiitFi 2
Room 12 25 25
T urn-Off T ime etOFF
L,Lp, S
See Test Circuit, Figure 2 Room 8 20 20
T urn-On Time tON RL = 300 W, CL = 75 pF
VS
=
2 V
Room
Full 19 35
50 35
50 ns
T urn-Off T ime tOFF
V
S =
2
V
See Test Circuit, Figure 2 Room
Full 16 25
35 25
35
Charge InjectioneQ CL = 1 nF, VS= 0 V Room 4
pC
Ch. Injection Changee, gDQCL = 1 nF, VS 3 V Room 3 4 4 pC
Off IsolationeOIRR RIN = 50 W, RL = 50 W
f = 5 MHz Room 74 dB
CrosstalkeXTALK RIN = 10 W, RL = 50 W, f = 5 MHz Room 87
Power Supplies
Positive
Supply Curent I+
V0V5V
Room
Full 0.005 1
51
5
A
Negative
Supply Current I–
VIN
=
0 V or 5 V
Room
Full –0.005 –1
–5 –1
–5
mA
Logic Supply Current IL
V
IN =
0
V
or
5
V
Room
Full 0.005 1
51
5
m
A
Ground Current IGND Room
Full –0.005 –1
–5 –1
–5
DG611/612/613
Vishay Siliconix
www.vishay.com S FaxBack 408-970-5600
4-4 Document Number: 70057
S-00399—Rev. G, 13-Sep-99
P
Sbl
Test Conditions
Unless Otherwise Specified
Tb
Tc
A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Ui
Parameter Symbol V+ = 15 V, V– = –3 V
VL = 5 V, VIN = 4 V, 1 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full 0 7 0 7 V
Switch On-Resistance rDS(on) IS = –1 mA, VD = 1 V Room 25 60 60 W
Dynamic Characteristics
Turn-On TimeetON RL = 300 W, CL = 3 pF, VS = 2 V
STtCiitFi 2
Room 15 30 30
ns
T urn-Off T ime etOFF
L,Lp, S
See Test Circuit, Figure 2 Room 10 25 25
ns
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. T ypical values are for DESIGN AID ONL Y, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. DQ = Q at VS = 3 V – Q at VS = –3 V.
DG611/612/613
Vishay Siliconix
Document Number: 70057
S-00399—Rev. G, 13-Sep-99 www.vishay.com S FaxBack 408-970-5600
4-5
_
rDS(on)
– Drain-Source On-Resistance (
–4 –2 0 2 4 6 8 10 12–5
400
350
300
250
200
150
100
50
0
rDS(on) vs. VD and Power Supply Voltages
VD – Drain Voltage (V)
V+ = 5 V
V– = –5 V
V+ = 12 V
V– = –5 V
V+ = 15 V
V– = –3 V
IS = –1 mA
rDS(on)
– Drain-Source On-Resistance (
–4–2024681012
400
350
300
250
200
150
100
50
0
rDS(on) vs. VD and Temperature
VD – Drain Voltage (V)
25_C
V+ = 15 V
V– = –3 V
IS = –1 mA
125_C
–55_C
–4 –2 0 2 4 6 8 10
3
2
1
0
–1
–2
–3
– Leakage Current (pA)
, I D
VD or VS – Drain or Source Voltage (V)
IS(off), ID(off)
ID(on)
V+ = 15 V
V– = –3 V
Leakage Current vs. Analog Voltage
IS
–55 0 125
Leakage Currents vs. Temperature
Temperature (_C)
–25 25 50 75 100
10 nA
0.1 pA
100 pA
10 pA
1 pA
IS(off), ID(off)
ID(on)
1 nA
– Leakage (A)I , I
S(off) D(off)
0 5 10 15
6
5
4
3
2
1
0
Input Switching Threshold vs. VL
VL – Logic Supply Voltage (V)
V+ = 15 V
V– = –3 V
VTH– Logic Input Voltage (V)
16
14
12
10
8
6
4
2
0
24
22
20
18
–55 –35 –15 5 25 45 65 85 105 125
V+ = 15 V
V– = –3 V
RL = 300
CL = 10 pF
Switching Times vs. Temperature
tON
tOFF
T ime (ns)
Temperature (_C)
)
)
DG611/612/613
Vishay Siliconix
www.vishay.com S FaxBack 408-970-5600
4-6 Document Number: 70057
S-00399—Rev. G, 13-Sep-99
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Charge (pC)
VANALOG – Analog V oltage (V)
20
10
0
–10
–20–3–2–1012345678910
Charge Injection vs. Analog Voltage
Qd
Qs
V+ = 15 V
V– = –3 V
1 10 100
–20
–40
–60
–80
–100
–120
f – Frequency (MHz)
Crosstalk and Off Isolation vs. Frequency
V+ = 15 V
V– = –3 V
(dB)
Crosstalk
Off Isolation
Insertion Loss (dB)
1 10 100 1000
–24
–20
–16
–12
–8
–4
0
f – Frequency (MHz)
RL = 50
–3 dB Bandwidth/Insertion Loss vs. Frequency
–3 dB Point
Supply Current (mA)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5 1 k 100 k 100 k 1 M 10 M
V+ = 15 V
V– = –3 V
VL = 5 V
CX = 0, 5 V
Supply Currents vs. Switching Frequency
f – Frequency (Hz)
I+
IL
I–
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
VL
V+
V–
S
D
DMOS Switch
Level
Translator
Input
Logic
INX
FIGURE 1.
Driver
DG611/612/613
Vishay Siliconix
Document Number: 70057
S-00399—Rev. G, 13-Sep-99 www.vishay.com FaxBack 408-970-5600
4-7
S1
D2
S2
VS
1 V, 4 V VO
IN2
Rg = 50
1 V, 4 V
XTALK Isolation = 20 log VS
VL
VO
V+
IN150
C = RF bypass
RL
D1
–3 V
GND V–
NC
C
+15 V
C+5 V C
CL (includes fixture and stray capacitance)
VL
RL
RL + rDS(on)
VO = VS
VO
2 V
V+
V–
IN
V–
S
GND RL
300
D
CL
+15 V+5 V
FIGURE 2. Switching T ime
50%
20%
90%
tON tOFF
Logic Input
0 V
5 V
VS= 2 V
0 V
Switch Output
tr < 10 ns
tf < 10 ns
FIGURE 3. Charge Injection
CL
1 nF
D
RgVO
V+
S
V–
5 V IN
VL
Vg
–3 V
GND
+15 V+5 V
FIGURE 4. Crosstalk
High-Speed Sample-and-Hold
In a fast sample-and-hold application, the analog switch
characteristics are critical. A fast switch reduces aperture
uncertainty. A low charge injection eliminates offset (step)
errors. A low leakage reduces droop errors. The CLC111, a fast
input buffer, helps to shorten acquisition and settling times. A
low leakage, low dielectric absorption hold capacitor must
be used. Polycarbonate, polystyrene and polypropylene
are good choices. The JFET output buffer reduces droop
due to its low input bias current. (See Figure 5.)
Pixel-Rate Switch
Windows, picture-in-picture, title overlays are economically
generated using a high-speed analog switch such as the
DG613. For this application the two video sources must be
sync locked. The glitch-less analog switch eliminates halos.
(See Figure 6.)
GaAs FET Drivers
Figure 7 illustrates a high-speed GaAs FET driver . To turn the
GaAs FET on 0 V are applied to its gate via S1, whereas to turn
it off, –8 V are applied via S2. This high-speed, low-power
driver is especially suited for applications that require a large
number of RF switches, such as phased array radars.
DG611/612/613
Vishay Siliconix
www.vishay.com FaxBack 408-970-5600
4-8 Document Number: 70057
S-00399—Rev. G, 13-Sep-99
CLC111
75
+
–
LF356
1/4 DG611
5 V Control
Analog
Input
Input Buffer
S
IN
D
Output Buffer
5 V Output
to A/D
+5 V +12 V
–5 V
CHOLD
650 pF Polystyrene
FIGURE 5. High-Speed Sample-and-Hold
+
–
CLC410
75
1/2 DG613
Background D
Output Buf fer Composite
Output
+5 V +12 V
–5 V
75
Titles
5 V Control
75
250
1/2 CLC114
250
FIGURE 6. A Pixel-Rate Switch Creates T itle Overlays
1/2 DG613
D1
+5 V
–8 V
D2
S1
S2
IN1
IN2
GND V–
GaAs
RF
IN RF
OUT
VLV+
FIGURE 7. A High-Speed GaAs FET Driver that Saves Power
5 V
