PRELIMINARY CY7C1020D 512K (32K x 16) Static RAM Features automatic power-down feature that significantly reduces power consumption when deselected. * Pin- and function-compatible with CY7C1020B * High speed -- tAA = 10 ns * CMOS for optimum speed/power * Low active power -- ICC = 60 mA @ 10ns * Low CMOS Standby Power -- ISB2 = 1.2 mA ("L" Version only) * Automatic power-down when deselected * Data Retention at 2.0V * Independent control of upper and lower bits * Available in 44-pin TSOP II and 400-mil SOJ Pb-Free Packages Functional Description[1] The CY7C1020D is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020D is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ Pb-Free packages. Logic Block Diagram Pin Configuration SOJ / TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K x 16 RAM Array I/O0-I/O7 I/O8-I/O15 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A4 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05463 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 11, 2005 CY7C1020D PRELIMINARY Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) CY7C1020D-10 10 60 3 1.2 Com'l / Ind'l Com'l / Ind'l Com'l / Ind'l L-Version Only Maximum Ratings CY7C1020D-12 12 50 3 1.2 Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[Notes:]-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................-0.5V to VCC+0.5V DC Input Voltage[2] ...................................-0.5V to VCC+0.5V Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200mA Operating Range Ambient Temperature Range Commercial Industrial VCC 0C to +70C 5V 10% -40C to +85C 5V 10% Electrical Characteristics Over the Operating Range Parameter 7C1020D-10 Test Conditions Description VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage Min. 7C1020D-12 Max. Min. 2.4 VCC = Min., IOL = 8.0 mA 2.4 0.4 Voltage[2] Max. Unit V 0.4 V 2.0 VCC + 0.3V 2.0 VCC + 0.3V V -0.5 0.8 -0.5 0.8 V VIL Input LOW IIX Input Load Current GND < VI < VCC -1 +1 -1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled -1 +1 -1 +1 A IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND -300 -300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 60 50 mA ISB1 Automatic CE Power-Down Current--TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 10 10 mA ISB2 Automatic CE Power-Down Current--CMOS Inputs Non-L, Com'l / Ind'l Max. VCC, CE > L-Version Only VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 3 3 mA 1.2 1.2 mA Capacitance[4] Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V COUT Output Capacitance Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: 38-05463 Rev. *C Max. Unit 8 pF 8 pF Page 2 of 10 CY7C1020D PRELIMINARY Thermal Resistance[4] Parameter All - Packages Unit JA Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board (Junction to Ambient)[4] Description Test Conditions TBD C/W JC Thermal Resistance (Junction to Case)[4] TBD C/W AC Test Loads and Waveforms 10-ns Device 12 -ns Devices Z = 50 R 480 5V OUTPUT OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* R2 255 30 pF 1.5V INCLUDING JIG AND SCOPE (b) (a) High-Z Characteristics ALL INPUT PULSES 3.0V 90% 5V 10% 10% GND R 480 90% OUTPUT R2 255 5 pF Rise Time: 1 V/ns Fall Time: 1 V/ns INCLUDING JIG AND SCOPE (c) 167 OUTPUT Equivalent to: THEVENIN EQUIVALENT 1.73V Switching Characteristics[5] Over the Operating Range 7C1020D-10 Parameter Description Min. Max. 7C1020D-12 Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 100 100 s tRC Read Cycle Time 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns Z[7] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[7, 8] tLZCE CE LOW to Low Z[7] tHZCE CE HIGH to High 10 3 12 3 0 0 Z[7, 8] ns 0 5 ns 6 3 5 0 ns ns ns 6 0 ns tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 10 12 ns tDBE Byte Enable to Data Valid 5 6 ns tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z 0 ns 0 5 ns 6 ns Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. Document #: 38-05463 Rev. *C Page 3 of 10 CY7C1020D PRELIMINARY Switching Characteristics[5] Over the Operating Range 7C1020D-10 Parameter Write Description Min. 7C1020D-12 Max. Min. Max. Unit Cycle[9] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 7 9 ns tAW Address Set-Up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 6 6 ns tHD Data Hold from Write End 0 0 ns 3 3 ns WE HIGH to Low Z[7] tHZWE WE LOW to High Z[7, 8] tBW Byte Enable to End of Write tLZWE 6 6 7 ns 8 ns Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [4] Conditions Min. VCC = VDR = 2.0V, CE > VCC - 0.3V, Non-L, Com'l / Ind'l VIN > VCC - 0.3V or L-Version Only VIN < 0.3V Chip Deselect to Data Retention Time tR[10] Operation Recovery Time Max. 2.0 Unit V 3 mA 1.2 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR VDR > 2V 4.5V tR CE Notes: 9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. Document #: 38-05463 Rev. *C Page 4 of 10 CY7C1020D PRELIMINARY Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05463 Rev. *C Page 5 of 10 CY7C1020D PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05463 Rev. *C Page 6 of 10 CY7C1020D PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled) OE LOW tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE H X X X X High Z High Z Power-Down Standby (ISB) L L H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L X WE L BLE BHE I/O0-I/O7 I/O8-I/O15 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code Package Name Package Type Operating Range CY7C1020D-10VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial CY7C1020D-10ZXC V34 44-Lead TSOP Type II (Pb-Free) CY7C1020D-10VXI Z44 44-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial CY7C1020D-10ZXI Z44 44-Lead TSOP Type II (Pb-Free) CY7C1020D-12VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial CY7C1020D-12ZXC V34 44-Lead TSOP Type II (Pb-Free) CY7C1020D-12VXI Z44 44-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial CY7C1020D-12ZXI Z44 44-Lead TSOP Type II (Pb-Free) Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05463 Rev. *C Page 7 of 10 PRELIMINARY CY7C1020D Package Diagrams 44-Lead (400-Mil) Molded SOJ V34 51-85082-B Document #: 38-05463 Rev. *C Page 8 of 10 PRELIMINARY CY7C1020D Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05463 Rev. *C Page 9 of 10 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1020D Document History Page Document Title: CY7C1020D 512K (32K x 16) Static RAM (Preliminary) Document #: 38-05463 REV. ECN NO. Orig. of Issue Date Change Description of Change ** 201560 See ECN SWI Advance Datasheet for C9 IPP *A 233695 See ECN RKF 1) DC parameters modified as per EROS (Spec # 01-0216) 2) Pb-free Offering in the `Ordering Information' *B 263769 See ECN RKF 1) Corrected Pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4 2) Changed I/O1 - I/O16 to I/O0 - I/O15 on the Pin-out diagram 3) Added Tpower Spec in Switching Characteristics Table 4) Added Data Retention Characteristics Table and Waveforms 5) Shaded `Ordering Information' *C 307594 See ECN RKF Reduced Speed bins to -10, -12 and -15 ns Document #: 38-05463 Rev. *C Page 10 of 10