PCF8563TD-T - NXP Semiconductors / Philips Semiconductors

1. General description

The PCF8563 is a CMOS real-time clock/calendar optimized for low power consumption.

A programmable clock output, interrupt output and voltage-low detector are also provided.

All addresses and data are transferred serially via a two-line bidirectional I2C-bus.

Maximum bus speed is 400 kbit/s. The built-in word address register is incremented

automatically after each written or read data byte.

2. Features

nProvides year, month, day, weekday, hours, minutes and seconds based on

32.768 kHz quartz crystal

nCentury ﬂag

nClock operating voltage: 1.8 V to 5.5 V

nLow backup current; typical 0.25 µA at VDD = 3.0 V and Tamb =25°C

n400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V)

nProgrammable clock output for peripheral devices (32.768 kHz, 1024 Hz, 32 Hz and

1 Hz)

nAlarm and timer functions

nIntegrated oscillator capacitor

nInternal power-on reset

nI2C-bus slave address: read A3h and write A2h

nOpen-drain interrupt pin

nElectroStatic Discharge (ESD) protection exceeds 2000 V Human Body Model (HBM)

per JESD22-A114, 200 V Machine Model (MM) per JESD22-A115 and 2000 V

Charged Device Model (CDM) per JESD22-C101

nLatch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

3. Applications

nMobile telephones

nPortable instruments

nElectronic metering

nBattery powered products

PCF8563

Real-time clock/calendar

Rev. 06 — 21 February 2008 Product data sheet

Product data sheet Rev. 06 — 21 February 2008 2 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

4. Ordering information

5. Block diagram

Table 1. Ordering information

Type number Topside

mark Package

Name Description Version

PCF8563P PCF8563P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1

PCF8563T 8563T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

PCF8563TS 8563 TSSOP8 plastic thin shrink small outline package; 8 leads; body width

3mm SOT505-1

PCF8563BS 8563S HVSON10 plastic thermal enhanced very thin small outline package;

no leads; 10 terminals; body 3 × 3 × 0.85 mm SOT650-1

Fig 1. Block diagram

001aah658

PCF8563

OSCILLATOR

32.768 kHz DIVIDER CLOCK OUT

INTERRUPT

CLKOUT

INT

MONITOR

POWER ON

RESET

WATCH

DOG

I2C-BUS

INTERFACE

OSCI

SCL

SDA

OSCO

VDD

VSS

TIMER FUNCTION

TIMER_CONTROL0E

TIMER0F

CONTROL

CONTROL_STATUS_100

CONTROL_STATUS_201

CLKOUT_CONTROL0D

TIME

VL_SECONDS02

MINUTES03

HOURS04

DAYS05

ALARM FUNCTION

MINUTE_ALARM09

HOUR_ALARM0A

DAY_ALARM0B

WEEKDAY_ALARM0C

WEEKDAYS06

CENTURY_MONTHS07

YEARS08

Product data sheet Rev. 06 — 21 February 2008 3 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

6. Pinning information

6.1 Pinning

Fig 2. Pin conﬁguration DIP8 Fig 3. Pin conﬁguration SO8

Fig 4. Pin conﬁguration TSSOP8 Fig 5. Pin conﬁguration HVSON10

Fig 6. Device diode protection diagram

PCF8563P

OSCI VDD

OSCO CLKOUT

INT SCL

VSS SDA

001aaf977

7PCF8563T

OSCI VDD

OSCO CLKOUT

INT SCL

VSS SDA

001aaf975

PCF8563TS

OSCI VDD

OSCO CLKOUT

INT SCL

VSS SDA

001aaf976

001aaf981

PCF8563BS

SDA

INT

VSS

SCL

n.c. CLKOUT

OSCO VDD

OSCI n.c.

Transparent top view

4 7

3 8

2 9

1 10

terminal 1

index area

mgr886

SDA

VSS

SCL

INT

CLKOUT

OSCO

VDD

OSCI

PCF8563

Product data sheet Rev. 06 — 21 February 2008 4 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

6.2 Pin description

7. Functional description

The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register,

an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which

provides the source clock for the Real-Time Clock/calender (RTC), a programmable clock

output, a timer, an alarm, a voltage-low detector and a 400 kHz I2C-bus interface.

All 16 registers are designed as addressable 8-bit parallel registers although not all bits

are implemented. The ﬁrst two registers (memory address 00h and 01h) are used as

control and/or status registers. The memory addresses 02h through 08h are used as

counters for the clock function (seconds up to years counters). Address locations 09h

through 0Ch contain alarm registers which deﬁne the conditions for an alarm.

Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control

and timer registers, respectively.

The seconds, minutes, hours, days, weekdays, months, years as well as the minute alarm,

hour alarm, day alarm and weekday alarm registers are all coded in Binary Coded

Decimal (BCD) format.

When one of the RTC registers is read the contents of all counters are frozen. Therefore,

faulty reading of the clock/calendar during a carry condition is prevented.

7.1 Alarm function modes

By clearing the MSB of one or more of the alarm registers (bit AE = Alarm Enable), the

corresponding alarm condition(s) will be active. In this way an alarm can be generated

from once per minute up to once per week. The alarm condition sets the Alarm Flag (AF).

The asserted AF can be used to generate an interrupt (on pin INT). The AF can only be

cleared by software.

Table 2. Pin description

Symbol Pin Description

DIP8, SO8, TSSOP8 HVSON10

OSCI 1 1 oscillator input

OSCO 2 2 oscillator output

n.c. - 3 not connected

INT 3 4 interrupt output (open-drain; active LOW)

VSS 4 5 ground

SDA 5 6 serial data input and output

SCL 6 7 serial clock input

CLKOUT 7 8 clock output, open-drain

VDD 8 9 positive supply voltage

n.c. - 10 not connected

Product data sheet Rev. 06 — 21 February 2008 5 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

7.2 Timer

The 8-bit countdown timer at address 0Fh is controlled by the timer control register at

address 0Eh. The timer control register determines one of 4 source clock frequencies for

the timer (4096 Hz, 64 Hz, 1 Hz, or 1⁄60 Hz), and enables or disables the timer. The timer

counts down from a software-loaded 8-bit binary value. At the end of every countdown,

the timer sets the Timer Flag (TF). The TF may only be cleared by software. The

asserted TF can be used to generate an interrupt (on pin INT). The interrupt may be

generated as a pulsed signal every countdown period or as a permanently active signal

which follows the state of TF. Bit TI_TP is used to control this mode selection. When

reading the timer, the current countdown value is returned.

7.3 Clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

CLKOUT control register at address 0Dh. Frequencies of 32.768 kHz (default), 1024 Hz,

32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock, input to

a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and

enabled at power-on. If disabled it becomes high-impedance.

7.4 Reset

The PCF8563 includes an internal reset circuit which is active whenever the oscillator is

stopped. In the reset state the I2C-bus logic is initialized and all registers are reset

according to Table 25.

7.5 Voltage-low detector

The PCF8563 has an on-chip voltage-low detector (see Figure 7). When VDD drops below

Vlow, bit VL in the seconds register is set to indicate that the integrity of the clock

information is no longer guaranteed. The VL ﬂag can only be cleared by software.

Bit VL is intended to detect the situation when VDD is decreasing slowly, for example under

battery operation. Should VDD reach Vlow before power is re-asserted then bit VL is set.

This will indicate that the time may be corrupted.

Fig 7. Voltage-low detection

VL set

normal power

operation

period of battery

operation

VDD

Vlow

mgr887

Product data sheet Rev. 06 — 21 February 2008 6 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

7.6 Register organization

7.6.1 Control_status_1 register

7.6.2 Control_status_2 register

Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer

countdown, TF is set to logic 1. These bits maintain their value until overwritten by

software. If both timer and alarm interrupts are required in the application, the source of

the interrupt can be determined by reading these bits. To prevent one ﬂag being

overwritten while clearing another a logic AND is performed during a write access.

Table 3. Formatted registers overview

Bit positions labelled as x are not relevant. Bit positions labelled with 0 should always be written with logic 0; if read they could

be either logic 0 or logic 1.

Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h control_status_1 TEST1 0 STOP 0 TESTC 0 0 0

01h control_status_2 0 0 0 TI_TP AF TF AIE TIE

02h VL_seconds VL <seconds 00 to 59 coded in BCD>

03h minutes x <minutes 00 to 59 coded in BCD>

04h hours x x <hours 00 to 23 coded in BCD>

05h days x x <days 01 to 31 coded in BCD>

06h weekdays xxxxx<weekdays 0 to 6 in BCD>

07h century_months C x x <months 01 to 12 coded in BCD>

08h years <years 00 to 99 coded in BCD>

09h minute_alarm AE <minute alarm 00 to 59 coded in BCD>

0Ah hour_alarm AE x <hour alarm 00 to 23 coded in BCD>

0Bh day_alarm AE x <day alarm 01 to 31 coded in BCD>

0Ch weekday_alarm AE xxxx<weekday alarm 0 to 6 in BCD>

0Dh CLKOUT_control FE xxxxxFD1FD0

0Eh timer_control TE xxxxxTD1TD0

0Fh timer <timer countdown value>

Table 4. Control_status_1 - Control and Status register 1 (address 00h) bit description

Bit Symbol Value Description

7 TEST1 0 Normal mode

1 EXT_CLK test mode

6 0 default value is logic 0

5 STOP 0 RTC source clock runs

1 all RTC divider chain ﬂip-ﬂops are asynchronously set to logic 0; the

RTC clock is stopped (CLKOUT at 32.768 kHz is still available)

4 0 default value is logic 0

3 TESTC 0 Power-on reset override facility is disabled; set to logic 0 for normal

operation

1 Power-on reset override may be enabled

2 to 0 0 default value is logic 0

Product data sheet Rev. 06 — 21 February 2008 7 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer stopped when n = 0.

7.6.3 Time and date registers

Table 5. Control_status_2 - Control and Status register 2 (address 01h) bit description

Bit Symbol Value Description

7 to 5 0 default value is logic 0

4 TI_TP 0 INT is active when TF is active (subject to the status of TIE)

1INT pulses active according to Table 6 (subject to the status of

TIE); note that if AF and AIE are active then INT will be

permanently active

3 AF 0 (read) alarm ﬂag inactive

1 (read) alarm ﬂag active

0 (write) alarm ﬂag is cleared

1 (write) alarm ﬂag remains unchanged

2 TF 0 (read) timer ﬂag inactive

1 (read) timer ﬂag active

0 (write) timer ﬂag is cleared

1 (write) timer ﬂag remains unchanged

1 AIE 0 alarm interrupt disabled

1 alarm interrupt enabled

0 TIE 0 timer interrupt disabled

1 timer interrupt enabled

Table 6. INT operation (bit TI_TP = 1)

Source clock (Hz) INT period (s)[1]

n=1

[2] n>1

[2]

4096 1⁄8192 1⁄4096

64 1⁄128 1⁄64

11⁄64 1⁄64

1⁄60 1⁄64 1⁄64

Table 7. VL_seconds - Validity and Seconds register (address 02h) bit description

Bit Symbol Value Description

7 VL 0 clock integrity is guaranteed

1 integrity of the clock information is no longer guaranteed

6 to 0 SECONDS[6:0] 00 to 59 the current seconds, coded in BCD format. Example:

seconds register contains x101 1001 = 59 seconds

Product data sheet Rev. 06 — 21 February 2008 8 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

[1] These bits may be re-assigned by the user.

[1] This bit may be re-assigned by the user.

Table 8. Minutes - Minutes register (address 03h) bit description

Bit Symbol Value Description

7 x not relevant

6 to 0 MINUTES[6:0] 00 to 59 the current minutes, coded in BCD format

Table 9. Hours - Hours register (address 04h) bit description

Bit Symbol Value Description

7 to 6 x not relevant

5 to 0 HOURS[5:0] 00 to 23 the current hours, coded in BCD format

Table 10. Days - Days register (address 05h) bit description

Bit Symbol Value Description

7 to 6 x not relevant

5 to 0 DAYS[5:0] 01 to 31 the current day, coded in BCD format[1]

Table 11. Weekdays - Weekdays register (address 06h) bit description

Bit Symbol Value Description

7 to 3 x not relevant

2to0

[1] WEEKDAYS[2:0] 0 to 6 the current weekday, coded in BCD format,

see Table 12.

Table 12. Weekday assignments

Weekday Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Sunday xxxxx000

Monday xxxxx001

Tuesday xxxxx010

Wednesday xxxxx011

Thursday xxxxx100

Friday xxxxx101

Saturday xxxxx110

Table 13. Century_months - Century and Months register (address 07h) bit description

Bit Symbol Value Description

[1] century; this bit is toggled when the years register

overﬂows from 99 to 00

0 indicates the century is 20xx

1 indicates the century is 19xx

6 to 5 x not relevant

4 to 0 MONTHS[4:0] 01 to 12 the current month, coded in BCD format, see Table 14

Product data sheet Rev. 06 — 21 February 2008 9 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

7.6.4 Alarm registers

When one or more of these registers are loaded with a valid minute, hour, day or weekday

and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be

compared with the current minute, hour, day and weekday. When all enabled comparisons

ﬁrst match, the Alarm Flag (AF) is set. AF will remain set until cleared by software.

Once AF has been cleared it will only be set again when the time increments to match the

alarm condition once more. Alarm registers which have their bit AE at logic 1 will be

ignored.

Table 14. Month assignments

Month Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January Cxx00001

February Cxx00010

March C x x 00011

April Cxx00100

May Cxx00101

June Cxx00110

July Cxx00111

August C x x 01000

September C x x 01001

October C x x 10000

November C x x 10001

December C x x 10010

Table 15. Years - Years register (address 08h) bit description

Bit Symbol Value Description

7 to 0 YEARS[7:0] 00 to 99 the current year, coded in BCD format

Table 16. Minute_alarm - Minute alarm register (address 09h) bit description

Bit Symbol Value Description

7 AE 0 minute alarm is enabled

1 minute alarm is disabled

6 to 0 ALARM _MINUTES[6:0] 00 to 59 the minute alarm information, coded in BCD

format

Table 17. Hour_alarm - Hour alarm register (address 0Ah) bit description

Bit Symbol Value Description

7 AE 0 hour alarm is enabled

1 hour alarm is disabled

6 x not relevant

5 to 0 ALARM_HOURS[5:0] 00 to 23 the hour alarm information, coded in BCD format

Product data sheet Rev. 06 — 21 February 2008 10 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

7.6.5 Clock output control register

7.6.6 Countdown timer

The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the

timer control register bit TE. The source clock for the timer is also selected by the timer

control register. Other timer properties such as interrupt generation are controlled via

control_status_2 register.

For accurate read back of the countdown value, the I2C-bus clock (SCL) must be

operating at a frequency of at least twice the selected timer clock.

Table 18. Day_alarm - Day alarm register (address 0Bh) bit description

Bit Symbol Value Description

7 AE 0 day alarm is enabled

1 day alarm is disabled

6 x not relevant

5 to 0 ALARM_DAYS[5:0] 01 to 31 the day alarm information, coded in BCD format

Table 19. Weekday_alarm - Weekday alarm register (address 0Ch) bit description

Bit Symbol Value Description

7 AE 0 weekday alarm is enabled

1 weekday alarm is disabled

6 to 3 x not relevant

2 to 0 ALARM_

WEEKDAYS[2:0] 0 to 6 the weekday alarm information, coded in BCD

format

Table 20. CLKOUT_control - CLKOUT control register (address 0Dh) bit description

Bit Symbol Value Description

7 FE 0 the CLKOUT output is inhibited and set to

high-impedance

1 the CLKOUT output is activated

6 to 2 x not relevant

1 to 0 FD[1:0] see Table 21 these bits control the frequency output at

pin CLKOUT

Table 21. FD1 and FD0: CLKOUT frequency selection

FD1 FD0 CLKOUT frequency

0 0 32.768 kHz

0 1 1024 Hz

1 0 32 Hz

111Hz

Product data sheet Rev. 06 — 21 February 2008 11 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

7.7 EXT_CLK test mode

A Test mode is available which allows for on-board testing. In such a mode it is possible to

set up test conditions and control the operation of the RTC.

The Test mode is entered by setting bit TEST1 in control_status_1 register. Then

pin CLKOUT becomes an input. The Test mode replaces the internal 64 Hz signal with the

signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is

divided down to 1 Hz by a 26divide chain called a pre-scaler. The pre-scaler can be set

into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0

(STOP must be cleared before the pre-scaler can operate again).

From a STOP condition, the ﬁrst 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the Test mode, no assumption as to the state of the pre-scaler can be

made.

Table 22. Timer_control - Timer control register (address 0Eh) bit description

Bit Symbol Value Description

7 TE 0 timer is disabled

1 timer is enabled

6 to 2 x not relevant

1 to 0 TD[1:0] see Table 23 timer source clock frequency select; these bits

determine the source clock for the countdown

timer; when not in use, TD[1:0] should be set

to 11 (1⁄60 Hz) for power saving

Table 23. TD1 and TD0: Timer frequency selection

TD1 TD0 TIMER Source clock frequency

0 0 4096 Hz

0 1 64 Hz

101Hz

1⁄60 Hz

Table 24. Timer - Timer value register (address 0Fh) bit description

Bit Symbol Value Description

7 to 0 TIMER 00h to FFh countdown value = n;

CountdownPeriod n

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 06 — 21 February 2008 12 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Operation example:

1. Set EXT_CLK test mode (control_status_1, bit TEST1 = 1)

2. Set STOP (control_status_1, bit STOP = 1)

3. Clear STOP (control_status_1, bit STOP = 0)

4. Set time registers to desired value

5. Apply 32 clock pulses to CLKOUT

6. Read time registers to see the ﬁrst change

7. Apply 64 clock pulses to CLKOUT

8. Read time registers to see the second change

Repeat steps 7 and 8 for additional increments.

7.8 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and hence speed up on-board test of the device. The setting of this mode

requires that the I2C-bus pins, SDA and SCL, be toggled in a speciﬁc order as shown in

Figure 8. All timings are required minimums.

Once the Override mode has been entered, the device immediately stops being reset and

normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus

access. The Override mode may be cleared by writing a logic 0 to TESTC. TESTC must

be set to logic 1 before re-entry into the Override mode is possible. Setting TESTC to

logic 0 during normal operation has no effect except to prevent entry into the POR

override mode.

Table 25 shows the register reset values.

Fig 8. POR override sequence

mgm664

SCL

500 ns 2000 ns

SDA

8 ms

override active

power up

Table 25. Register reset value[1]

Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h control_status_1 0 0 0 0 1 0 0 0

01h control_status_2 x x 0 0 0 0 0 0

02h VL_seconds 1 x x x x x x x

03h minutes 1 x x x x x x x

04h hours x x x x x x x x

Product data sheet Rev. 06 — 21 February 2008 13 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

[1] registers marked ‘x’ are undeﬁned at power-up and unchanged by subsequent resets.

8. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 9).

8.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P); see Figure 10.

05hdays xxxxxxxx

06h weekdays x x x x x x x x

07h century_months x x x x x x x x

08h years x x x x x x x x

09h minute_alarm 1 x x x x x x x

0Ah hour_alarm 1 x x x x x x x

0Bh day_alarm 1 x x x x x x x

0Ch weekday_alarm 1 x x x x x x x

0Dh CLKOUT_control 1 x x x x x 0 0

0Eh timer_control 0 x x x x x 1 1

0Fh timer x x x x x x x x

Table 25. Register reset value[1]

…continued

Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Fig 9. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Product data sheet Rev. 06 — 21 February 2008 14 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

8.3 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is a

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves (see Figure 11).

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge-related clock pulse. A slave

receiver which is addressed must generate an acknowledge after the reception of each

byte. Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter (see Figure 12).

The device that acknowledges must pull down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge-related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

event the transmitter must leave the data line HIGH to enable the master to generate a

STOP condition.

Fig 10. Deﬁnition of start and stop conditions

mbc622

SDA

SCL P

STOP condition

SDA

SCL

START condition

Fig 11. System conﬁguration

mba605

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

Product data sheet Rev. 06 — 21 February 2008 15 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

8.5 I2C-bus protocol

8.5.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the start procedure.

The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL

is only an input signal, but the data signal SDA is a bidirectional line.

The PCF8563 slave address is shown in Figure 13.

8.5.2 Clock/calendar read/write cycles

The I2C-bus conﬁguration for the different PCF8563 read and write cycles is shown in

Figure 14,Figure 15 and Figure 16. The word address is a 4-bit value that deﬁnes which

Fig 12. Acknowledgement on the I2C-bus

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Fig 13. Slave address

mce189

1 0 1 0 0 0 1 R/W

group 1 group 2

Product data sheet Rev. 06 — 21 February 2008 16 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Fig 14. Master transmits to slave receiver (Write mode)

S0ASLAVE ADDRESS WORD ADDRESS A ADATA P

acknowledgement

from slave acknowledgement

from slave

R/W

auto increment

memory word address

mbd822

n bytes

Fig 15. Master reads after setting word address (write word address; read data)

S0ASLAVE ADDRESS WORD ADDRESS A ASLAVE ADDRESS

acknowledgement

from slave acknowledgement

from slave

R/W

acknowledgement

from master

ADATA

auto increment

memory word address

001aag133

no acknowledgement

from master

1DATA

auto increment

memory word address

last byte

R/W

n bytes

at this moment master transmitter

becomes master receiver and

PCA8563 slave receiver

becomes slave transmitter

Fig 16. Master reads slave immediately after ﬁrst byte (Read mode)

S1A

SLAVE ADDRESS DATA A1DATA

acknowledgement

from slave acknowledgement

from master no acknowledgement

from master

R/W

auto increment

word address

mgl665

auto increment

word address

n bytes last byte

Product data sheet Rev. 06 — 21 February 2008 17 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

9. Limiting values

10. Static characteristics

Table 26. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6.5 V

IDD supply current −50 +50 mA

VIinput voltage on pins SCL and SDA −0.5 +6.5 V

on pin OSCI −0.5 VDD + 0.5 V

VOoutput voltage on pins CLKOUT and INT −0.5 +6.5 V

IIinput current at any input −10 +10 mA

IOoutput current at any output −10 +10 mA

Ptot total power dissipation - 300 mW

Tamb ambient temperature −40 +85 °C

Tstg storage temperature −65 +150 °C

Table 27. Static characteristics

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage interface inactive; fSCL = 0 Hz; Tamb =25°C;

see Figure 20 [1] 1.0 - 5.5 V

interface active; fSCL = 400 kHz; see Figure 20 [1] 1.8 - 5.5 V

clock data integrity; Tamb =25°CV

low - 5.5 V

IDD supply current interface active; see Figure 19

fSCL = 400 kHz - - 800 µA

fSCL = 100 kHz - - 200 µA

interface inactive (fSCL = 0 Hz); CLKOUT

disabled; Tamb =25°C; see Figure 17 [2]

VDD = 5.0 V - 275 550 nA

VDD = 3.0 V - 250 500 nA

VDD = 2.0 V - 225 450 nA

interface inactive (fSCL = 0 Hz); CLKOUT

disabled; Tamb =−40 °C to +85 °C;

see Figure 17

[2]

VDD = 5.0 V - 500 750 nA

VDD = 3.0 V - 400 650 nA

VDD = 2.0 V - 400 600 nA

Product data sheet Rev. 06 — 21 February 2008 18 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

[1] For reliable oscillator start-up at power-up: VDD(min)power-up =V

DD(min) + 0.3 V.

[2] Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3] Tested on sample basis.

IDD supply current interface inactive (fSCL = 0 Hz); CLKOUT

enabled at 32 kHz; Tamb =25°C; see Figure 18 [2]

VDD = 5.0 V - 825 1600 nA

VDD = 3.0 V - 550 1000 nA

VDD = 2.0 V - 425 800 nA

interface inactive (fSCL = 0 Hz); CLKOUT

enabled at 32 kHz; Tamb =−40 °C to +85 °C;

see Figure 18

[2]

VDD = 5.0 V - 950 1700 nA

VDD = 3.0 V - 650 1100 nA

VDD = 2.0 V - 500 900 nA

Inputs

VIL LOW-level input

voltage VSS - 0.3VDD V

VIH HIGH-levelinput

voltage 0.7VDD -V

DD V

ILI input leakage

current VI=V

DD or VSS −10 +1µA

Ciinput

capacitance [3] --7pF

Outputs

IOL LOW-level

output current VOL = 0.4 V; VDD =5V

on pin SDA −3--mA

on pin INT −1--mA

on pin CLKOUT −1--mA

IOH HIGH-level

output current on pin CLKOUT; VOH = 4.6 V; VDD =5V 1 - - mA

ILO output leakage

current VO=V

DD or VSS −10 +1µA

Voltage detector

Vlow low voltage Tamb =25°C; sets bit VL; see Figure 7 - 0.9 1.0 V

Table 27. Static characteristics

…continued

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 06 — 21 February 2008 19 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Tamb =25°C; Timer = 1 minute. Tamb =25°C; Timer = 1 minute.

Fig 17. Supply current IDD as a function of supply

voltage VDD; CLKOUT disabled Fig 18. Supply current IDD as a function of supply

voltage VDD; CLKOUT = 32 kHz

VDD = 3 V; Timer = 1 minute. Tamb =25°C; normalized to VDD =3V.

Fig 19. Supply current IDD as a function of

temperature T; CLKOUT = 32 kHz Fig 20. Frequency deviation as a function of supply

voltage VDD

02 6

mgr888

4VDD (V)

0.4

0.2

0.8

0.6

IDD

(µA)

02 6

mgr889

4VDD (V)

0.4

0.2

0.8

0.6

IDD

(µA)

−40 0 40 120

mgr890

80 T (°C)

0.4

0.2

0.8

0.6

IDD

(µA)

02 6

−4

−2

mgr891

4VDD (V)

frequency

deviation

(ppm)

Product data sheet Rev. 06 — 21 February 2008 20 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

11. Dynamic characteristics

[1] Unspeciﬁed for fCLKOUT = 32.768 kHz.

[2] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[3] A detailed description of the I2C-bus speciﬁcation, with applications, is given in brochure

The I2C-bus speciﬁcation

. This brochure may

be ordered using the code 9398 393 40011.

[4] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

Table 28. Dynamic characteristics

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Oscillator

CL(itg) integrated load capacitance 15 25 35 pF

∆fosc/fosc relative oscillator frequency variation ∆VDD = 200 mV;

Tamb =25°C-2×10−7-

Quartz crystal parameters (f = 32.768 kHz)

Rsseries resistance - - 40 kΩ

CLload capacitance parallel - 10 - pF

Ctrim trimmer capacitance 5 - 25 pF

CLKOUT output

δCLKOUT duty cycle on pin CLKOUT [1] -50-%

I2C-bus timing characteristics (see Figure 21)[2][3]

fSCL SCL clock frequency [4] - - 400 kHz

tHD;STA hold time (repeated) START condition 0.6 - - µs

tSU;STA set-up time for a repeated START condition 0.6 - - µs

tLOW LOW period of the SCL clock 1.3 - - µs

tHIGH HIGH period of the SCL clock 0.6 - - µs

trrise time of both SDA and SCL signals SDA - - 0.3 µs

SCL - - 0.3 µs

tffall time of both SDA and SCL signals SDA - - 0.3 µs

SCL - - 0.3 µs

Cbcapacitive load for each bus line - - 400 pF

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - ns

tSU;STO set-up time for STOP condition 0.6 - - µs

tw(spike) spike pulse width on bus - - 50 ns

Product data sheet Rev. 06 — 21 February 2008 21 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

12. Application information

Fig 21. I2C-bus timing waveforms

SDA

mga728

SDA

SCL

tSU;STA tSU;STO

tHD;STA

tBUF tLOW

tHD;DAT tHIGH

tSU;DAT

Fig 22. Application diagram

mgm665

SCL

SDA

VSS

OSCI

OSCO

CLOCK CALENDAR

PCF8563

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

VDD

SDA SCL

VDD

(I2C-bus)

R: pull-up resistor

R =

1 F

Product data sheet Rev. 06 — 21 February 2008 22 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

12.1 Quartz frequency adjustment

12.1.1 Method 1: ﬁxed OSCI capacitor

By evaluating the average capacitance necessary for the application layout, a ﬁxed

capacitor can be used. The frequency is best measured via the 32.768 kHz signal

available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz

crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average

±5×10−6). Average deviations of ±5 minutes per year can be easily achieved.

12.1.2 Method 2: OSCI trimmer

Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a

trimmer is possible.

12.1.3 Method 3: OSCO output

Direct measurement of OSCO out (accounting for test probe capacitance).

Product data sheet Rev. 06 — 21 February 2008 23 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

13. Package outline

Fig 23. Package outline SOT97-1 (DIP8)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT97-1 99-12-27

03-02-13

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.14 0.53

0.38 0.36

0.23 9.8

9.2 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 1.154.2 0.51 3.2

inches 0.068

0.045 0.021

0.015 0.014

0.009

1.07

0.89

0.042

0.035 0.39

0.36 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0450.17 0.02 0.13

050G01 MO-001 SC-504-8

(e )

seating plane

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

pin 1 index

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1

Product data sheet Rev. 06 — 21 February 2008 24 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Fig 24. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Product data sheet Rev. 06 — 21 February 2008 25 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Fig 25. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet Rev. 06 — 21 February 2008 26 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

Fig 26. Package outline SOT650-1 (HVSON10)

0.50.21 0.05

0.00

A1Eh

UNIT D(1) ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.75

1.45

3.1

2.9

2.55

2.15

0.30

0.18 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT650-1 MO-229 - - -- - -

E(1)

0.55

0.30

0.1

0.05

0 2 mm1

scale

SOT650-1

HVSON10: plastic thermal enhanced very thin small outline package; no leads;

10 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

01-01-22

02-02-08

terminal 1

index area

terminal 1

index area

bAC

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Product data sheet Rev. 06 — 21 February 2008 27 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

14. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

MOS devices; see

JESD625-A and/or IEC61340-5

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 06 — 21 February 2008 28 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 27) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 29 and 30

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 27.

Table 29. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 30. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 06 — 21 February 2008 29 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

MSL: Moisture Sensitivity Level

Fig 27. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 06 — 21 February 2008 30 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

16. Revision history

Table 31. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8563_6 20080221 Product data sheet - PCF8563_5

Modiﬁcations: •Register names modiﬁed in Figure 1 and various tables.

•Figure 17,Figure 18 and Figure 19: corrected the unit on the vertical axis.

PCF8563_5 20070717 Product data sheet - PCF8563-04

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Quick reference data table removed to comply with guidelines.

•Table 3: Table 3 and Table 4 combined in one table.

•Section 4: added topside mark.

•Section 4: added HVSON10 package.

PCF8563-04

(9397 750 12999) 20040312 Product data - PCF8563-03

PCF8563-03

(9397 750 11158) 20030414 Product data - PCF8563-02

PCF8563-02

(9397 750 04855) 19990416 Product data - PCF8563_N_1

PCF8563_N_1

(9397 750 03282) 19980325 Objective speciﬁcation - -

Product data sheet Rev. 06 — 21 February 2008 31 of 32

NXP Semiconductors PCF8563

Real-time clock/calendar

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCF8563

Real-time clock/calendar

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 February 2008

Document identifier: PCF8563_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 Alarm function modes. . . . . . . . . . . . . . . . . . . . 4

7.2 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.5 Voltage-low detector. . . . . . . . . . . . . . . . . . . . . 5

7.6 Register organization . . . . . . . . . . . . . . . . . . . . 6

7.6.1 Control_status_1 register . . . . . . . . . . . . . . . . . 6

7.6.2 Control_status_2 register . . . . . . . . . . . . . . . . . 6

7.6.3 Time and date registers . . . . . . . . . . . . . . . . . . 7

7.6.4 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.6.5 Clock output control register. . . . . . . . . . . . . . 10

7.6.6 Countdown timer. . . . . . . . . . . . . . . . . . . . . . . 10

7.7 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 11

7.8 Power-On Reset (POR) override . . . . . . . . . . 12

8 Characteristics of the I2C-bus. . . . . . . . . . . . . 13

8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8.2 Start and stop conditions . . . . . . . . . . . . . . . . 13

8.3 System conﬁguration . . . . . . . . . . . . . . . . . . . 14

8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.5 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 15

8.5.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.5.2 Clock/calendar read/write cycles . . . . . . . . . . 15

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 17

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 20

12 Application information. . . . . . . . . . . . . . . . . . 21

12.1 Quartz frequency adjustment . . . . . . . . . . . . . 22

12.1.1 Method 1: ﬁxed OSCI capacitor . . . . . . . . . . . 22

12.1.2 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 22

12.1.3 Method 3: OSCO output. . . . . . . . . . . . . . . . . 22

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

14 Handling information. . . . . . . . . . . . . . . . . . . . 27

15 Soldering of SMD packages . . . . . . . . . . . . . . 27

15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 27

15.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 27

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27

15.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 28

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 31

17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 31

17.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31

18 Contact information . . . . . . . . . . . . . . . . . . . . 31

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32