1
November 01, 2001
U6264A
Standard 8K x 8 SRAM
FESD protection > 2000 V
(MIL STD 883C M3015.7)
FLatch-up im mu nity > 100 mA
FPackages: PDIP28 (600 mil)
SO P28 (300 mil)
SO P28 (330 mil)
Description
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read - St andby
- Write - Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the act ive state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycl e.
In a Read cycle, the data outputs
are activated by the falling ed ge of
G, afterwards the data word read
will be av a ilable a t t he ou tp u ts
DQ0 - DQ7. After the address
change, the dat a outputs go High-Z
until the new read information is
available. The data outputs have
no preferred state. If the memo ry is
driven by CMOS levels in the
active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E 2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
wit h TTL-lev els too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150 µA typ.
F8192 x 8 bit static CMOS RAM
F70 and 100 ns Access Times
FCommon data inputs and
outputs
FThree-state outputs
FTyp. operating supply current
70 ns: 45 mA
100 ns: 37 mA
FData retention current
at 3 V: < 10 µA (standard)
FStandby current standard < 30 µA
FStandby current low power
(L) < 10 µA
FStandby current very low power
(LL) < 1 µA
FStandby current for LL-version
at 25 °C and 5 V: typ. 50 nA
FTTL/CMOS-compatible
FAutomatic reduction of power dis-
sip ation in long Read or Write
cycles
FPower supply voltage 5 V
FOperati ng temperature ranges:
0 to 70 °C
-25 to 85 °C
-40 to 85 °C
FQuality assessmen t according to
CECC 90000, CECC 90100 and
CECC 90111
Pin Description
Sign al Name Sign al Desc ription
A0 - A12 Address Inputs
DQ0 - DQ7 Da ta In/Out
E1 Chip Enable 1
E2 Chip Enable 2
GOut put Enabl e
WWrite Enable
VCC Powe r Supply Vo ltage
VSS Ground
n.c. not connected
Pin Configuration
1
n.c. VCC
28
2
A12 W (WE)
27
4
A6 A8
25
5
A5 A9
24
3
A7 E2 (CE2)
26
6
A4 A11
23
7
A3 G (OE)
22
8
A2 A10
21
12
DQ1 DQ5
17
9
A1 E1 (CE1)
20
10
A0 DQ7
19
11
DQ0 DQ6
18
13
DQ2 DQ4
16
14
VSS DQ3
15
PDIP
Top View
SOP
Features
2 November 01, 2001
U6264A
Block Diagram
*H or L
Operating Mode E1 E2 W GDQ0 - DQ7
Standby/not
selected * L * * High-Z
H*** High-Z
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L * Data In puts High-Z
Truth Tab l e
Maximum Ratings Symbol Min. Max. Unit
Power Supply Vol tage VCC -0.3 7 V
Input Voltage VI-0.3 VCC + 0.5 V
Outp ut Voltage VO-0.3 VCC + 0.5 V
Power Dissipation PD-1W
Operat ing Temperature C-Type
G-Type
K-Type
Ta0
-25
-40
70
85
85
°C
°C
°C
St orage Temperature Tstg -55 125 °C
Characteristics
All voltages are referenced to VSS = 0 V (grou nd).
All characteristics are valid in the power supply volt age range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measure d between 10 % an d 90 % of VI,as well as
input levels of VIL = 0 V and VIH = 3 V. T he timing reference level of all input and ou tput signals i s 1.5 V,
with the excep tion of the t dis-times, in which cases transition is measured ± 200 mV fro m steady -state voltage.
Address
Change
Detector
A0
A1
A2
A3
A10
Mem ory Cell
Array
256 R ow s x
256 Columns
Row Decoder
Row Address
Inputs
Column Decoder
Common Data I/O
Sense Amplifier/
Write Control Logic
Clock
Generator
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E2
E1
Column Address
Inputs
VCC VSS W G
A4
A5
A6
A7
A8
A9
A11
A12
3
November 01, 2001
U6264A
* -2 V at Pulse Width 10 ns
Recommended
Oper ating Conditions Symbol Conditions Min. Max. Unit
Powe r Supply Vo ltage VCC 4.5 5.5 V
Data Ret ention Volt age VCC(DR) 2.0 V
Input Low Voltage* VIL -0.3 0.8 V
Input High Vol tage VIH 2.2 VCC + 0.3 V
Electrical Characteristic s Symbol C ondition s Min. Max. Unit
Suppl y Current - Operating Mode
Standard
Low Power (L)
Very Low Power (LL)
ICC(OP) VCC
VIL
VIH
tcW
tcW
tcW
tcW
tcW
tcW
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
= 100 ns
= 70 ns
= 100 ns
= 70 ns
= 100 ns
70
60
70
60
55
45
mA
mA
mA
mA
mA
mA
Suppl y Current - Standby Mode
(CMOS level )
Standard
Low Power (L)
Very Low Power (LL)
ICC(SB) VCC
VE1 = VE2
or VE2
= 5.5 V
= VCC - 0.2 V
= 0.2 V
30
10
1
µA
µA
µA
Suppl y Current - Standby Mode
(TT L lev e l)
Standard
Low Power (L)
Very Low Power (LL)
ICC(SB)1 VCC
VE1 = VE2
or VE2
= 5.5 V
= 2.2 V
= 0.2 V
5
5
3
mA
mA
mA
Supply Current - Data Retention
Mode
Standard
Low Power (L)
Very Low Power (LL)
ICC(DR) VCC(DR)
VE1 = VE2
or VE2
= 3 V
= VCC(DR) - 0.2 V
= 0.2 V
10
10
1
µA
µA
µA
4 November 01, 2001
U6264A
Electrical Characteristics Symb ol Conditions M i n. Ma x. U nit
Output High Voltage
Output Low V ol tage
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
= -1.0 mA
= 4.5 V
= 3.2 mA
2.4
0.4
V
V
Input Leakage Curr ent
Standard &
Low Power (L)
Very Low Power (LL)
High
Low
High
Low
IIH
IIL
IIH
IIL
VCC
VIH
VCC
VIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
-2
-1
2
1
µA
µA
µA
µA
Output High Current
O utput Lo w Cur ren t
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V 3.2
-1 mA
mA
Output Leakage Current
Standard & Low Power (L)
High at Three-S tate Outputs
Low at Three-S t ate Outputs
Very Low Power (LL)
High at Three-S tate Outputs
Low at Three-S t ate Outputs
IOHZ
IOLZ
IOHZ
IOLZ
VCC
VOH
VCC
VOL
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V
-2
-2
2
1
-
µA
µA
µA
µA
5
November 01, 2001
U6264A
Switching Characteri sti cs Symbol Min. Max. Unit
Alt. IEC 07100710
T i me to Output in Low-Z tLZ tt(QX) 5 5 10 10 ns
Cycle Time
Write Cycle Time
Read Cycle Time tWC
tRC
tcW
tcR
70
70 100
100 ns
ns
Access Time
E1 L O W o r E2 H IGH to D a ta Valid
G LOW to Data Valid
Address to Data Valid
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
-
-
-
-
-
-
70
40
70
100
50
100
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write tWP
tCW
tw(W)
tw(E)
50
65 70
90 ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Da ta Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
tsu(D)
0
65
50
35
0
90
70
40
ns
ns
ns
ns
Data Hold Time
Address Hold from End of Write tDH
tAH
th(D)
th(A)
0
00
0ns
ns
Output Hold Time from Address Change tOH tv(A) 55 ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
tHZCE
tHZWE
tHZOE
tdis(E)
tdis(W)
tdis(G)
0
0
0
0
0
0
25
30
25
35
35
35
ns
ns
ns
Data Retention Mode E1-Controlled
Data Retention
4.5 V
tDR trec
VCC
E1
VCC(DR) ≥ 2 V
VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
0 V
2.2 V
2.2 V VCC(DR) ≥ 2 V
Data Ret ention Mode E 2- C on tr ol led
Data Retention trec
tDR 0.8 V
0.8 V VE2(DR) ≤ 0.2 V
4.5 V
0 V
VCC
E2
Chip Deselect to Data Retention Ti me tDR : min 0 ns
Operating Rec overy Time trec : min tcR
6 November 01, 2001
U6264A
Example
Test Confi gurat i on for Functiona l Ch eck
VIH
VIL
VSS
VCC
5 V
960
510
30 pF1)
VO
Simultaneous measure-
m ent of all 8 outp ut pins
Input level according to the
relev ant tes t measurement
1) In measurem ent of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.
IC Code Numbers
07
All pins not under test must be connected with ground by capacitors.
LU6264A GD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
E1
E2
W
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Capacitance Conditions Symbol Min. Max. Unit
Input Capacit ance VCC = 5.0 V
VI = VSS CI8pF
Output Capacitance f = 1 MHz
Ta = 25 °CCO10 pF
Type
Package
D = PDIP
S = SOP (330 mil)
S1 = SOP (300 mil)
Access Time
07 = 70 ns
10 = 100 ns
Power Consumption
= Standard
L = Low Power
LL = Very Low Power
In t e r na l C ode
Operating Temperature Range
C = 0 to 70 °C
G = -25 to 85 °C
K = -40 to 85 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
7
November 01, 2001
U6264A
th(D)
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
Read Cycle 2 (during Read cycle: W = VIH)
Wr ite Cycle 1 (W-controlled)
ta(A)
Previous Data Valid Output Data Valid
tcR
Addresses Valid
tv(A)
Ai
DQi
Ai
E1
E2
G
DQi
Output
Output
tdis(E)
tcR
tsu(A) ta(E)
tsu(A)
tt(QX)
tt(QX)
tt(QX)
ta(G)
ta(E) tdis(E)
tdis(G)
Addresses Valid
Output Data Valid
Ai
E1
E2
W
DQi
Input
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A)
tsu(E)
tsu(D)
tdis(W) tt(QX)
Addres ses Valid
Inpu t D ata Vali d
High-Z
High-Z
8 November 01, 2001
U6264A
High-Z
tsu(A)
Inpu t D ata Vali d
th(D)
tsu(W)
tw(E)
tsu(D)
tcW
Addresses Valid
tsu(E) th(A)
tt(QX) tdis(W)
Ai
E1
E2
W
DQi
Input
G
DQi
Output
tsu(A)
undefined L- or H-level
Write Cycle 2 (E1-controlled)
Wr ite Cycle 3 (E2-controlled)
th(D)
Ai
E1
E2
W
DQi
Input
G
DQi
Output
tcW
tw(E) th(A)
tsu(W)
tsu(E)
tsu(D)
tdis(W)
tt(QX)
Ad dr e s se s Vali d
Input Data Va lid
High-Z
The information desc ribes the type of component and shall not be considered as assured characteristic. Te rms of
delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email : sales@zmd.d e • http://www.zmd.de
November 01, 2001
U6264A
LIFE S U PP O R T POLIC Y
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or o ther applications intended to s upport or sustain life, or f or any othe r application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Componen ts used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or wa rran ty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The inform ation in this docum ent des cribes t he t ype of comp onent and sh all not be c onsidere d as ass ured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upo n the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product bey ond that set forth in its standard terms and
condition s of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
