U6264A Standard 8K x 8 SRAM Features F 8192 x 8 bit static CMOS RAM F 70 and 100 ns Access Times F Common data inputs and outputs F Three-state outputs F Typ. operating supply current F F F F F F F F F F 70 ns: 45 mA 100 ns: 37 mA Data retention current at 3 V: < 10 A (standard) Standby current standard < 30 A Standby current low power (L) < 10 A Standby current very low power (LL) < 1 A Standby current for LL-version at 25 C and 5 V: typ. 50 nA TTL/CMOS-compatible Automatic reduction of power dissipation in long Read or Write cycles Power supply voltage 5 V Operating temperature ranges: 0 to 70 C -25 to 85 C -40 to 85 C Quality assessment according to CECC 90000, CECC 90100 and CECC 90111 F ESD protection > 2000 V (MIL STD 883C M3015.7) F Latch-up immunity > 100 mA F Packages: PDIP28 (600 mil) SOP28 (300 mil) SOP28 (330 mil) Description The U6264A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. During the active state (E1 = L and E2 = H), each address change leads to a new Read or Write cycle. In a Read cycle, the data outputs are activated by the falling edge of Pin Configuration Pin Description n.c. 1 28 VCC A12 2 27 W (WE) A7 3 26 E2 (CE2) A6 4 25 A5 5 A4 6 A3 7 A2 8 PDIP 22 SOP 21 A1 9 20 E1 (CE1) A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 VSS 14 15 DQ3 Signal Name Signal Description A8 A0 - A12 Address Inputs 24 A9 DQ0 - DQ7 Data In/Out 23 A11 E1 Chip Enable 1 G (OE) E2 Chip Enable 2 A10 G Output Enable W VCC Write Enable Power Supply Voltage VSS Ground n.c. not connected Top View November 01, 2001 G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too. If the circuit is inactivated by E2 = L, the standby current (TTL) drops to 150 A typ. 1 A2 A3 A10 Memory Cell Array 256 Rows x 256 Columns DQ0 Sense Amplifier/ Write Control Logic Address Change Detector E2 DQ1 Common Data I/O A1 Row Decoder A0 Column Decoder A4 A5 A6 A7 A8 A9 A11 A12 Row Address Inputs Block Diagram Column Address Inputs U6264A Clock Generator DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS VCC 1 W G E1 Truth Table Operating Mode E1 E2 W G DQ0 - DQ7 Standby/not selected * L * * High-Z H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times, in which cases transition is measured 200 mV from steady-state voltage. Maximum Ratings Symbol Min. Max. Unit VCC -0.3 7 V Input Voltage VI -0.3 VCC + 0.5 V Output Voltage VO -0.3 VCC + 0.5 V Power Dissipation PD - 1 W Ta 0 -25 -40 70 85 85 C C C Tstg -55 125 C Power Supply Voltage Operating Temperature Storage Temperature C-Type G-Type K-Type 2 November 01, 2001 U6264A Recommended Operating Conditions Symbol Conditions Min. Max. Unit 5.5 V Power Supply Voltage VCC 4.5 Data Retention Voltage VCC(DR) 2.0 Input Low Voltage* VIL -0.3 0.8 V Input High Voltage VIH 2.2 VCC + 0.3 V Min. Max. Unit V * -2 V at Pulse Width 10 ns Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) Conditions VCC VIL VIH = 5.5 V = 0.8 V = 2.2 V Standard tcW tcW = 70 ns = 100 ns 70 60 mA mA Low Power (L) tcW tcW = 70 ns = 100 ns 70 60 mA mA Very Low Power (LL) tcW tcW = 70 ns = 100 ns 55 45 mA mA 30 10 1 A A A 5 5 3 mA mA mA 10 10 1 A A A Supply Current - Standby Mode (CMOS level) ICC(SB) VCC = 5.5 V VE1 = VE2 = VCC - 0.2 V = 0.2 V or VE2 Standard Low Power (L) Very Low Power (LL) Supply Current - Standby Mode (TTL level) ICC(SB)1 VCC = 5.5 V VE1 = VE2 = 2.2 V = 0.2 V or VE2 Standard Low Power (L) Very Low Power (LL) Supply Current - Data Retention Mode ICC(DR) VCC(DR) = 3V VE1 = VE2 = VCC(DR) - 0.2 V = 0.2 V or VE2 Standard Low Power (L) Very Low Power (LL) November 01, 2001 3 U6264A Electrical Characteristics Symbol Output High Voltage VOH Output Low Voltage VOL Input Leakage Current Standard & Low Power (L) Very Low Power (LL) High IIH Low IIL High IIH Low IIL Output High Current IOH Output Low Current IOL Output Leakage Current Standard & Low Power (L) High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ Very Low Power (LL) High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ Conditions VCC IOH VCC IOL = 4.5 V = -1.0 mA = 4.5 V = 3.2 mA VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0V 4 4.5 V 2.4 V 4.5 V 0.4 V Min. Max. 2.4 V 0.4 V 2 A A -2 1 A A -1 -1 3.2 mA mA 2 A A -2 -2 Unit 1 A - A November 01, 2001 U6264A Symbol Min. Max. Unit Switching Characteristics Alt. IEC 07 10 07 10 Time to Output in Low-Z tLZ tt(QX) 5 5 10 10 Cycle Time Write Cycle Time Read Cycle Time tWC tRC tcW tcR 70 70 100 100 Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid tACE tOE tAA ta(E) ta(G) ta(A) - - Pulse Widths Write Pulse Width Chip Enable to End of Write tWP tCW tw(W) tw(E) 50 65 70 90 ns ns Setup Times Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time tAS tCW tWP tDS tsu(A) tsu(E) tsu(W) tsu(D) 0 65 50 35 0 90 70 40 ns ns ns ns Data Hold Time Address Hold from End of Write tDH tAH th(D) th(A) 0 0 0 0 ns ns Output Hold Time from Address Change tOH tv(A) 5 5 ns tHZCE tdis(E) 0 0 25 35 ns tHZWE tHZOE tdis(W) tdis(G) 0 0 0 0 30 25 35 35 ns ns E1 HIGH or E2 LOW to Output in High-Z W LOW to Output in High-Z G HIGH to Output in High-Z Data Retention Mode E1-Controlled Data Retention 100 50 100 trec ns ns ns VCC VCC(DR) 2 V 2.2 V E1 tDR 0.8 V 0V Data Retention VE2(DR) 0.2 V 0V VE2(DR) VCC(DR) - 0.2 V or V E2(DR) 0.2 V VCC(DR) - 0.2 V VE1(DR) V CC(DR) + 0.3 V Chip Deselect to Data Retention Time Operating Recovery Time November 01, 2001 70 40 70 4.5 V VCC(DR) 2 V 2.2 V tDR ns ns Data Retention Mode E2-Controlled VCC 4.5 V ns 5 tDR : trec : min 0 ns min tcR E2 trec 0.8 V U6264A Test Configuration for Functional Check 1) DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 960 ment of all 8 output pins E1 E2 W G VCC Simultaneous measure- VIL relevant test measurement VIH Input level according to the 5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VO 30 pF1) 510 VSS In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF. Capacitance Conditions Symbol Min. Max. Unit Input Capacitance VCC = 5.0 V VI = VSS CI 8 pF Output Capacitance f Ta CO 10 pF = 1 MHz = 25 C All pins not under test must be connected with ground by capacitors. IC Code Numbers Example U6264A D G 07 L Type Internal Code Package D = PDIP S = SOP (330 mil) S1 = SOP (300 mil) Power Consumption = Standard L = Low Power LL = Very Low Power Operating Temperature Range C = 0 to 70 C G = -25 to 85 C K = -40 to 85 C Access Time 07 = 70 ns 10 = 100 ns The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. 6 November 01, 2001 U6264A Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH) tcR Ai DQi Output Addresses Valid ta(A) Previous Data Valid Output Data Valid tv(A) Read Cycle 2 (during Read cycle: W = VIH) tcR Ai E1 Addresses Valid ta(E) tsu(A) tt(QX) tdis(E) tsu(A) ta(E) E2 ta(G) G DQi Output tdis(E) tt(QX) tdis(G) tt(QX) High-Z Output Data Valid Write Cycle 1 (W-controlled) tcW Ai Addresses Valid tsu(E) th(A) E1 E2 W tsu(E) tsu(A) tw(W) tsu(D) DQi Input DQi Input Data Valid tdis(W) tt(QX) High-Z Output G November 01, 2001 th(D) 7 U6264A Write Cycle 2 (E1-controlled) tcW Ai tsu(A) E1 E2 Addresses Valid tw(E) th(A) tsu(E) tsu(W) W th(D) tsu(D) DQi Input tt(QX) Input Data Valid tdis(W) DQi High-Z Output G Write Cycle 3 (E2-controlled) tcW Ai Addresses Valid tsu(E) th(A) E1 tsu(A) tw(E) E2 tsu(W) W tsu(D) DQi Input tt(QX) th(D) Input Data Valid tdis(W) DQi High-Z Output G L- or H-level undefined The information describes the type of component and shall not be considered as assured characteristic. Terms of delivery and rights to change design reserved. 8 November 01, 2001 U6264A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. Zentrum Mikroelektronik Dresden AG November 01, 2001 Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: sales@zmd.de * http://www.zmd.de