MT28F162P2FG-80BET - Micron

ADVANCE‡

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

MT28F162P2FG_1.p65 – Rev. 1, Pub. 6/01

1 MEG x 16

PAGE FLASH MEMORY

FLASH MEMORY MT28F162P2

Low Voltage, Extended Temperature

BALL ASSIGNMENT

48-Ball FBGA

FEATURES

• Flexible dual-bank architecture

– Support for true concurrent operation with zero

latency

– Read bank a during program bank b and vice

versa

– Read bank a during erase bank b and vice versa

• Basic configuration:

Thirty-nine erasable blocks

– Bank a (4Mb for data storage)

– Bank b (12Mb for program storage)

•VCC, VCCQ, VPP voltages*

– 1.65V (MIN), 1.95V (MAX) VCC, VCCQ or

1.80V (MIN), 2.20V (MAX) VCC, VCCQ

– 1.65V (MIN) VPP (in-system PROGRAM/ERASE)

– 12V ±5% (HV) VPP tolerant (factory

programming compatibility)

• Random access time: 80ns and 90ns @ 1.80V VCC*

• Page Mode read access*

– Eight-word page

– Interpage read access: 80ns/90ns @ 1.80V

– Intrapage read access: 30ns/35ns @ 1.80V

• Low power consumption (VCC = 1.95V)

– READ < 15mA

– WRITE/ERASE < 20mA (MAX)

– Standby < 25µA (TYP), 50µA (MAX)

– Automatic power saving feature (APS)

• Enhanced write and erase suspend options

– ERASE-SUSPEND-to-READ within same bank

– PROGRAM-SUSPEND-to-READ within same bank

– ERASE-SUSPEND-to-PROGRAM within same bank

• Dual 64-bit chip protection registers for security

purposes

• Cross-compatible command support

– Extended command set

– Common Flash interface

• PROGRAM/ERASE cycle

– 100,000 WRITE/ERASE cycles per block

* These specifications are guaranteed for operations within

either one of two voltage ranges, 1.65V–1.95 or 1.80–2.20V.

Use only one of the voltage ranges for PROGRAM and ERASE

operations.

NOTE: See page 7 for Ball Description Table.

See page 37 for mechanical drawing.

1 2 3 4 5 6 7 8

Top View

(Ball Down)

A13

A14

A15

A16

A19

A17

DQ8

DQ9

DQ10

WP#

A18

DQ2

DQ3

WE#

DQ5

DQ6

DQ13

OE#

CE#

DQ0

DQ1

A11

A10

A12

DQ14

DQ15

DQ7

RST#

DQ11

DQ12

DQ4

OPTIONS MARKING

• Timing

80ns access -80

90ns access -90

• Boot Block Starting Address

Top (FFFFFh) T

Bottom (00000h) B

• Package

48-ball FBGA (6 x 8 ball grid) FG

• Operating Temperature Range

Extended (-40ºC to +85ºC) ET

Part Number Example:

MT28F162P2FG-80

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

GENERAL DESCRIPTION

The MT28F162P2 is a high-performance, high-

density, nonvolatile memory solution that can

significantly improve system performance. This new

architecture features a two-memory-bank configura-

tion that supports background operation with no

latency.

A high-performance bus interface allows a fast page

mode, data transfer; a conventional asynchronous bus

interface is provided as well.

The MT28F162P2 allows soft protection for blocks,

as read only, by configuring soft protection registers

with dedicated command sequences. For security pur-

poses, two 64-bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state

machine (WSM). Two on-chip status registers, one for

each of the two memory partitions, can be used to moni-

tor the WSM status and to determine the progress of

the program/erase task.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-

ware packages.

The device is manufactured using 0.22µm process

technology.

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

ARCHITECTURE AND MEMORY

ORGANIZATION

The MT28F162P2 Flash device contains two sepa-

rate banks of memory (bank a and bank b) for simulta-

neous READ and WRITE operations.

The MT28F162P2 Flash memory is available in the

following bank segmentation configuration:

• Bank a is one-fourth of the memory and con-

tains 8 x 4K-word parameter blocks; the re-

mainder of bank a is split into 7 x 32K-word

blocks.

• Bank b represents three-fourths of the

memory, is equally sectored, and contains 24

x 32K-word blocks.

Figures 2 and 3 show the bottom and top memory

organizations.

DEVICE MARKING

Due to the size of the package, Micron’s standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross referenced to Micron part num-

bers in Table 1.

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT SAMPLE MECHANICAL

PART NUMBER MARKING MARKING SAMPLE MARKING

MT28F162P2FG-80 BET FW729 FX729 FY729

MT28F162P2FG-80 TET FW727 FX727 FY727

MT28F162P2FG-90 BET FW728 FX728 FY728

MT28F162P2FG-90 TET FW726 FX726 FY726

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

PART NUMBERING INFORMATION

Micron’s low-power devices are available with sev-

eral different combinations of features (see Figure 1).

Table 2

Valid Part Number Combinations

BOOT BLOCK OPERATING

ACCESS STARTING TEMPERATURE

PART NUMBER TIME (ns) ADDRESS RANGE

MT28F162P2FG-80 BET 80 Bottom -40oC to +85oC

MT28F162P2FG-80 TET 80 Top -40oC to +85oC

MT28F162P2FG-90 BET 90 Bottom -40oC to +85oC

MT28F162P2FG-90 TET 90 Top -40oC to +85oC

MT 28F 162 P 2 FG-90 T ET

Micron Technology

Flash Family

28F = Dual-Supply Flash

Density/Organization/Banks

162 = 16Mb (1,024K x 16)

bank a = 1/4; bank b = 3/4

Access Time

-80 = 80ns

-90 = 90ns

-10 = 100ns

Read Mode Operation

P = Asynchronous/Page Read

Package Code

FG = 48-ball FBGA (6 x 8 grid)

Operating Temperature Range

ET = Extended (-40ºC to +85ºC)

Boot Block Starting Address

B = Bottom boot

T = Top boot

Operating Voltage Range

2 = 1.65V–1.95V or 1.80V–2.20V

Figure 1

Part Number Chart

Valid combinations of features and their correspond-

ing part numbers are listed in Table 2.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

Address

Input

Buffer

X DEC

Y/Z DEC

Data Input

Buffer

Output

Multiplexer

Address

CNT WSM

Output

Buffer

Status

Reg.

WSM

Program/

Erase

Pump Voltage

Generators

Address Latch

DQ0–DQ15

CSM

RST#

CE#

X DEC

Y/Z DEC

WE#

OE#

I/O Logic

A0–A19

Address

Multiplexer

Bank 2 Blocks

Y/Z Gating/Sensing

Data

Bank 1 Blocks

Y/Z Gating/Sensing

ID Reg.

RCR

Block Lock

Device ID

Manufacturer’s ID

OTP

Query

PR Lock

Query/OTP

PR Lock

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Figure 2

Bottom Boot Block Device

Bank b = 12Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

38 64/32 0F8000h-0FFFFFh

37 64/32 0F0000h-0F7FFFh

36 64/32 0E8000h-0EFFFFh

35 64/32 0E0000h-0E7FFFh

34 64/32 0D8000h-0DFFFFh

33 64/32 0D0000h-0D7FFFh

32 64/32 0C8000h-0CFFFFh

31 64/32 0C0000h-0C7FFFh

30 64/32 0B8000h-0BFFFFh

29 64/32 0B0000h-0B7FFFh

28 64/32 0A8000h-0AFFFFh

27 64/32 0A0000h-0A7FFFh

26 64/32 098000h-097FFFh

25 64/32 090000h-097FFFh

24 64/32 088000h-087FFFh

23 64/32 080000h-087FFFh

22 64/32 078000h-07FFFFh

21 64/32 070000h-077FFFh

20 64/32 068000h-067FFFh

19 64/32 060000h-067FFFh

18 64/32 058000h-05FFFFh

17 64/32 050000h-057FFFh

16 64/32 048000h-04FFFFh

15 64/32 040000h-047FFFh

Bank a = 4Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

14 64/32 038000h-03FFFFh

13 64/32 030000h-037FFFh

12 64/32 028000h-02FFFFh

11 64/32 020000h-027FFFh

10 64/32 018000h-01FFFFh

9 64/32 010000h-017FFFh

8 64/32 008000h-00FFFFh

7 8/4 007000h-007FFFh

6 8/4 006000h-006FFFh

5 8/4 005000h-005FFFh

4 8/4 004000h-004FFFh

3 8/4 003000h-003FFFh

2 8/4 002000h-002FFFh

1 8/4 001000h-001FFFh

0 8/4 000000h-000FFFh

Figure 3

Top Boot Block Device

Bank b = 12Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

23 64/32 0B8000h-0BFFFFh

22 64/32 0B0000h-0B7FFFh

21 64/32 0A8000h-0AFFFFh

20 64/32 0A0000h-0A7FFFh

19 64/32 098000h-09FFFFh

18 64/32 090000h-097FFFh

17 64/32 088000h-08FFFFh

16 64/32 080000h-087FFFh

15 64/32 078000h-07FFFFh

14 64/32 070000h-077FFFh

13 64/32 068000h-06FFFFh

12 64/32 060000h-067FFFh

11 64/32 058000h-05FFFFh

10 64/32 050000h-057FFFh

9 64/32 048000h-04FFFFh

8 64/32 040000h-047FFFh

7 64/32 038000h-03FFFFh

6 64/32 030000h-037FFFh

5 64/32 028000h-02FFFFh

4 64/32 020000h-027FFFh

3 64/32 018000h-01FFFFh

2 64/32 010000h-017FFFh

1 64/32 008000h-00FFFFh

0 64/32 000000h-007FFFh

Bank a = 4Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

38 8/4 0FF000h-0FFFFFh

37 8/4 0FE000h-0FEFFFh

36 8/4 0FD000h-0FDFFFh

35 8/4 0FC000h-0FCFFFh

34 8/4 0FB000h-0FBFFFh

33 8/4 0FA000h-0FAFFFh

32 8/4 0F9000h-0F9FFFh

31 8/4 0F8000h-0F8FFFh

30 64/32 0F0000h-0F7FFFh

29 64/32 0E8000h-0EFFFFh

28 64/32 0E0000h-0E7FFFh

27 64/32 0D8000h-0DFFFFh

26 64/32 0D0000h-0D7FFFh

25 64/32 0C8000h-0CFFFFh

24 64/32 0C0000h-0C7FFFh

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

BALL DESCRIPTIONS

48-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

D8, C8, B8, C7, A0–A19 Input Address Inputs: Inputs for the address during READ and WRITE

A8, B7, C6, A7, operations. Addresses are internally latched during READ and WRITE

A3, C3, B2, A2, cycles.

C2, A1, B1, C1,

D1, B6, B5, A6

D7 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the

device is disabled and goes into standby power mode.

F8 OE# Input Output Enable: Enables the output buffer when LOW. When OE# is

HIGH, the output buffers are disabled.

B3 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is

LOW, the cycle is either a WRITE to the command state machine

(CSM) or to the memory array.

B4 RST# Input Reset: When RST# is a logic LOW, the device is in reset mode, which

drives the outputs to High-Z and resets the write state machine

(WSM). When RST# is at logic HIGH, the device is in standard

operation. When RST# transitions from logic LOW to logic HIGH, the

device resets all blocks to locked and defaults to the read array

mode.

A5 WP# Input Write Protect: Controls the lock down function of the flexible locking

feature.

A4 VPP Input Program/Erase Enable: [0.9V–2.2V or 11.4V–12.6V] Operates as input

at logic levels to control complete device protection. Provides factory

programming compatibility when driven to 11.4V–12.6V.

E7, F7, D5, B5, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE#

F4, D3, E3, F2, Output cycle during PROGRAM command. Input commands to the

D6, 36, F6, D4, command user interface when CE# and WE# are active. DQ0–DQ15

E4, F3, D2, E2 output data when CE# and OE# are active.

E8, F1 VSS Supply Do not float any ground ball.

F5 VCC Supply Device Power Supply: [1.65V–1.95 or 1.80–2.20V] Supplies power for

device operation.

E1 VCCQ Supply I/O Power Supply: [1.65V–1.95 or 1.80–2.20V] Supplies power for

input/output buffers. This input should be tied directly to VCC.

C4, C5 NC – Internally not connected; contact balls may not be physically present.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

COMMAND STATE MACHINE (CSM)

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between external

microprocessors and the internal WSM. The available

commands are listed in Table 3, their definitions are

given in Table 4, and their descriptions in Table 5.

Program and erase algorithms are automated by an

on-chip WSM. Table 6 shows the CSM transition states.

Once a valid PROGRAM/ERASE command is entered,

the WSM executes the appropriate algorithm, which

generates the necessary timing signals to control the

device internally and accomplish the requested op-

eration. A command is valid only if the exact sequence

of WRITEs is completed. After the WSM completes its

task, the WSM status bit (SR7) (see Table 8) is set to a

logic HIGH level (1), allowing the CSM to respond to the

full command set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional

microprocessor timings into an on-chip CSM through

I/Os DQ0–DQ7. The number of bus cycles required to

activate a command is typically one or two. The first

operation is always a WRITE. Control signals CE# and

WE# must be at a logic LOW level (VIL), and OE# and

RST# must be at logic HIGH (VIH). The second opera-

tion, when needed, can be a WRITE or a READ depend-

ing upon the command. During a READ operation, con-

trol signals CE# and OE# must be at a logic LOW level

(VIL), and WE# and RST# must be at logic HIGH (VIH).

Table 7 shows the bus operations for all the modes:

write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-

tion. Changing the mode of operation requires that a

command code be entered into the CSM. For each one

of the two memory partitions, an on-chip status regis-

ter is available. These two registers allow the progress

of the various operations that can take place on a

memory bank to be monitored. One of the two status

registers is interrogated by entering a READ STATUS

ing an address within the memory partition boundary,

and reading the register data on I/Os DQ0–DQ7 (cycle

2). Status register bits SR0-SR7 correspond to DQ0–

DQ7 (see Table 8).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating

the necessary timing signals to program, erase, and

verify data. See Table 4 for the CSM command defini-

tions and data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is

pending or complete. The status register is monitored

toggling OE#, CE#, and address lines by reading the

resulting status code on I/Os DQ0–DQ7. The high-

order I/Os (DQ8–DQ15) are set to 00h internally, so

Table 3

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7 CODE ON DEVICE MODE

10h/40h Program setup/alternate program setup

20h Block erase setup

50h Clear status register

60h Protection configuration setup

70h Read status register

90h Read protection configuration register

98h Read query

B0h Program/erase suspend

C0h Protection register program/lock

D0h Program/erase resume – erase confirm

FFh Read array

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

only the low-order I/Os (DQ0–DQ7) need to be inter-

preted. Address lines select the status register perti-

nent to the selected memory partition.

edge of OE# or CE#, whichever occurs first. The latest

falling edge of either of these two signals updates the

latch within a given READ cycle. Latching the data pre-

vents errors from occurring if the register input changes

during a status register read.

The status register provides the internal state of the

WSM to the external microprocessor. During periods

when the WSM is active, the status register can be polled

to determine the WSM status. Table 8 defines the sta-

tus register bits.

After monitoring the status register during a

PROGRAM/ERASE operation, the data appearing on

DQ0–DQ7 remains as status register data until a new

command is issued to the CSM. To return the device to

other modes of operation, a new command must be

issued to the CSM.

CSM OPERATIONS

The CSM decodes instructions for read array, read

protection configuration register, read query, read sta-

tus register, clear status register, program, erase, erase

suspend, erase resume, program suspend, program

resume, lock block, unlock block, and lock down block,

chip protection program, and set read configuration

on DQ0–DQ7 (see Table 3 for CSM codes and Table 4

for command definitions). During a PROGRAM or

ERASE cycle, the CSM informs the WSM that a PRO-

GRAM or ERASE cycle has been requested.

During a PROGRAM cycle, the WSM controls the

program sequences and the CSM responds to a PRO-

GRAM SUSPEND command only.

During an ERASE cycle, the CSM responds to an

ERASE SUSPEND command only. When the WSM has

completed its task, the WSM status bit (SR7) is set to a

logic HIGH level and the CSM responds to the full com-

Table 4

Command Definitions

FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND OPERATION ADDRESS DATA OPERATION ADDRESS DATA

READ ARRAY WRITE WA FFh

READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID

READ STATUS REGISTER WRITE BA 70h READ X SRD

CLEAR STATUS REGISTER WRITE BA 50h

READ QUERY WRITE QA 98h READ QA QD

BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h

PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA WD

PROGRAM/ERASE SUSPEND WRITE BA B0h

PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h

LOCK BLOCK WRITE BA 60h WRITE BA 01h

UNLOCK BLOCK WRITE BA 60h WRITE BA D0h

LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh

PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD

PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh

NOTE: 1. WA: Word address of memory location to be written, or read

2. IA: Identification code address

3. BA: Address within the block

4. ID: Identification code data

5. SRD: Data read from the status register

6. QA: Query code address

6. QD: Query code data

8. WD: Data to be written at the location WA

9. PA: Protection register address

10. LPA: Lock protection register address

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

(continued on the next page)

Table 5

Command Descriptions

CODE DEVICE MODE BUS CYCLE DESCRIPTION

10 Alt. Program Setup First Operates the same as a PROGRAM SETUP command.

20 Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next

command is not ERASE CONFIRM, the CSM will set both SR4 and SR5

of the status register to a “1,” place the device into read status

40 Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM

operation, and the second cycle latches addresses and data and

initiates the WSM to execute the program algorithm. The Flash

device outputs status register data on the falling edge of OE# or CE#,

whichever occurs first.

50 Clear Status First The WSM can set the block lock status (SR3), program status (SR4),

clear them to “0.” Issuing this command clears those bits to “0.”

60 Protection First Prepares the CSM for changes to the block locking status. If the next

Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK

Setup DOWN, then the CSM will set both the program and erase status

70 Read Status First Places the device into read status register mode. Reading the device

address presented to the device. The device will automatically enter

this mode after a PROGRAM or ERASE operation has been initiated.

90 Read Protection First Puts the device into the read protection configuration mode so that

Configuration reading the device will output the manufacturer/device codes or

block lock status.

98 Read Query First Puts the device into the read query mode so that reading the device

will output common flash interface information.

B0 Program/Erase First Suspends the currently executing PROGRAM/ERASE operation. The

Suspend status register will indicate when the operation has been successfully

suspended by setting either the program suspend (SR2) or erase

suspend (SR6), and the WSM status bit (SR7) to a “1” (ready). The

WSM will continue to idle in the suspend state, regardless of the state

of all input control signals except RST#, which will immediately shut

down the WSM and the remainder of the chip if RST# is driven to VIL.

C0 Program Device First Writes a specific code into the device protection register.

Protection Register

Lock Device First Locks the device protection register; data can no longer be changed.

Protection Register

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1 MEG x 16

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ADVANCE

Table 5

Command Descriptions (continued)

CODE DEVICE MODE BUS CYCLE DESCRIPTION

D0 Erase Confirm First If the previous command was an ERASE SETUP command, then the

CSM will close the address and data latches, and it will begin erasing

the block indicated on the address balls. During programming/erase,

the device will respond only to the READ STATUS REGISTER,

PROGRAM SUSPEND, or ERASE SUSPEND commands and will output

status register data on the falling edge of OE# or CE#, whichever

occurs last.

Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this

Resume command will resume the operation.

FF Read Array First During the array mode, array data will be output on the data bus.

01 Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock the block indicated on the

address bus.

2F Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock down the block indicated on

the address bus.

D0 Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and unlock the block indicated on the

address bus. If the block had been previously set to lock down, this

operation will have no effect.

00 Invalid/Reserved Unassigned command that should not be used.

mand set. The CSM stays in the current command state

until the microprocessor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when VPP is within its correct volt-

age range.

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the VPP status bit (SR3), the pro-

gram status bit (SR4), and the erase status bit (SR5) of

the status register. The CLEAR STATUS REGISTER com-

mand (50h) allows the external microprocessor to clear

these status bits and synchronize to the internal op-

erations. When the status bits are cleared, the device

returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-

ISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0–DQ7. Control signals CE# and OE# must

be at a logic LOW level (VIL), and WE# and RST# must be

at logic HIGH level (VIH) to read data from the array.

Data is available on DQ0–DQ15. Any valid address

within any of the blocks selects that address and allows

data to be read from that address. Upon initial power-

up, the device defaults to the read array mode.

READ CHIP PROTECTION IDENTIFICATION DATA

The chip identification mode outputs four types of

information: the manufacturer/device identifier, the

block locking status, the read configuration register,

and the protection register. Two bus cycles are required

for this operation: the chip identification data is read

by entering the command code 90h on DQ0–DQ7 and

the identification code address on the address lines.

Control signals CE# and OE# must be at a logic LOW

level (VIL), and WE# and RST# must be at a logic HIGH

level (VIH) to read data from the protection configura-

tion register. Data is available on DQ0–DQ15. To re-

turn to read array mode, write the read array command

code FFh on DQ0–DQ7. See Table 10 for further details.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

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ADVANCE

Taking RST# to VIL during programming aborts the

PROGRAM operation. During programming, VPP must

remain in the appropriate VPP voltage range as shown

in the recommended operating conditions table.

ERASE OPERATIONS

An ERASE operation must be used to initialize all

bits in an array block to “1s.” After BLOCK ERASE con-

firm is issued, the CSM responds only to an ERASE

SUSPEND command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accom-

plished only by blocks; data at single address locations

within the array cannot be erased individually. The

block to be erased is selected by using any valid ad-

dress within that block. Block erasure is initiated by a

command sequence to the CSM: BLOCK ERASE setup

(20h) followed by BLOCK ERASE CONFIRM (D0h) (see

Figure 6). A two-command erase sequence protects

against accidental erasure of memory contents.

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence

of events to complete the block erasure. During this

sequence, the block is programmed with logic 0s, data

is verified, all bits in the block are erased, and finally

verification is performed to ensure that all bits are cor-

rectly erased. The ERASE operation may be monitored

through the status register (see the Status Register

section).

During the execution of an ERASE operation the

ERASE SUSPEND command (B0h) can be entered to

direct the WSM to suspend the ERASE operation. Once

the WSM has reached the suspend state, it allows the

CSM to respond only to the READ ARRAY, READ STA-

TUS REGISTER, READ QUERY, READ CHIP PROTEC-

TION CONFIGURATION, PROGRAM SETUP, PRO-

GRAM RESUME, ERASE RESUME and LOCK SETUP

(see the Block Locking section). During the ERASE SUS-

PEND operation, array data must be read from a block

other than the one being erased. To resume the ERASE

operation, an ERASE RESUME command (D0h) must

be issued to cause the CSM to clear the suspend state

previously set (see Figure 7). It is also possible to sus-

pend an ERASE in any bank and initiate a WRITE to

another block in the same bank. After the completion

of a WRITE, an ERASE can be resumed by writing an

ERASE RESUME command.

READ QUERY

The read query mode outputs common flash inter-

face (CFI) data when the device is read (see Table 12).

Two bus cycles are required for this operation. It is

possible to access the query by writing the read query

command code 98h on DQ0–DQ7. Control signals CE#

and OE# must be at a logic LOW level (VIL), and WE# and

RST# must be at a logic HIGH level (VIH) to read data

from the query. The CFI data structure contains infor-

mation such as block size, density, command set, and

electrical specifications. To return to read array mode,

write the read array command code FFh on DQ0–DQ7.

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0–DQ7. Two bus cycles are required for

this operation: one to enter the command code and the

block address and a second to read the status register.

In a READ cycle, the address is latched and register

data is updated on the falling edge of OE# or CE#,

whichever occurs last. Register data is updated and

latched on the falling edge of OE# or CE#, whichever

occurs first.

PROGRAMMING OPERATIONS

There are two CSM commands for programming:

PROGRAM SETUP and ALTERNATE PROGRAM SETUP

(see Table 3).

After the desired command code is entered (10h or

40h command code on DQ0–DQ7), the WSM takes over

and correctly sequences the device to complete the

PROGRAM operation. The WRITE operation may be

monitored through the status register (see the Status

respond to a PROGRAM SUSPEND command until the

PROGRAM operation has been completed, after which

time all commands to the CSM become valid again.

The PROGRAM operation can be suspended by issuing

a PROGRAM SUSPEND command (B0h). Once the WSM

reaches the suspend state, it allows the CSM to re-

spond only to READ ARRAY, READ STATUS REGISTER,

READ PROTECTION CONFIGURATION, READ QUERY,

PROGRAM SETUP, or PROGRAM RESUME. During the

PROGRAM SUSPEND operation, array data should be

read from an address other than the one being pro-

grammed. To resume the PROGRAM operation, a PRO-

GRAM RESUME command (D0h) must be issued to

cause the CSM to clear the suspend state previously

set (see Figure 4 for programming operation and Figure

5 for program suspend and program resume).

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 6

Command State Machine Transition Table

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP

noititrap

etatstneserP

rehtoehtfo

noititrap

hF2

kcoL

nwod

mrifnoc

h10

kcoL

mrifnoc

h0C

PTO

putes

h06

kcolnU/kcoL

nwodkcoL/

h89

daeR

yreuq

h09

daeR

ecived

h05

raelC

sutats

retsiger

h07

daeR

sutats

h0B

margorP

esarE/

dnepsus

h0D

,mrifnocEB

,emuserE/P

mrifnocBLU

h02

esarE

putes

h04/h01

margorP

putes

hFF

daeR

yarra 7RS

ataD

nehw

daer

etatSedoM

yarradaeR

kcoL daeR

yreuq

daeR

yarra

daeR

sutats

yarradaeR

1yarrAyarrA

daeR

1puteS

2ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

3eldI

yarradaeR

yarradaeR 4 esarE

dnepsus

yarradaeR5

.gorP

dnepsus

yarradaeR

kcoL daeR

yreuq

daeR

yarra

daeR

sutats

yarradaeR

1IFCyreuQ

6puteS

7ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

8eldI

yarradaeR

yarradaeR 9 esarE

dnepsus

yarradaeR01.gorP

dnepsus

yarradaeR

kcoL daeR

yreuq

daeR

yarra

daeR

sutats

yarradaeR

1DIeciveD

11puteS

21ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

31eldI

yarradaeR

yarradaeR 41 esarE

dnepsus

yarradaeR51.gorP

dnepsus

yarradaeR

kcoL daeR

yreuq

daeR

yarra

daeR

sutats

yarradaeR

1sutatSsutatS

61puteS

71ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

81eldI

yarradaeR

yarradaeR 91 esarE

dnepsus

yarradaeR02.gorP

dnepsus

ysubretsigernoitcetorP 1sutatSputeS P

12eldI

ysubretsigernoitcetorP 0sutatSysuB22eldI

yarradaeRkcoL daeR

yreuq

daeR

yarra

daeR

sutats yarradaeR1sutatSenoD

32puteS

42ysuB

yarradaeR PTO

putes

kcoL daeR

yreuq

daeR

yarra

daeR

sutats

yarradaeR esarE

putes margorP

putes

daeR

yarra

1sutatSenoD

52eldI

yarradaeR

yarradaeR 62 esarE

dnepsus

yarradaeR72.gorP

dnepsus

(continued on the next page)

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 6

Command State Machine Transition Table (continued)

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP

noititrap

foetatstneserP

rehtoeht

noititrap

hF2

kcoL

nwod

mrifnoc

h10

kcoL

mrifnoc

H0C

PTO

putes

h06

kcolnU/kcoL

nwodkcoL/

h89

daeR

yreuq

h09

daeR

DIecived

h05

raelC

sutats

retsiger

h07

daeR

sutats

h0B

margorP

esarE/

dnepsus

h0D

,mrifnocEB

,emuserE/P

mrifnocBLU

h02

esarE

putes

h04/h01

margorP

putes

hFF

daeR

yarra 7RS

ataD

nehw

daer

etatSedoM

BLU/BLkcoLLBLU/BLkcoL1sutatSputeS

kcoL

82 ynA

etats

yarradaeR

kcoL daeR

yreuq DIdaeR daeR

yarra

daeR

sutats

yarradaeR

1sutatSrorrE

92puteS

03ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

13eldI

yarradaeR

yarradaeR 23 esarE

dnepsus

yarradaeR33.gorP

dnepsus

yarradaeR

kcoL daeR

yreuq DIdaeR daeR

yarra

daeR

sutats

yarradaeR

1sutatS /kcoL

kcolnU

43puteS

53ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

63eldI

yarradaeR

yarradaeR 73 esarE

dnepsus

yarradaeR83.gorP

dnepsus

ysuBmargorP 1sutatSputeS

margorP

93 ynA

etats

ysuBmargorPdaerSPysubmargorP0sutatSysuB04eldI

yarradaeR

kcoL daeR

yreuq DIdaeR daeR

yarra

daeR

sutats

yarradaeR

1sutatSenoD

14puteS

24ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

34eldI

yarradaeR

yarradaeR 44 esarE

dnepsus

yarradaeR54.gorP

dnepsus

daerdnepsusmargorP

yarra kcoL

margorP

dnepsus

daer

yreuq

margorP

dnepsus

DIdaer

margorP

dnepsus

daer

yarra

margorP

dnepsus

daer

sutats

margorP

dnepsus

daer

yarra

ysubmargorP daerdnepsusmargorP

yarra 1sutatS daeR

sutats

margorP

dnepsus

64puteS

74eldI

84 esarE

dnepsus

(continued on the next page)

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 6

Command State Machine Transition Table (continued)

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP

noititrap

etatstneserP

rehtoehtfo

noititrap

hF2

kcoL

nwod

mrifnoc

h10

kcoL

mrifnoc

h0C

PTO

putes

h06

kcolnU/kcoL

nwodkcoL/

h89

daeR

yreuq

h09

daeR

DIecived

h05

raelC

sutats

retsiger

h07

daeR

sutats

h0B

margorP

esarE/

dnepsus

h0D

,mrifnocEB

,emuserE/P

mrifnocBLU

h02

esarE

putes

h04/h01

margorP

putes

hFF

daeR

yarra 7RS

ataD

nehw

daer

etatSedoM

daerdnepsusmargorP

yarra kcoL

margorP

dnepsus

daer

yreuq

margorP

dnepsus

DIdaer

margorP

dnepsus

daer

yarra

margorP

dnepsus

daer

sutats

margorP

dnepsus

daer

yarra

ysubmargorP daerdnepsusmargorP

yarra 1yarrA daeR

yarra

margorP

dnepsus

94puteS

05eldI

15 esarE

dnepsus

daerdnepsusmargorP

yarra kcoL

margorP

dnepsus

daer

yreuq

margorP

dnepsus

DIdaer

margorP

dnepsus

daer

yarra

margorP

dnepsus

daer

sutats

margorP

dnepsus

daer

yarra

ysubmargorP daerdnepsusmargorP

yarra

DIdaeR

25puteS

35eldI

45 esarE

dnepsus

daerdnepsusmargorP

yarra kcoL

margorP

dnepsus

daer

yreuq

margorP

dnepsus

DIdaer

margorP

dnepsus

daer

yarra

margorP

dnepsus

daer

sutats

margorP

dnepsus

daer

yarra

ysubmargorP daerdnepsusmargorP

yarra 1IFC daeR

yreuQ

55puteS

65eldI

75 esarE

dnepsus

BLU/BLrorreesarE esarE

rorre ysubesarErorreesarE

1sutatSputeS

esarE

85eldI

yarradaeR

kcoL daeR

yreuq DIdaeR daeR

yarra

daeR

sutats

yarradaeR

sutatS

rorrE

95puteS

06ysuB

yarradaeR PTO

putes yarradaeR esarE

putes margorP

putes

daeR

yarra

16eldI

yarradaeR

yarradaeR 26 esarE

dnepsus

yarradaeR36.gorP

dnepsus

yarradaeR

kcoL daeR

yreuq DIdaeR daeR

yarra

daeR

sutats

yarradaeR

sutatS

enoD

46puteS

56ysuB

yarradaeR PTO

putes yarradaeResarE margorP

putes

daeR

yarra

66eldI

yarradaeR

yarradaeR 76 esarE

dnepsus

yarradaeR86.gorP

dnepsus

ysubesarekcolB daerSE

sutats ysubesarE0sutatSysuB96eldI

(continued on the next page)

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 6

Command State Machine Transition Table

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP

noititrap

etatstneserP

rehtoehtfo

noititrap

hF2

kcoL

nwod

mrifnoc

h10

kcoL

mrifnoc

h0C

PTO

putes

h06

kcolnU/kcoL

nwodkcoL/

h89

daeR

yreuq

h09

daeR

DIecived

h05

raelC

sutats

retsiger

h07

daeR

sutats

h0B

margorP

esarE/

dnepsus

h0D

,mrifnocEB

,emuserE/P

mrifnocBLU

h02

esarE

putes

h04/h01

margorP

putes

hFF

daeR

yarra 7RS

ataD

nehw

daer

etatSedoM

yarradaerdnepsusesarEkcoL

esarE

dnepsus

daer

yreuq

esarE

dnepsus

DIdaer

esarE

dnepsus

daer

yarra

esarE

dnepsus

daer

sutats

daerSE

yarra ysubesarE daerdnepsusesarE

yarra

sutatS daeR

sutats

esarE

dnepsus

07puteS

yarradaerdnepsusesarE 17ysuB

daerSE

yarra ysubesarE

daer

yarra

.gorP

putes

daer

yarra

27eldI

yarradaerdnepsusesarE 37 .gorP

dnepsus

yarradaerdnepsusesarEkcoL

esarE

dnepsus

daer

yreuq

esarE

dnepsus

DIdaer

esarE

dnepsus

daer

yarra

esarE

dnepsus

daer

sutats

daerSE

yarra ysubesarE daerdnepsusesarE

yarra

1yarrA daeR

arra

47puteS

yarradaerdnepsusesarE 57ysuB

daerSE

yarra ysubesarE

daer

yarra

.gorP

putes

daer

yarra

67eldI

yarradaerdnepsusesarE 77 .gorP

dnepsus

yarradaerdnepsusesarEkcoL

esarE

dnepsus

daer

yreuq

esarE

dnepsus

DIdaer

esarE

dnepsus

daer

yarra

esarE

dnepsus

daer

sutats

daerSE

yarra ysubesarE daerdnepsusesarE

yarra

DI daeR

87puteS

yarradaerdnepsusesarE 97ysuB

daerSE

yarra ysubesarE

daer

yarra

.gorP

putes

daer

yarra

08eldI

yarradaerdnepsusesarE 18 .gorP

dnepsus

yarradaerdnepsusesarEkcoL

esarE

dnepsus

daer

yreuq

esarE

dnepsus

DIdaer

esarE

dnepsus

daer

yarra

esarE

dnepsus

daer

sutats

daerSE

yarra ysubesarE daerdnepsusesarE

yarra

1IFC daeR

yreuq

28puteS

yarradaerdnepsusesarE 38ysuB

daerSE

yarra ysubesarE

daer

yarra

.gorP

putes

daer

yarra

48eldI

yarradaerdnepsusesarE 58 .gorP

dnepsus

NOTE: 1. If the chip is configured as a top boot block device, it is not possible to read the CFI data and device identification data

when bank a is in program/erase mode.

2. If the chip is configured as a top boot block device, it is not possible to program the OTP when bank a is in read mode.

3. If the chip is configured as a top boot block device, it is possible to read bank b when bank a is in program/erase mode,

and vice versa.

4. If the chip is configured as a bottom boot block device, it is possible to read the CFI and device identification data

when bank b is in program/erase mode.

5. If the chip is configured as a bottom boot block device, it is possible to program the OTP area when bank b is in read

mode.

6. If the chip is configured as a bottom boot block device, it is possible to read bank b when bank a is in program/erase

mode, and vice versa.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 8

Status Register Bit Definition

WSMS ESS ES PS VPPS PSS BLS R

76543210

STATUS

BIT # STATUS REGISTER BIT DESCRIPTION

SR7 WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word

1 = Ready program or block erase completion, before checking

0 = Busy program or erase status bits.

SR6 ERASE SUSPEND STATUS (ESS) When ERASE SUSPEND is issued, WSM halts execution and

1 = BLOCK ERASE Suspended sets both WSMS and ESS bits to “1.” ESS bit remains set to

0 = BLOCK ERASE in “1” until an ERASE RESUME command is issued.

Progress/Completed

SR5 ERASE STATUS (ES) When this bit is set to “1,” WSM has applied the maximum

1 = Error in Block Erasure number of erase pulses to the block and is still unable to

0 = Successful BLOCK ERASE verify successful block erasure.

SR4 PROGRAM STATUS (PS) When this bit is set to “1,” WSM has attempted but failed

1 = Error in PROGRAM to program a word.

0 = Successful PROGRAM

SR3 VPP STATUS (VPPS) The VPP status bit does not provide continuous indication

1 = VPP Low Detect, Operation Abort of the VPP level. The WSM interrogates the VPP level only

0 = VPP = OK after the program or erase command sequences have been

entered and informs the system if VPP has not been

switched on. The VPP level is also checked before the

PROGRAM/ERASE operation is verified by the WSM.

SR2 PROGRAM SUSPEND STATUS (PSS) When PROGRAM SUSPEND is issued, WSM halts execution

1 = PROGRAM Suspended and sets both WSMS and PSS bits to “1.” PSS bit remains

0 = PROGRAM in Progress/Completed set to “1” until a PROGRAM RESUME command is issued.

SR1 BLOCK LOCK STATUS (BLS) If a PROGRAM or ERASE operation is attempted to one of

1 = PROGRAM/ERASE Attempted on a the locked blocks, this is set by the WSM. The operation

Locked Block; Operation Aborted specified is aborted and the device is returned to read

0 = No Operation to Locked Blocks status mode.

SR0 RESERVED FOR FUTURE This bit is reserved for future use.

ENHANCEMENT

Table 7

Bus Operations

MODE RST# CE# OE# WE# ADDRESS DQ0–DQ15

Read (array, status registers, VIH VIL VIL VIH XDOUT

device identification register, or

query)

Standby VIH VIH X X X High-Z

Output Disable VIH VIH X X X High-Z

Reset VIL X X X X High-Z

Write VIH VIL VIH VIL XDIN

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Figure 4

Automated Word Programming

Flowchart

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

BUS

OPERATION COMMAND COMMENTS

WRITE WRITE Data = 40h or 10h

PROGRAM Addr = Address of word to be

SETUP programmed

WRITE WRITE Data = Word to be

DATA programmed

Addr = Address of word to be

programmed

READ Status register data

Toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready, 0 = Busy

Repeat for subsequent words.

Write FFh after the last word programming operation

to reset the device to read array mode.

BUS

OPERATION COMMAND COMMENTS

Standby Check SR1

1 = Detect locked block

Standby Check SR3

1 = Detect V

LOW

Standby Check SR4

1 = Word program error

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Issue READ ARRAY

Command

PROGRAM

Complete

Finished

Reading

Issue PROGRAM

RESUME Command

YES

SR2 = 1?

Start

PROGRAM Resumed

Read Status Register

Bits

Issue PROGRAM

SUSPEND Command

YES

SR7 = 1?

Figure 5

PROGRAM SUSPEND/

PROGRAM RESUME Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE PROGRAM Data = B0h

SUSPEND

READ Status register data

Toggle OE# or CE# to update

status register.

Standby Check SR7

1 = Ready

Standby Check SR2

1 = Suspended

WRITE READ Data = FFh

ARRAY

READ Read data from block other

than that being programmed.

WRITE PROGRAM Data = D0h

RESUME

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR 7 = 1?

Start

BLOCK ERASE Passed

Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

ERASE

SUSPEND Loop

YES

SR1 = 0?

YES

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted

on a Locked Block

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

Figure 6

BLOCK ERASE Flowchart

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

BUS

OPERATION COMMAND COMMENTS

WRITE WRITE Data = 20h

ERASE Block Addr = Address

SETUP within block to be erased

WRITE ERASE Data = D0h

Block Addr = Address

within block to be erased

READ Status register data

Toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready, 0 = Busy

Repeat for subsequent blocks.

Write FFh after the last BLOCK ERASE operation to

reset the device to read array mode.

BUS

OPERATION COMMAND COMMENTS

Standby Check SR1

1 = Detect locked block

Standby Check SR32

1 = Detect VPP block

Standby Check SR53

1 = BLOCK ERASE error

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

READ

PROGRAM

Issue READ ARRAY

Command

PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM

Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 1)

YES

SR7 = 1?

Figure 7

ERASE SUSPEND/ERASE RESUME

Flowchart

NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.

2. See Word Programming Flowchart for complete programming procedure.

BUS

OPERATION COMMAND COMMENTS

WRITE ERASE Data = B0h

SUSPEND

READ Status register data

Toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready

Standby Check SR6

1 = Suspended

WRITE READ Data = FFh

ARRAY

READ Read data from block

other than that being

erased.

WRITE ERASE Data = D0h

RESUME

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

READ-WHILE-WRITE/ERASE

CONCURRENCY

It is possible for the device to read from one bank

while erasing/writing to another bank. Once a bank

enters the WRITE/ERASE operation, the other bank

automatically enters read array mode. For example,

during a READ CONCURRENCY operation, if a PRO-

GRAM/ERASE command is issued in bank a, then bank

a changes to the read status mode and bank b defaults

to the read array mode. The device will read from bank

b if the latched address resides in bank b (see Figure 8).

Similarly, if a PROGRAM/ERASE command is issued in

bank b, then bank b changes to read status mode and

bank a defaults to read array mode. When returning to

bank a, the device will read PROGRAM/ERASE status if

the latched address resides in bank a. A correct bank

address must be specified to read status register after

returning from concurrent read in the other bank.

When reading the CFI data area, or the chip protec-

tion register, the possible concurrent operations are

reported in Figures 9a and 9b.

Figure 8

READ-While-WRITE Concurrency

Bank a

1 - Erasing/writing to bank a

2 - Erasing in bank a can be

suspended, and a WRITE to

another block in bank a

can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

1 - Reading bank a

Bank b

1 - Reading from bank b

1 - Erasing/writing to bank b

2 - Erasing in bank b can be

suspended, and a WRITE to

another block in bank b

can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

Figure 9a

Top Boot Block Device

Figure 9b

Bottom Boot Block Device

Reading the CFI

or Chip Protection

Bank aBank b

Not Supported Not Supported

Reading the CFI

or Chip Protection

Bank aBank b

Not Supported Supported

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

BLOCK LOCKING

The MT28F162P2 Flash memory provides a flexible

locking scheme which allows each block to be individu-

ally locked or unlocked with no latency.

The device offers two-level protection for the blocks.

The first level allows software-only control of block lock-

ing (for data which needs to be changed frequently),

while the second level requires hardware interaction

before locking can be changed (code which does not

require frequent updates).

Control signals WP#, DQ0, and DQ1 define the state

of a block; for example, state [001] means WP# = 0,

DQ0 = 0 and DQ1 = 1.

Table 9 defines all of the possible locking states.

NOTE: All blocks are software-locked upon power-

up sequence completion.

LOCKED STATE

After a power-up sequence completion, or after a

reset sequence, all blocks are locked (states [001] or

[101]). This means full protection from alteration. Any

PROGRAM or ERASE operations attempted on a locked

block will return an error on bit SR1 of the status regis-

ter. The status of a locked block can be changed to

unlocked or lock down using the appropriate software

commands. Writing the lock command sequence, 60h

followed by 01h, can lock an unlocked block.

UNLOCKED STATE

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to

ERASE operations, but their protection status cannot

be changed using software commands alone. A locked

or unlocked block can be locked down by writing the

lock down command sequence, 60h followed by 2Fh.

Locked down blocks revert to the locked state when the

device is reset or powered down.

The LOCK DOWN function is dependent on the WP#

input. When WP# = 0, blocks in lock down [011] are

protected from program, erase, and lock status

changes. When WP# = 1, the LOCK DOWN function is

disabled ([111]) and locked down blocks can be indi-

vidually unlocked by a software command to the [110]

state, where they can be erased and programmed.

These blocks can then be relocked [111] and unlocked

[110] as desired as long as WP# remains HIGH. When

WP# goes LOW, blocks that were previously locked down

return to the lock down state [011] regardless of any

changes made while WP# was HIGH. Device reset or

power-down resets all locks, including those in lock

down, to the locked state (see Table 9).

READING A BLOCK’S LOCK STATUS

The lock status of every block can be read in the

read device identification mode. To enter this mode,

Table 9

Block Locking State Transition

ERASE/PROGRAM LOCK

WP# DQ1 DQ0 NAME ALLOWED LOCK UNLOCK DOWN

0 0 0 Unlocked Yes To [001] No Change To [011]

0 0 1 Locked (Default) No No Change To [000] To [011]

0 1 1 Lock Down No No Change No Change No Change

1 0 0 Unlocked Yes To [101] No Change To [111]

1 0 1 Locked No No Change To [100] To [111]

1 1 0 Lock Down Yes To [111] No Change To [111]

Disabled

1 1 1 Lock Down No No Change To [110] No Change

Disabled

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

write 90h to the device. Subsequent READs at block

address +00002 will output the lock status of that block.

The lowest two outputs, DQ0 and DQ1, represent the

lock status. DQ0 indicates the block lock/unlock status

and is set by the LOCK command and cleared by the

UNLOCK command. It is also automatically set when

entering lock down. DQ1 indicates lock down status

and is set by the LOCK DOWN command. It can only be

cleared by reset or power-down, not by software. Table

9 shows the locking state transition scheme.

LOCKING OPERATIONS DURING ERASE

SUSPEND

Changes to block lock status can be performed dur-

ing an ERASE SUSPEND by using the standard locking

command sequences to unlock, lock, or lock down. This

is useful in the case when another block needs to be

updated while an ERASE operation is in progress.

To change block locking during an ERASE opera-

tion, first write the ERASE SUSPEND command (B0h),

then check the status register until it indicates that the

ERASE operation has been suspended. Next, write the

desired lock command sequence to block lock, and the

lock status will be changed. After completing any de-

sired LOCK, READ, or PROGRAM operations, resume

the ERASE operation with the ERASE RESUME com-

mand (D0h).

If a block is locked or locked down during an ERASE

SUSPEND on the same block, the locking status bits

will be changed immediately. When the ERASE is re-

sumed, the ERASE operation will complete.

A locking operation cannot be performed during a

PROGRAM SUSPEND.

CHIP PROTECTION REGISTER

A 128-bit protection register can be used to fulfill

the security considerations in the system (preventing

the device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the

manufacturing site with a unique 64-bit unchange-

able number. The other segment is left blank for cus-

tomers to program as desired. (See Figure 10).

Figure 10

Protection Register Memory Map

4 Words

Factory-Programmed

4 Words

User-Programmed

PR Lock

88h

85h

84h

81h

80h

ITEM ADDRESS DATA

Manufacturer Code (x16) 00000h 002Ch

Device Code 00001h

·Top boot configuration 44A6h

·Bottom boot configuration 44A7h

Block Lock Configuration2XX002h Lock

·Block is unlocked DQ0 = 0

·Block is locked DQ0 = 1

·Block is locked down DQ1 = 1

Chip Protection Register Lock 80h PR Lock

Chip Protection Register 1 81h–84h Factory Data

Chip Protection Register 2 85h–88h User Data

NOTE: 1. Other locations within the configuration address space are reserved by

Micron for future use.

2. “XX” specifies the block address of lock configuration.

Table 10

Chip Protection Configuration Addressing1

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

READING THE CHIP PROTECTION REGISTER

The chip protection register is read in the device

identification mode. To enter this mode, load the 90h

command. Once in this mode, READ cycles from ad-

dresses shown in Table 10 retrieve the specified infor-

mation. To return to the read array mode, write the

READ ARRAY command (FFh).

ASYNCHRONOUS READ CYCLE

When accessing addresses in a random order or

when switching between pages, the access time is given

by tAA.

When CE# and OE# are LOW, the data is placed on

the data bus and the processor can read the data.

PAGE READ MODE

The initial portion of the page mode cycle is the

same as the asynchronous access cycle. Holding CE#

LOW and toggling addresses A0–A1 allows random ac-

cess of other words in the page. The page word size is

eight words.

VPP / VCC PROGRAM AND ERASE

VOLTAGES

The MT28F162P2 Flash memory provides in-sys-

tem programming and erase with VPP in the 0.9V–2.2V

range. The 12V VPP mode programming is offered for

compatibility with existing programming equipment.

The device can withstand 100,000 WRITE/ERASE

operations when VPP = VPP1 or 100 WRITE/ERASE opera-

tions and 10 cumulative hours when VPP = VPP2.

In addition to the flexible block locking, the VPP pro-

gramming voltage can be held low for absolute hard-

ware write protection of all blocks in the flash device.

When VPP is below VPPLK, any PROGRAM or ERASE op-

eration will result in an error, prompting the correspond-

ing status register bit (SR3) to be set.

During WRITE and ERASE operations, the WSM

monitors the VPP voltage level. WRITE/ERASE opera-

tions are allowed only when VPP is within the ranges

specified in Table 11.

When VCC is below VLKO, any WRITE/ERASE opera-

tion will be disabled.

STANDBY MODE

Icc supply current is reduced by applying a logic

HIGH level on CE# and RST# to enter the standby

mode. In the standby mode, the outputs are placed in

High-Z. Applying a CMOS logic HIGH level on CE# and

RST# reduces the current to ICC2 (MAX). If the device is

deselected during an ERASE operation or during pro-

gramming, the device continues to draw current until

the operation is complete.

AUTOMATIC POWER SAVE MODE (APS)

Substantial power savings are realized during peri-

ods when the array is not being read and the device is in

the active mode. During this time the device switches

to the automatic power save mode. When the device

switches to this mode, ICC is reduced to ICC2. The low

level of power is maintained until another operation is

initiated. In this mode, the I/Os retain the data from

the last memory address read until a new address is

read. This mode is entered automatically if no address

or control signals toggle.

DEVICE RESET

To correctly reset the MT28F162P2 Flash memory,

the RST# signal must be asserted (RST# = VIL) for a

minimum of tRP. After reset, the device can be accessed

for a READ operation with a delayed access time of

tRWH from the rising edge of RST#. The circuitry used

for generating the RST# signal needs to be common

with the rest of the system reset to ensure that correct

system initialization occurs. Please refer to the timing

diagram for further details.

POWER-UP SEQUENCE

The following power-up sequence must be applied

to initialize internal chip operations:

• At power-up, RST# should be kept at VIL for 2µs

after VCC reaches the 1.65V level.

•VCCQ will not come up before VCC.

•VPP must be kept at VIL.

• When the power-up sequence is completed, RST#

should be brought to VIH.

Table 11

VPP Range (V)

MIN MAX

In-System 0.9 2.2

In-Factory 11.4 12.6

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

ABSOLUTE MAXIMUM RATINGS*

Voltage to Any Ball Except VCC and VPP

with Respect to VSS ....................... -0.5V to +2.45V

VPP Voltage (for BLOCK ERASE and PROGRAM

with Respect to VSS) ................. -0.5V to +13.5V**

VCC and VCCQ Supply Voltage

with Respect to VSS ....................... -0.3V to +2.45V

Output Short Circuit Current............................... 100mA

Operating Temperature Range ............ -40oC to +85oC

Storage Temperature Range............... -55oC to +125oC

Soldering Cycle .......................................... 260oC for 10s

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

**Maximum DC voltage on VPP may overshoot to +13.5V

for periods <20ns.

OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNITS NOTE

Operating temperature tA -40 +85 oC

VCC supply voltage VCC 1.65 2.20 V

I/O supply voltage (VCC = 1.65V–1.95V) VCCQ 1.65 1.95 V

I/O supply voltage (VCC = 1.80V–2.20V) VCCQ 1.80 2.20 V

VPP voltage VPP10.9 2.2 V

VPP in-factory programming voltage VPP211.4 12.6 V

Block erase cycling VPP = VPP1VPP1– 100,000 Cycles

VPP = VPP2VPP2– 100 Cycles 1

NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

DC CHARACTERISTICS

VCC/VCCQ = 1.65V–1.95V or

1.80V–2.20V

PARAMETER SYMBOL MIN MAX UNITS

Input Low Voltage VIL -0.4 0.4 V

Input High Voltage VIH VCCQ - 0.4V VCCQ + 0.3V V

Output Low Voltage VOL -0.10 0.10 V

IOL = 100µA

Output High Voltage VOH VCCQ - 0.1V – V

IOH = -100µA

VPP Lock Out Voltage VPPLK – 0.4 V

VPP During Program/Erase VPP10.9 2.2 V

Operations VPP211.4 12.6 V

VCC Program/Erase Lock Voltage VLKO 1.0 – V

Input Leakage Current IL–1mA

Output Leakage Current IOZ 0.2 1 mA

VCC Read Current ICC1

Asynchronous Random Read, 80ns cycle – 15 mA

Asynchronous Page Read, 80ns/30ns cycle – 5 mA

VCC Standby Current (12µA TYP) ICC2–50mA

Program Current ICC3 + IPP3–20mA

Erase Current ICC4 + IPP4–20mA

VCC Erase Suspend Current ICC5–50mA

VCC Program Suspend Current ICC6–50mA

Read-While-Write Current ICC7–45mA

VPP Read Current IPP1

VPP ≤ VCC 0.5 1 mA

VPP ³ VCC 50 200 mA

VPP Standby Current IPP20.5 1 mA

VPP Erase Suspend Current IPP5

VPP = VPP10.5 1 mA

VPP = VPP250 200 mA

VPP Program Suspend Current IPP6

VPP = VPP10.5 1 mA

VPP = VPP250 200 mA

NOTE: 1. All currents are in RMS unless otherwise noted.

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

READ CYCLE TIMING REQUIREMENTS

VCC = 1.65V–1.95V

-80 -90

PARAMETER SYMBOL MIN MAX MIN MAX UNITS

Address to output delay tAA 85 95 ns

CE# LOW to output delay tACE 85 95 ns

Page address access tAPA 30 35 ns

OE# LOW to output delay tAOE 25 30 ns

RST# HIGH to output delay tRWH 200 200 ns

RST# LOW pulse width tRP 200 200 ns

CE# or OE# HIGH to output High-Z tOD 25 25 ns

Output hold from address, CE# or OE# change tOH 0 0 ns

CE# HIGH between subsequent synchronous READs tCBPH 20 20 ns

READ cycle time tRC 85 95 ns

I/O

14.5K

30pF

14.5K

Figure 11

Output Load Circuit

READ CYCLE TIMING REQUIREMENTS

VCC = 1.80V–2.20V

-80 -90

PARAMETER SYMBOL MIN MAX MIN MAX UNITS

Address to output delay tAA 80 90 ns

CE# LOW to output delay tACE 80 90 ns

Page address access tAPA 30 35 ns

OE# LOW to output delay tAOE 25 30 ns

RST# HIGH to output delay tRWH 150 150 ns

RST# LOW pulse width tRP 150 150 ns

CE# or OE# HIGH to output High-Z tOD 25 25 ns

Output hold from address, CE# or OE# change tOH 0 0 ns

CE# HIGH between subsequent synchronous READs tCBPH 20 20 ns

READ cycle time tRC 80 90 ns

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

WRITE CYCLE TIMING REQUIREMENTS

-80/-90

VCC = 1.65V–1.95V or

1.80V–2.20V

PARAMETER SYMBOL MIN MAX UNITS

tRST# HIGH recovery to WE# going LOW tRS 150 ns

CE# setup to WE# going LOW tCS 0 ns

Write pulse width tWP 50 ns

Data setup to WE# going HIGH tDS 50 ns

Address setup to WE# going HIGH tAS 50 ns

CE# hold from WE# HIGH tCH 0 ns

Data hold from WE# HIGH tDH 0 ns

Address hold from WE# HIGH tAH 9 ns

Write pulse width HIGH tWPH 30 ns

WP# setup to WE# going HIGH tRHS 200 ns

VPP setup to WE# going HIGH tVPS 200 ns

Write recovery before READ tWOS 50 ns

WP# hold from valid SRD tRHH 0 ns

VPP hold from valid SRD tVPH 0 ns

WE# HIGH to data valid tWB tAA + 50 ns

ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS

-80/-90

VCC = 1.65V–1.95V or

1.80V–2.20V

PARAMETER TYP MAX UNITS

4KW parameter block program time 0.1 0.3 s

32KW parameter block program time 0.8 2.4 s

Word program time 8 185 µs

4KW parameter block erase time 0.5 6 s

32KW parameter block erase time 1 6 s

Program suspend latency 510µs

Erase suspend latency 520µs

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

SINGLE ASYNCHRONOUS READ OPERATION

READ TIMING PARAMETERS

VCC = 1.65V–1.95V

-80 -90

SYMBOL MIN MAX MIN MAX UNITS

tAA 85 95 ns

tACE 85 95 ns

tAOE 25 30 ns

tRWH 200 200 ns

tOD 25 25 ns

tOH 0 0 ns

tRC 85 95 ns

VALID ADDRESS

UNDEFINED

ACE

A0–A19

OE#

CE#

WE#

RWH

DQ0–DQ15

RP#

VALID OUTPUT

High-Z

AOE

READ TIMING PARAMETERS

VCC = 1.80V–2.20V

-80 -90

SYMBOL MIN MAX MIN MAX UNITS

tAA 80 90 ns

tACE 80 90 ns

tAOE 25 30 ns

tRWH 150 150 ns

tOD 25 25 ns

tOH 0 0 ns

tRC 80 90 ns

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

ASYNCHRONOUS PAGE MODE READ OPERATION

VALID ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

UNDEFINED

ACE

APA

AOE

A0-A1

F_OE#

F_CE#

F_WE#

VALID ADDRESS

A2–A19 V

RMH

DQ0–DQ15

F_RP #

High-Z

READ TIMING PARAMETERS

VCC = 1.65V–1.95V

-80 -90

SYMBOL MIN MAX MIN MAX UNITS

tAA 85 95 ns

tACE 85 95 ns

tAOE 25 30 ns

tRWH 200 200 ns

tOD 25 25 ns

tOH 0 0 ns

tRC 85 95 ns

READ TIMING PARAMETERS

VCC = 1.80V–2.20V

-80 -90

SYMBOL MIN MAX MIN MAX UNITS

tAA 80 90 ns

tACE 80 90 ns

tAOE 25 30 ns

tRWH 150 150 ns

tOD 25 25 ns

tOH 0 0 ns

tRC 80 90 ns

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

TWO-CYCLE PROGRAMMING/ERASE OPERATION

VALID ADDRESS VALID ADDRESS VALID ADDRESS

UNDEFINED

RHS

A0–A19

OE#

CE#

WE#

RP#

WP#

IPPLK

IPPH

WPH

WOS

CMD CMD/

DATA

DQ0–DQ15

RHH

VPS

VPPH

STATUS

High-Z

-80/-90

VCC = 1.65V–1.95V

or 1.80V–2.20V

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

-80/-90

VCC = 1.65V–1.95V

or 1.80V–2.20V

SYMBOL MIN MAX UNITS

tRS 150 ns

tCS 0 ns

tWP 50 ns

tDS 50 ns

tAS 50 ns

tCH 0 ns

tAH 9 ns

tRHS 200 ns

tVPS 200 ns

tWOS 50 ns

tRHH 0 ns

tVPH 0 ns

tWB tAA+50 ns

tDH 0 ns

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

RESET OPERATION

OE#

DQ0–DQ15

VIH

VIL

RST# VIH

VIL

CE# VIH

VIL

VOH

VOL

tRWH

tRP

READ AND WRITE TIMING PARAMETERS

-80/-90

VCC = 1.80V–2.20V VCC = 1.65V–1.95V

SYMBOL MIN MAX MIN MAX UNITS

tRWH 150 200 ns

tRP 150 200 ns

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 12

CFI

OFFSET DATA DESCRIPTION

00 2Ch Manufacturer code

01 A6h Top boot block device code

A7h Bottom boot block device code

02–0F reserved Reserved

10, 11 0051, 0052 “QR”

12 0059 “Y”

13, 14 0003, 0000 Primary OEM command set

15, 16 0039, 0000 Address for primary extended table

17, 18 0000, 0000 Alternate OEM command set

19, 1A 0000, 0000 Address for OEM extended table

1B 0017 VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

1C 0022 VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

1D 00B4 VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

1E 00C6 VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

1F 0003 Typical timeout for single byte/word program, 2n µs, 0000 = not supported

20 0000 Typical timeout for maximum size multiple byte/word program, 2n µs, 0000 = not

supported

21 0009 Typical timeout for individual block erase, 2n ms, 0000 = not supported

22 0000 Typical timeout for full chip erase, 2n ms, 0000 = not supported

23 000C Maximum timeout for single byte/word program, 2n µs, 0000 = not supported

24 0000 Maximum timeout for maximum size multiple byte/word program, 2n µs, 0000 = not

supported

25 0003 Maximum timeout for individual block erase, 2n ms, 0000 = not supported

26 0000 Maximum timeout for full chip erase, 2n ms, 0000 = not supported

27 0015 Device size, 2n bytes

28 0001 Bus Interface x16 = 1

29 0000 Flash device interface description 0000 = async

2A, 2B 0000, 0000 Maximum number of bytes in multibyte program or page, 2n

2C 0003 Number of erase block regions within device (4K words and 32K words)

2D, 2E 0017, 0000 Top boot block device erase block region information 1, 8 blocks …

0007, 0000 Bottom boot block device erase block region information 1, 8 blocks …

2F, 30 0000, 0001 Top boot block device …..of 8KB

0020, 0000 Bottom boot block device …..of 8KB

31, 32 0006, 0000 15 blocks of ….

33, 34 0000, 0001 ……64KB

(continued on the next page)

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1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 12

CFI (continued)

OFFSET DATA DESCRIPTION

35, 36 0007, 0000 Top boot block device 56 block of

0017, 0000 Bottom boot block device 48 block of

37, 38 0020, 0000 Top boot block device ……64KB

0000, 0001 Bottom boot block device ……64KB

39, 3A 0050, 0052 “PR”

3B 0049 “I”

3C 0030 Major version number, ASCII

3D 0031 Minor version number, ASCII

3E 00E6 Optional Feature and Command Support

3F 0002 Bit 0 Chip erase supported no = 0

40 0000 Bit 1 Suspend erase supported = yes = 1

41 0000 Bit 2 Suspend program supported = yes = 1

Bit 3 Chip lock/unlock supported = no = 0

Bit 4 Queued erase supported = no = 0

Bit 5 Instant individual block locking supported = yes = 1

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

Bit 8 Synchronous read supported = no = 0

Bit 9 Simultaneous operation supported = yes = 1

42 0001 Program supported after erase suspend = yes

43, 44 0003, 0000 Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

45 0018 VCC supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in

BCD

46 00C0 VPP supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in

BCD

47 0001 Number of protection register fields in JEDEC ID space

48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address

4A, 4B 0003, 0003 2n factory programmed bytes, 2n user programmable bytes

4C 0003 Background Operation

0000 = Not used

0001 = 4% block split

0002 = 12% block split

0003 = 25% block split

0004 = 50% block split

4D 0000 Burst Mode Type

0000 = No burst mode

00x1 = 4 words MAX

00x2 = 8 words MAX

00x3 = 16 words MAX

001x = Linear burst, and/or

002x = Interleaved burst, and/or

004x = Continuous burst

(continued on the next page)

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

Table 12

CFI (continued)

OFFSET DATA DESCRIPTION

4E 0002 Page Mode Type

0000 = No page mode

0001 = 4-word page

0002 = 8-word page

0003 = 16-word page

0004 = 32-word page

4F 0000 Not used

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.

48-BALL FBGA

0.80 ±0.075

0.10 CC

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or

62% Sn, 37% Pb, 2%Ag

SOLDER BALL PAD: Ø 0.27mm

PIN #1 ID

ENCAPSULATION MATERIAL: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

0.75

TYP

3.75

1.875 ±0.05

6.00 ±0.05

PIN #1 ID

0.75

TYP

3.50 ±0.052.625 ±0.05

5.25

7.00 ±.10

0.3548X TYP

12.00 ± 0.10

1.20 MAX

BALL A8

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE

PRE-REFLOW DIAMETER

IS Ø 0.33

BALL A1

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark, and the Micron logo and M logo are trademarks of Micron Technology, Inc.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

1 Meg x 16 Page Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 MEG x 16

PAGE FLASH MEMORY

ADVANCE

REVISION HISTORY

Original document, Pub. 6/01, Advance....................................................................................................................... 6/01