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MOS INTEGRATED CIRCUIT
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
18M-BIT DDRII SRAM
2-WORD BURST OPERATION
Document No. M19866EJ1V0DS00 (1st edition)
Date Published July 2009
Printed in Japan
DATA SHEET
2009
Description
The
μ
PD44164082A-A is a 2,097,152-word by 8-bit, the
μ
PD44164092A-A is a 2,097,152-word by 9-bit, the
μ
PD44164182A-A is a 1,048,576-word by 18-bit and the
μ
PD44164362A-A is a 524,288-word by 36-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44164082A-A,
μ
PD44164092A-A,
μ
PD44164182A-A and
μ
PD44164362A-A integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the
positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA package (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
User programmable impedance output
Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Operating ambient temperature: Commercial TA = 0 to +70°C (-E33, -E37, -E40, -E50)
Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)
2 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Ordering Information
(1) Operating Ambient Temperature TA = 0 to +70°C
Part number Cycle Clock Organization Package Operating
Time Frequency (word x bit) Ambient
ns MHz Temperature
μ
PD44164082AF5-E33-EQ2-A
3.3 300 2M x 8-bit 165-pin PLASTIC Commercial
μ
PD44164082AF5-E40-EQ2-A 4.0 250 BGA (13 x 15) (TA = 0 to +70°C)
μ
PD44164082AF5-E50-EQ2-A 5.0 200
μ
PD44164092AF5-E33-EQ2-A
3.3 300 2M x 9-bit Lead-free
μ
PD44164092AF5-E40-EQ2-A 4.0 250
μ
PD44164092AF5-E50-EQ2-A 5.0 200
μ
PD44164182AF5-E33-EQ2-A
3.3 300 1M x 18-bit
μ
PD44164182AF5-E37-EQ2-A 3.7 270
μ
PD44164182AF5-E40-EQ2-A 4.0 250
μ
PD44164182AF5-E50-EQ2-A 5.0 200
μ
PD44164362AF5-E33-EQ2-A
3.3 300 512K x 36-bit
μ
PD44164362AF5-E40-EQ2-A 4.0 250
μ
PD44164362AF5-E50-EQ2-A 5.0 200
Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2. Products with -A at the end of the part number are lead-free products.
3 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
(2) Operating Ambient Temperature TA = –40 to +85°C
Part number Cycle Clock Organization Package Operating
Time Frequency (word x bit) Ambient
ns MHz Temperature
μ
PD44164082AF5-E37Y-EQ2-A 3.7 270 2M x 8-bit 165-pin PLASTIC Industrial
μ
PD44164082AF5-E40Y-EQ2-A 4.0 250 BGA (13 x 15) (TA = –40 to +85°C)
μ
PD44164082AF5-E50Y-EQ2-A 5.0 200
μ
PD44164092AF5-E37Y-EQ2-A 3.7 270 2M x 9-bit Lead-free
μ
PD44164092AF5-E40Y-EQ2-A 4.0 250
μ
PD44164092AF5-E50Y-EQ2-A 5.0 200
μ
PD44164182AF5-E37Y-EQ2-A 3.7 270 1M x 18-bit
μ
PD44164182AF5-E40Y-EQ2-A 4.0 250
μ
PD44164182AF5-E50Y-EQ2-A 5.0 200
Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2. Products with -A at the end of the part number are lead-free products.
4 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Pin Configurations
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164082A-A]
2M x 8-bit
1 2 3 4 5 6 7 8 9 10 11
A CQ# VSS A R, W# NW1# K# NC LD# A VSS CQ
B NC NC NC A NC K NW0# A NC NC DQ3
C NC NC NC VSS A A A VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS A A A VSS NC NC NC
P NC NC DQ7 A A C A A NC NC NC
R TDO TCK A A A C# A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
DQ0 to DQ7 : Data inputs / outputs TDI : IEEE 1149.1 Test input
LD# : Synchronous load TCK : IEEE 1149.1 Clock input
R, W# : Read Write input TDO : IEEE 1149.1 Test output
NW0#, NW1# : Nibble Write data select VREF : HSTL input reference input
K, K# : Input clock VDD : Power Supply
C, C# : Output clock VDDQ : Power Supply
CQ, CQ# : Echo clock VSS : Ground
ZQ : Output impedance matching NC : No connection
DLL# : DLL/PLL disable
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
5 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164092A-A]
2M x 9-bit
1 2 3 4 5 6 7 8 9 10 11
A CQ# VSS A R, W# NC K# NC LD# A VSS CQ
B NC NC NC A NC K BW0# A NC NC DQ4
C NC NC NC VSS A A A VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ5 VDDQ VSS VSS VSS VDDQ NC NC DQ3
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC NC DQ6 VDDQ VDD VSS VDD VDDQ NC NC NC
H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ2 NC
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC DQ7 NC VDDQ VSS VSS VSS VDDQ NC NC DQ1
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS A A A VSS NC NC NC
P NC NC DQ8 A A C A A NC NC DQ0
R TDO TCK A A A C# A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
DQ0 to DQ8 : Data inputs / outputs TDI : IEEE 1149.1 Test input
LD# : Synchronous load TCK : IEEE 1149.1 Clock input
R, W# : Read Write input TDO : IEEE 1149.1 Test output
BW0# : Byte Write data select VREF : HSTL input reference input
K, K# : Input clock VDD : Power Supply
C, C# : Output clock VDDQ : Power Supply
CQ, CQ# : Echo clock VSS : Ground
ZQ : Output impedance matching NC : No connection
DLL# : DLL/PLL disable
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
6 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164182A-A]
1M x 18-bit
1 2 3 4 5 6 7 8 9 10 11
A CQ# VSS A R, W# BW1# K# NC LD# A VSS CQ
B NC DQ9 NC A NC K BW0# A NC NC DQ8
C NC NC NC VSS A A0 A VSS NC DQ7 NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6
F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5
G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC
H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC
K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3
L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2
M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC
N NC NC DQ16 VSS A A A VSS NC NC NC
P NC NC DQ17 A A C A A NC NC DQ0
R TDO TCK A A A C# A A A TMS TDI
A0, A : Address inputs TMS : IEEE 1149.1 Test input
DQ0 to DQ17 : Data inputs / outputs TDI : IEEE 1149.1 Test input
LD# : Synchronous load TCK : IEEE 1149.1 Clock input
R, W# : Read Write input TDO : IEEE 1149.1 Test output
BW0#, BW1# : Byte Write data select VREF : HSTL input reference input
K, K# : Input clock VDD : Power Supply
C, C# : Output clock VDDQ : Power Supply
CQ, CQ# : Echo clock VSS : Ground
ZQ : Output impedance matching NC : No connection
DLL# : DLL/PLL disable
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
7 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164362A-A]
512K x 36-bit
1 2 3 4 5 6 7 8 9 10 11
A CQ# VSS NC R, W# BW2# K# BW1# LD# A VSS CQ
B NC DQ27 DQ18 A BW3# K BW0# A NC NC DQ8
C NC NC DQ28 VSS A A0 A VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5
G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14
H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQVREF ZQ
J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4
K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
N NC DQ35 DQ25 VSS A A A VSS NC NC DQ10
P NC NC DQ26 A A C A A NC DQ9 DQ0
R TDO TCK A A A C# A A A TMS TDI
A0, A : Address inputs TMS : IEEE 1149.1 Test input
DQ0 to DQ35 : Data inputs / outputs TDI : IEEE 1149.1 Test input
LD# : Synchronous load TCK : IEEE 1149.1 Clock input
R, W# : Read Write input TDO : IEEE 1149.1 Test output
BW0# to BW3# : Byte Write data select VREF : HSTL input reference input
K, K# : Input clock VDD : Power Supply
C, C# : Output clock VDDQ : Power Supply
CQ, CQ# : Echo clock VSS : Ground
ZQ : Output impedance matching NC : No connection
DLL# : DLL/PLL disable
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 3A and 10A are expansion addresses: 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.
2A and 10A of this product can also be used as NC.
8 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Pin Identification (1/2)
Symbol Description
A0
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used
as the lowest order address bit permitting a random starting address within the burst operation on x18 and x36
devices. These inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH).
DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output
data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied to HIGH.
x8 device uses DQ0 to DQ7.
x9 device uses DQ0 to DQ8.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
LD# Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus
activity).
R, W# Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#
is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times
around the rising edge of K.
BWx#
NWx#
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
K, K# Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock rising edges.
C, C# Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
C# is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and
C# are fixed to HIGH (i.e. toggle of C and C#).
9 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
(2/2)
Symbol Description
CQ, CQ# Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ
tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also
stop.
ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be
connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon
power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new
output impedance is reset by implementing power-on sequence.
DLL# DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics
cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a
10 kΩ or less resistor.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO IEEE 1149.1 Test Output: 1.8 V I/O level.
VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
VDD Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for
range.
VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended
DC Operating Conditions and DC Characteristics for range.
VSS Power Supply: Ground
NC No Connect: These signals are not connected internally.
10 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Block Diagram
2 : 1
MUX
0
1
/A0'
A0'
/A0'
A0'
0
1
Input
Register
E
K#
R, W#`
Input
Register
E
Write address
Register
E
K
R, W#
Register
E
Output control
Logic
C# C
Address
Register
E
LD#
Address
A0'' A0'''
Compare
Output Buffer
ZQ
DQ
Output Enable
Register
C
Burst
Logic
D0 Q0
A0
CLK
A0'
WRITE Register
Memory
Array
WRITE Driver
Sense Amps
Output Register
A0'
CLK K
E
A0'''
R
W#
11 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Power-on Sequence
The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after
VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable.
1. Clock starts after VDD/VDDQ stable
The clock is supplied from a controller.
(a)
V
DD
/V
DD
Q
V
DD
/V
DD
Q Stable (< ±0.1 V DC per 50 ns)
DLL#
Clock Start Normal Operation
Start
Clock
Fix HIGH (or tied to V
DD
Q)
20 ns (MIN.)
1,024 cycles or more
Stable Clock
Note
Note Input a stable clock from the start.
(b)
VDD/VDDQ
DLL# Switched to HIGH after Clock is stable.
Unstable Clock
(level, frequency)
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Clock
Clock Start
Normal Operation
Start
1,024 cycles or more
Stable Clock
(c)
V
DD
/V
DD
Q
DLL#
30 ns. (MIN.)
Clock Stop
V
DD
/V
DD
Q Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to V
DD
Q)
Unstable Clock
(level, frequency)
Clock
Clock Start
Normal Operation
Start
1,024 cycles or more
Stable Clock
12 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
2. Clock starts before VDD/VDDQ stable
The clock is supplied from a clock generator.
(a)
V
DD
/V
DD
Q
DLL#
30 ns. (MIN.)
Clock Stop
V
DD
/V
DD
Q Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to V
DD
Q)
Unstable Clock
(level, frequency)
Clock
Clock Start
Normal Operation Start1,024 cycles or more
Stable Clock
(b)
V
DD
/V
DD
Q
DLL#
Clock keep running
Switched to HIGH after Clock is stable.
HIGH or LOW
30 ns (MIN.)
DLL# LOW
V
DD
/V
DD
Q Stable (< ±0.1 V DC per 50 ns)
Normal
Operation
Start
1,024 cycles or more
Stable Clock
Unstable Clock
(level, frequency)
Clock
Clock Start
13 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Burst Sequence
Linear Burst Sequence Table
[
μ
PD44164182A-A,
μ
PD44164362A-A]
A0 A0
External Address 0 1
1st Internal Burst Address 1 0
Truth Table
Operation LD# R, W# CLK DQ
WRITE cycle L L L H Data in
Load address, input write data on two Input data D(A1) D(A2)
consecutive K and K# rising edge Input clock K(t+1) K#(t+1)
READ cycle L H L H Data out
Load address, read data on two Output data Q(A1) Q(A2)
consecutive C and C# rising edge Output clock C#(t+1) C(t+2)
NOP (No operation) H X L H High-Z
Clock stop X X Stopped Previous state
Remarks 1. H : HIGH, L : LOW, × : don’t care, : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
address in accordance with the linear burst sequence.
7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
14 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Byte Write Operation
[
μ
PD44164082A-A]
Operation K K# NW0# NW1#
Write DQ0 to DQ7 L H 0 0
L H 0 0
Write DQ0 to DQ3 L H 0 1
L H 0 1
Write DQ4 to DQ7 L H 1 0
L H 1 0
Write nothing L H 1 1
L H 1 1
Remarks 1. H : HIGH, L : LOW, : rising edge.
2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[
μ
PD44164092A-A]
Operation K K# BW0#
Write DQ0 to DQ8 L H 0
L H 0
Write nothing L H 1
L H 1
Remarks 1. H : HIGH, L : LOW, : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[
μ
PD44164182A-A]
Operation K K# BW0# BW1#
Write DQ0 to DQ17 L H 0 0
L H 0 0
Write DQ0 to DQ8 L H 0 1
L H 0 1
Write DQ9 to DQ17 L H 1 0
L H 1 0
Write nothing L H 1 1
L H 1 1
Remarks 1. H : HIGH, L : LOW, : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
15 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
[
μ
PD44164362A-A]
Operation K K# BW0# BW1# BW2# BW3#
Write DQ0 to DQ35 L H 0 0 0 0
L H 0 0 0 0
Write DQ0 to DQ8 L H 0 1 1 1
L H 0 1 1 1
Write DQ9 to DQ17 L H 1 0 1 1
L H 1 0 1 1
Write DQ18 to DQ26 L H 1 1 0 1
L H 1 1 0 1
Write DQ27 to DQ35 L H 1 1 1 0
L H 1 1 1 0
Write nothing L H 1 1 1 1
L H 1 1 1 1
Remarks 1. H : HIGH, L : LOW, : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
16 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Bus Cycle State Diagram
READ DOUBLE
Count = Count + 2 WRITE DOUBLE
Count = Count + 2
Power UP
Write
NOP
Supply voltage provided
LOAD NEW
ADDRESS
Count = 0
NOP
Load, Count = 2
Read
Load, Count = 2
Load
NOP,
Count = 2
NOP,
Count = 2
Remarks 1. A0 is internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 2.
2. State machine control timing sequence is controlled by K.
17 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply voltage VDD –0.5 +2.5 V
Output supply voltage VDDQ –0.5 VDD V
Input voltage VIN –0.5 VDD + 0.5 (2.5 V MAX.) V
Input / Output voltage VI/O –0.5 VDDQ + 0.5 (2.5 V MAX.) V
Operating ambient temperature TA Commercial 0 +70 °C
Industrial –40 +85
Storage temperature Tstg –55 +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Supply voltage VDD 1.7 1.9 V
Output supply voltage VDDQ 1.4 VDD V 1
Input HIGH voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 1, 2
Input LOW voltage VIL (DC) –0.3 VREF – 0.1 V 1, 2
Clock input voltage VIN –0.3 VDDQ + 0.3 V 1, 2
Reference voltage VREF 0.68 0.95 V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms
Recommended AC Operating Conditions
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Input HIGH voltage VIH (AC) VREF + 0.2 V 1
Input LOW voltage VIL (AC) VREF – 0.2 V 1
Note 1. Overshoot: VIH (AC) VDD + 0.7 V (2.5 V MAX.) for t TKHKH/2
Undershoot: VIL (AC) – 0.5 V for t TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
18 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
DC Characteristics (VDD = 1.8 ± 0.1 V)
Parameter Symbol Test condition MIN. TYP. MAX. Unit Note
x8, x9 x18 x36
Input leakage current ILI –2 +2
μ
A
I/O leakage current ILO –2 +2
μ
A
Operating supply IDD Note1 Commercial -E33 480 520 610 mA
current (TA = 0 to +70°C) -E37 490
(Read cycle/ -E40 440 470 540
Write cycle) -E50 400 420 470
Industrial -E37Y 470 510
(TA = –40 to +85°C) -E40Y 460 490
-E50Y 420 440
Standby supply ISB1 Note1 Commercial -E33 300 300 300 mA
current (TA = 0 to +70°C) -E37 290
(NOP) -E40 280 280 280
-E50 260 260 260
Industrial -E37Y 310 310
(TA = –40 to +85°C) -E40Y 300 300
-E50Y 280 280
Output HIGH voltage VOH(Low) |IOH| 0.1 mA VDDQ – 0.2 VDDQ V 4, 5
VOH Note2 VDDQ/2–0.12 – VDDQ/2+0.12 V 4, 5
Output LOW voltage VOL(Low) IOL 0.1 mA VSS 0.2 V 4, 5
VOL Note3 VDDQ/2–0.12 – VDDQ/2+0.12 V 4, 5
Notes 1. VIN VIL or VIN VIH, II/O = 0 mA, Cycle = MAX.
2. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15 % for values of 175 Ω RQ 350 Ω.
3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15 % for values of 175 Ω RQ 350 Ω.
4. AC load current is higher than the shown DC values.
5. HSTL outputs meet JEDEC HSTL Class I and standards.
Capacitance (TA = 25°C, f = 1MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input capacitance (Address, Control) CIN VIN = 0 V 4 5 pF
Input / Output capacitance CI/O VI/O = 0 V 6 7 pF
(DQ, CQ, CQ#)
Clock Input capacitance Cclk Vclk = 0 V 5 6 pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Resistance
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Thermal resistance
θ
j-a 25.1 °C/W
(junction – ambient)
Thermal resistance
θ
j-c 2.8 °C/W
(junction – case)
Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.
19 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
AC Characteristics (VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time 0.3 ns)
0.75 V 0.75 V
Test Points
1.25 V
0.25 V
Output waveform
V
DD
Q / 2 V
DD
Q / 2
Test Points
Output load condition
Figure 1. External load at test
V
DD
Q / 2
0.75 V 50 Ω
Z
O
= 50 Ω
250 Ω
SRAM
V
REF
ZQ
20 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Read and Write Cycle
Parameter Symbol -E33 -E37, -E37Y -E40, -E40Y -E50, -E50Y Unit Note
(300 MHz) (270 MHz) (250 MHz) (200 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time (K, K#, C, C#) TKHKH 3.3 8.4 3.7 8.4 4.0 8.4 5.0 8.4 ns 1
Clock phase jitter (K, K#, C, C#) TKC var – 0.2 0.2 – 0.2 0.2 ns 2
Clock HIGH time (K, K#, C, C#) TKHKL 1.32 – 1.5 1.6 – 2.0 – ns
Clock LOW time (K, K#, C, C#) TKLKH 1.32 – 1.5 1.6 – 2.0 – ns
Clock HIGH to Clock# HIGH TKHK#H 1.49 – 1.7 1.8 – 2.2 – ns
(KK#, CC#)
Clock# HIGH to Clock HIGH TK#HKH 1.49 – 1.7 1.8 – 2.2 – ns
(K#K, C#C)
Clock to data clock 270 to 300 MHz TKHCH 0 1.45 ns
(KC, K#C#) 250 to 270 MHz 0 1.65 0 1.65
200 to 250 MHz 0 1.8 0 1.8 0 1.8
167 to 200 MHz 0 2.3 0 2.3 0 2.3 0 2.3
133 to 167 MHz 0 2.8 0 2.8 0 2.8 0 2.8
< 133 MHz 0 3.55 0 3.55 0 3.55 0 3.55
DLL/PLL lock time (K, C) TKC lock 1,024 – 1,024 1,024 1,024 – Cycle 3
K static to DLL/PLL reset TKC reset 30 – 30 – 30 30 – ns 4
Output Times
C, C# HIGH to output valid TCHQV – 0.45 0.45 – 0.45 0.45 ns
C, C# HIGH to output hold TCHQX – 0.45 0.45 0.45 – – 0.45 – ns
C, C# HIGH to echo clock valid TCHCQV – 0.45 0.45 – 0.45 0.45 ns
C, C# HIGH to echo clock hold TCHCQX – 0.45 0.45 0.45 – – 0.45 – ns
CQ, CQ# HIGH to output valid TCQHQV – 0.27 0.3 0.3 0.35 ns 5
CQ, CQ# HIGH to output hold TCQHQX – 0.27 0.3 – 0.3 – 0.35 ns 5
C HIGH to output High-Z TCHQZ – 0.45 0.45 – 0.45 0.45 ns
C HIGH to output Low-Z TCHQX1 – 0.45 0.45 0.45 – – 0.45 – ns
Setup Times
Address valid to K rising edge TAVKH 0.4 – 0.5 0.5 – 0.6 – ns 6
Synchronous load input (LD#), TIVKH 0.4 – 0.5 0.5 – 0.6 – ns 6
read write input (R, W#) valid to
K rising edge
Data inputs and write data select TDVKH 0.3 – 0.35 0.35 – 0.4 – ns 6
inputs (BWx#, NWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold TKHAX 0.4 – 0.5 0.5 – 0.6 – ns 6
K rising edge to TKHIX 0.4 – 0.5 0.5 – 0.6 – ns 6
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs and TKHDX 0.3 – 0.35 0.35 – 0.4 – ns 6
write data select inputs (BWx#, NWx#)
hold
21 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.5 clock in
this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. V
DD slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.
DLL/PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
K
TKC reset
or
TKC reset
5. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
6. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
22 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Read and Write Timing
TKHKH
TKHAX
Q01 Q11
K
LD#
Address
DQ
Q02
K#
24 681013579
R, W#
A0 A1 A2
Qx2
Q12
TKHK#H
CQ
CQ#
C
C#
TKHCH
TCHQX1
TCHQV TCHQV
TCHQX TCHQZ
TKHKLTKLKH TKHKH TKHK#H
D21 D31D22 D32
TDVKH
TKHDX
TDVKH
TKHDX
NOP READ
(burst of 2) READ
(burst of 2) NOP NOP WRITE
(burst of 2) WRITE
(burst of 2)
TKHKL
TIVKH
TKLKH
TKHIX
TKLKH
TCHCQV
TCHCQV
TCHCQX
TCHCQX
TCQHQX
TCQHQV
READ
(burst of 2)
A3 A4
TCHQX
Q41 Q42
TK#HKH
TKHCH
TAVKH
TK#HKH
Remarks 1. Q01 refers to output from address A0.
Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high impedance) 2.5 clocks after the last READ (LD# = LOW, R, W# = HIGH) is
input in the sequences of [READ]-[NOP].
3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;
however, at high clock frequencies it may be required to prevent bus contention.
23 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Application Example
SRAM
Controller
Data IO
Address
LD#
R, W#
BW#
SRAM#1 CQ/CQ#
SRAM#4 CQ/CQ#
Source CLK/CLK#
Return CLK/CLK#
ZQ
CQ#
CQ
SRAM#4
DQ
A LD# R, W# BWx# C/C# K/K#
R
RV
t
V
t
RV
t
RV
t
RV
t
R =
250 ΩR =
250 Ω
ZQ
CQ#
CQ
SRAM#1
DQ
A LD# R, W#BWx# C/C# K/K#
R = 50 Ω V
t
= V
ref
. . .
. . .
Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.
24 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name Pin assignments Description
TCK 2R Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS 10R Test Mode Select. This is the command input for the TAP controller state machine.
TDI 11R Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO 1R Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
JTAG Input leakage current ILI 0 V VIN VDD –5.0 +5.0
μ
A
JTAG I/O leakage current ILO 0 V VIN VDDQ, –5.0 +5.0
μ
A
Outputs disabled
JTAG input HIGH voltage VIH 1.3 VDD+0.3 V
JTAG input LOW voltage VIL –0.3 +0.5 V
JTAG output HIGH voltage VOH1 | IOHC | = 100
μ
A 1.6 V
VOH2 | IOHT | = 2 mA 1.4 V
JTAG output LOW voltage VOL1 IOLC = 100
μ
A – 0.2 V
VOL2 IOLT = 2 mA 0.4 V
25 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
JTAG AC Test Conditions
Input waveform (Rise / Fall time 1 ns)
0.9 V 0.9 V
Test Points
1.8 V
0 V
Output waveform
0.9 V 0.9 V
Test Points
Output load
Figure 2. External load at test
TDO Z
O
= 50 Ω
V
TT
= 0.9 V
20 pF
50 Ω
26 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
JTAG AC Characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Clock
Clock cycle time tTHTH 50 ns
Clock frequency fTF 20 MHz
Clock HIGH time tTHTL 20 ns
Clock LOW time tTLTH 20 ns
Output time
TCK LOW to TDO unknown tTLOX 0 – – ns
TCK LOW to TDO valid tTLOV 10 ns
Setup time
TMS setup time tMVTH 5 – – ns
TDI valid to TCK HIGH tDVTH 5 – – ns
Capture setup time tCS 5 – – ns
Hold time
TMS hold time tTHMX 5 – – ns
TCK HIGH to TDI invalid tTHDX 5 – – ns
Capture hold time tCH 5 – – ns
JTAG Timing Diagram
t
THTH
t
TLOV
t
TLTH
t
THTL
t
MVTH
t
THDX
t
DVTH
t
THMX
TCK
TMS
TDI
TDO
t
TLOX
27 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Scan Register Definition (1)
Register name Description
Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name Bit size Unit
Instruction register 3 bit
Bypass register 1 bit
ID register 32 bit
Boundary register 107 bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit
μ
PD44164082A-A 2M x 8 XXXX 0000 0000 0001 0010 00000010000 1
μ
PD44164092A-A 2M x 9 XXXX 0000 0000 0101 0011 00000010000 1
μ
PD44164182A-A 1M x 18 XXXX 0000 0000 0001 0011 00000010000 1
μ
PD44164362A-A 512K x 36 XXXX 0000 0000 0001 0100 00000010000 1
28 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
SCAN Exit Order
Bit Signal name Bump Bit Signal name Bump Bit Signal name Bump
no. x8 x9 x18 x36 ID no. x8 x9 x18 x36 ID no. x8 x9 x18 x36 ID
1 C# 6R 37 NC NC NC NC 10D 73 NC NC NC NC 2C
2 C 6P 38 NC NC NC NC 9E 74 DQ4 DQ5 DQ11 DQ20 3E
3 A 6N 39 NC NC DQ7 DQ17 10C 75 NC NC NC DQ29 2D
4 A 7P 40 NC NC NC DQ16 11D 76 NC NC NC NC 2E
5 A 7N 41 NC NC NC NC 9C 77 NC NC NC NC 1E
6 A 7R 42 NC NC NC NC 9D 78 NC NC DQ12 DQ30 2F
7 A 8R 43 DQ3 DQ4 DQ8 DQ8 11B 79 NC NC NC DQ21 3F
8 A 8P 44 NC NC NC DQ7 11C 80 NC NC NC NC 1G
9 A 9R 45 NC NC NC NC 9B 81 NC NC NC NC 1F
10 NC DQ0 DQ0 DQ0 11P 46 NC NC NC NC 10B 82 DQ5 DQ6 DQ13 DQ22 3G
11 NC NC NC DQ9 10P 47 CQ 11A 83 NC NC NC DQ31 2G
12 NC NC NC NC 10N 48 Internal 84 NC NC NC NC 1J
13 NC NC NC NC 9P 49 A 9A 85 NC NC NC NC 2J
14 NC NC DQ1 DQ11 10M 50 A 8B 86 NC NC DQ14 DQ23 3K
15 NC NC NC DQ10 11N 51 A 7C 87 NC NC NC DQ32 3J
16 NC NC NC NC 9M 52 A A A0 A0 6C 88 NC NC NC NC 2K
17 NC NC NC NC 9N 53 LD# 8A 89 NC NC NC NC 1K
18 DQ0 DQ1 DQ2 DQ2 11L 54 NC NC NC BW1# 7A 90 DQ6 DQ7 DQ15 DQ33 2L
19 NC NC NC DQ1 11M 55 NW0# BW0# BW0# BW0# 7B 91 NC NC NC DQ24 3L
20 NC NC NC NC 9L 56 K 6B 92 NC NC NC NC 1M
21 NC NC NC NC 10L 57 K# 6A 93 NC NC NC NC 1L
22 NC NC DQ3 DQ3 11K 58 NC NC NC BW3# 5B 94 NC NC DQ16 DQ25 3N
23 NC NC NC DQ12 10K 59 NW1# NC BW1# BW2# 5A 95 NC NC NC DQ34 3M
24 NC NC NC NC 9J 60 R, W# 4A 96 NC NC NC NC 1N
25 NC NC NC NC 9K 61 A 5C 97 NC NC NC NC 2M
26 DQ1 DQ2 DQ4 DQ13 10J 62 A 4B 98 DQ7 DQ8 DQ17 DQ26 3P
27 NC NC NC DQ4 11J 63 A A A NC 3A 99 NC NC NC DQ35 2N
28 ZQ 11H 64 DLL# 1H 100 NC NC NC NC 2P
29 NC NC NC NC 10G 65 CQ# 1A 101 NC NC NC NC 1P
30 NC NC NC NC 9G 66 NC NC DQ9 DQ27 2B 102 A 3R
31 NC NC DQ5 DQ5 11F 67 NC NC NC DQ18 3B 103 A 4R
32 NC NC NC DQ14 11G 68 NC NC NC NC 1C 104 A 4P
33 NC NC NC NC 9F 69 NC NC NC NC 1B 105 A 5P
34 NC NC NC NC 10F 70 NC NC DQ10 DQ19 3D 106 A 5N
35 DQ2 DQ3 DQ6 DQ6 11E 71 NC NC NC DQ28 3C 107 A 5R
36 NC NC NC DQ15 10E 72 NC NC NC NC 1D
29 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
JTAG Instructions
Instructions Description
EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.
BYPASS When the BYPASS instruction is loaded in the instruction register, the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2 IR1 IR0 Instruction Note
0 0 0 EXTEST
0 0 1 IDCODE
0 1 0 SAMPLE-Z 1
0 1 1 RESERVED 2
1 0 0 SAMPLE / PRELOAD
1 0 1 RESERVED 2
1 1 0 RESERVED 2
1 1 1 BYPASS
Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
30 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Output Pin States of CQ, CQ# and DQ
Instructions Control-Register Status Output Pin Status
CQ, CQ# DQ
EXTEST 0 Update High-Z
1 Update Update
IDCODE 0 SRAM SRAM
1 SRAM SRAM
SAMPLE-Z 0 High-Z High-Z
1 High-Z High-Z
SAMPLE 0 SRAM SRAM
1 SRAM SRAM
BYPASS 0 SRAM SRAM
1 SRAM SRAM
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 48).
There are three statuses:
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
SRAM
CAPTURE
Register
Boundary Scan
Register
Update
Register
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
High-Z
Update
SRAM
Output
31 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Boundary Scan Register Status of Output Pins CQ, CQ# and DQ
Instructions SRAM Status Boundary Scan Register Status Note
CQ, CQ# DQ
EXTEST READ (Low-Z) Pad Pad
NOP (High-Z) Pad Pad
IDCODE READ (Low-Z) No definition
NOP (High-Z)
SAMPLE-Z READ (Low-Z) Pad Pad
NOP (High-Z) Pad Pad
SAMPLE READ (Low-Z) Internal Internal
NOP (High-Z) Internal Pad
BYPASS READ (Low-Z) No definition
NOP (High-Z)
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
There are two statuses:
Pad : Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
Pad
Internal
SRAM
Output
Driver
Update
Register
QDR
Pad
High-Z
JTAG ctrl
CAPTURE
Register
SRAM
Output
Boundary Scan
Register
32 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
TAP Controller State Diagram
Test-Logic-Reset
Run-Test / Idle Select-DR-Scan
Capture-DR Capture-IR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Select-IR-Scan
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
10 10
11 1
0
1
1
0
1
0
11
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix
them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also
when the TAP controller is not used.
33 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Test Logic Operation (Instruction Scan)
TCK
Controller
state
TDI
TMS
TDO
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Shift-IR
Exit1-IR
Update-IR
Run-Test/Idle
IDCODE
Instruction
Register state New Instruction
Output Inactive
34 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Test Logic (Data Scan)
Controller
state
TDI
TMS
TDO
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Shift-DR
Exit1-DR
Update-DR
Test-Logic-Reset
Instruction
Instruction
Register state IDCODE
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Output Inactive
TCK
35 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Package Drawing
165-PIN PLASTIC BGA (13x15)
ITEM DIMENSIONS
D
E
w
e
A
A1
A2
13.00±0.10
15.00±0.10
0.15
0.40±0.05
1.00
1.40±0.11
1.00
0.50±0.05
(UNIT:mm)
0.08
0.10
0.20
1.50
0.50
P165F5-100-EQ2
x
y
y1
ZD
ZE
b
A
11
10
9
8
7
6
5
4
3
2
1
INDEX MARK
ZE
ZD B
SwB
E
SwA
D
S
y
S
A
A2
A1
e
y1 S
SxbA
B
M
φφ
RPNMLKJHGFEDCBA
36 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μ
PD44164082AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μ
PD44164092AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μ
PD44164182AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μ
PD44164362AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
Quality Grade
A quality grade of the products is “Standard”.
Anti-radioactive design is not implemented in the products.
Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the
ground and so forth.
37 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
[ MEMO ]
38 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
[ MEMO ]
39 Data Sheet M19866EJ1V0DS
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
μ
PD44164082A-A, 44164092A-A, 44164182A-A, 44164362A-A
The information in this document is current as of July, 2009. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets,
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types are available in every country. Please check with an NEC Electronics sales representative for
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No part of this document may be copied or reproduced in any form or by any means without the prior
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(Note)
M8E0904E
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
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"Standard":
"Special":
"Specific":